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ARM: 9034/1: __div64_32(): straighten up inline asm constraints

The ARM version of __div64_32() encapsulates a call to __do_div64 with
non-standard argument passing. In particular, __n is a 64-bit input
argument assigned to r0-r1 and __rem is an output argument sharing half
of that r0-r1 register pair.

With __n being an input argument, the compiler is in its right to
presume that r0-r1 would still hold the value of __n past the inline
assembly statement. Normally, the compiler would have assigned non
overlapping registers to __n and __rem if the value for __n is needed
again.

However, here we enforce our own register assignment and gcc fails to
notice the conflict. In practice this doesn't cause any problem as __n
is considered dead after the asm statement and *n is overwritten.
However this is not always guaranteed and clang rightfully complains.

Let's fix it properly by making __n into an input-output variable. This
makes it clear that those registers representing __n have been modified.
Then we can extract __rem as the high part of __n with plain C code.

This asm constraint "abuse" was likely relied upon back when gcc didn't
handle 64-bit values optimally. Turns out that gcc is now able to
optimize things and produces the same code with this patch applied.

Reported-by: Antony Yu <swpenim@gmail.com>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

authored by

Nicolas Pitre and committed by
Russell King
e64ab473 9fa2e7af

+6 -15
+6 -15
arch/arm/include/asm/div64.h
··· 21 21 * assembly implementation with completely non standard calling convention 22 22 * for arguments and results (beware). 23 23 */ 24 - 25 - #ifdef __ARMEB__ 26 - #define __xh "r0" 27 - #define __xl "r1" 28 - #else 29 - #define __xl "r0" 30 - #define __xh "r1" 31 - #endif 32 - 33 24 static inline uint32_t __div64_32(uint64_t *n, uint32_t base) 34 25 { 35 26 register unsigned int __base asm("r4") = base; 36 27 register unsigned long long __n asm("r0") = *n; 37 28 register unsigned long long __res asm("r2"); 38 - register unsigned int __rem asm(__xh); 39 - asm( __asmeq("%0", __xh) 29 + unsigned int __rem; 30 + asm( __asmeq("%0", "r0") 40 31 __asmeq("%1", "r2") 41 - __asmeq("%2", "r0") 42 - __asmeq("%3", "r4") 32 + __asmeq("%2", "r4") 43 33 "bl __do_div64" 44 - : "=r" (__rem), "=r" (__res) 45 - : "r" (__n), "r" (__base) 34 + : "+r" (__n), "=r" (__res) 35 + : "r" (__base) 46 36 : "ip", "lr", "cc"); 37 + __rem = __n >> 32; 47 38 *n = __res; 48 39 return __rem; 49 40 }