···83838484/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */8585#define bfin_read_SWRST() bfin_read_SICA_SWRST()8686-#define bfin_write_SWRST() bfin_write_SICA_SWRST()8686+#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)8787#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()8888-#define bfin_write_SYSCR() bfin_write_SICA_SYSCR()8888+#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)89899090/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */9191#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)