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Blackfin arch: fix the aliased write macros

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>

authored by

Robin Getz and committed by
Bryan Wu
e62687f9 4bbd10fd

+2 -2
+2 -2
include/asm-blackfin/mach-bf561/cdefBF561.h
··· 83 83 84 84 /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 85 85 #define bfin_read_SWRST() bfin_read_SICA_SWRST() 86 - #define bfin_write_SWRST() bfin_write_SICA_SWRST() 86 + #define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) 87 87 #define bfin_read_SYSCR() bfin_read_SICA_SYSCR() 88 - #define bfin_write_SYSCR() bfin_write_SICA_SYSCR() 88 + #define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) 89 89 90 90 /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 91 91 #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)