Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17

Renesas RZ/T2H DT Binding Definitions

DT bindings and binding definitions for the Renesas RZ/T2H (R9A09G077)
SoC, shared by driver and DT source files.

+62 -11
+35 -11
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
··· 52 52 - renesas,r8a779f0-cpg-mssr # R-Car S4-8 53 53 - renesas,r8a779g0-cpg-mssr # R-Car V4H 54 54 - renesas,r8a779h0-cpg-mssr # R-Car V4M 55 + - renesas,r9a09g077-cpg-mssr # RZ/T2H 55 56 56 57 reg: 57 - maxItems: 1 58 + minItems: 1 59 + items: 60 + - description: base address of register block 0 61 + - description: base address of register block 1 62 + description: base addresses of clock controller. Some controllers 63 + (like r9a09g077) use two blocks instead of a single one. 58 64 59 65 clocks: 60 66 minItems: 1 ··· 98 92 the datasheet. 99 93 const: 1 100 94 101 - if: 102 - not: 103 - properties: 104 - compatible: 105 - items: 106 - enum: 107 - - renesas,r7s9210-cpg-mssr 108 - then: 109 - required: 110 - - '#reset-cells' 111 95 112 96 required: 113 97 - compatible ··· 106 110 - clock-names 107 111 - '#clock-cells' 108 112 - '#power-domain-cells' 113 + 114 + allOf: 115 + - if: 116 + properties: 117 + compatible: 118 + contains: 119 + const: renesas,r9a09g077-cpg-mssr 120 + then: 121 + properties: 122 + reg: 123 + minItems: 2 124 + clock-names: 125 + items: 126 + - const: extal 127 + else: 128 + properties: 129 + reg: 130 + maxItems: 1 131 + - if: 132 + not: 133 + properties: 134 + compatible: 135 + items: 136 + enum: 137 + - renesas,r7s9210-cpg-mssr 138 + then: 139 + required: 140 + - '#reset-cells' 109 141 110 142 additionalProperties: false 111 143
+27
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + * 3 + * Copyright (C) 2025 Renesas Electronics Corp. 4 + */ 5 + 6 + #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 7 + #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 8 + 9 + #include <dt-bindings/clock/renesas-cpg-mssr.h> 10 + 11 + /* R9A09G077 CPG Core Clocks */ 12 + #define R9A09G077_CLK_CA55C0 0 13 + #define R9A09G077_CLK_CA55C1 1 14 + #define R9A09G077_CLK_CA55C2 2 15 + #define R9A09G077_CLK_CA55C3 3 16 + #define R9A09G077_CLK_CA55S 4 17 + #define R9A09G077_CLK_CR52_CPU0 5 18 + #define R9A09G077_CLK_CR52_CPU1 6 19 + #define R9A09G077_CLK_CKIO 7 20 + #define R9A09G077_CLK_PCLKAH 8 21 + #define R9A09G077_CLK_PCLKAM 9 22 + #define R9A09G077_CLK_PCLKAL 10 23 + #define R9A09G077_CLK_PCLKGPTL 11 24 + #define R9A09G077_CLK_PCLKH 12 25 + #define R9A09G077_CLK_PCLKM 13 26 + 27 + #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */