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Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17
Renesas RZ/T2H DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/T2H (R9A09G077)
SoC, shared by driver and DT source files.
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-11
+35
-11
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+35
-11
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
···
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- renesas,r8a779f0-cpg-mssr # R-Car S4-8
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- renesas,r8a779g0-cpg-mssr # R-Car V4H
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- renesas,r8a779h0-cpg-mssr # R-Car V4M
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+
- renesas,r9a09g077-cpg-mssr # RZ/T2H
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reg:
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-
maxItems: 1
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minItems: 1
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items:
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- description: base address of register block 0
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- description: base address of register block 1
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description: base addresses of clock controller. Some controllers
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(like r9a09g077) use two blocks instead of a single one.
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clocks:
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minItems: 1
···
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the datasheet.
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const: 1
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-
if:
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not:
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properties:
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compatible:
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items:
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enum:
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- renesas,r7s9210-cpg-mssr
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then:
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required:
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- '#reset-cells'
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required:
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- compatible
···
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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+
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a09g077-cpg-mssr
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then:
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properties:
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reg:
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minItems: 2
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clock-names:
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items:
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- const: extal
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else:
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properties:
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reg:
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maxItems: 1
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- if:
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not:
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properties:
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compatible:
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items:
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enum:
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- renesas,r7s9210-cpg-mssr
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then:
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required:
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- '#reset-cells'
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additionalProperties: false
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+27
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
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include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
···
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
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#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* R9A09G077 CPG Core Clocks */
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#define R9A09G077_CLK_CA55C0 0
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#define R9A09G077_CLK_CA55C1 1
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#define R9A09G077_CLK_CA55C2 2
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#define R9A09G077_CLK_CA55C3 3
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#define R9A09G077_CLK_CA55S 4
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#define R9A09G077_CLK_CR52_CPU0 5
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#define R9A09G077_CLK_CR52_CPU1 6
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#define R9A09G077_CLK_CKIO 7
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#define R9A09G077_CLK_PCLKAH 8
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#define R9A09G077_CLK_PCLKAM 9
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#define R9A09G077_CLK_PCLKAL 10
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#define R9A09G077_CLK_PCLKGPTL 11
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#define R9A09G077_CLK_PCLKH 12
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#define R9A09G077_CLK_PCLKM 13
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */