tjh.dev / kernel
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powerpc: Fixes for instructions not using correct register naming

These macros are using integers where they could be using logical
names since they take registers.

We are going to enforce this soon, so fix these up now.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

authored by

Michael Neuling and committed by
Benjamin Herrenschmidt e55174e9 03a22bfc

+13 -13
+4 -4
arch/powerpc/kernel/exceptions-64e.S
··· 903 903 bne 1b /* If not, repeat */ 904 904 905 905 /* Invalidate all TLBs */ 906 - PPC_TLBILX_ALL(0,0) 906 + PPC_TLBILX_ALL(R0,R0) 907 907 sync 908 908 isync 909 909 ··· 961 961 tlbwe 962 962 963 963 /* Invalidate TLB1 */ 964 - PPC_TLBILX_ALL(0,0) 964 + PPC_TLBILX_ALL(R0,R0) 965 965 sync 966 966 isync 967 967 ··· 1020 1020 tlbwe 1021 1021 1022 1022 /* Invalidate TLB1 */ 1023 - PPC_TLBILX_ALL(0,0) 1023 + PPC_TLBILX_ALL(R0,R0) 1024 1024 sync 1025 1025 isync 1026 1026 ··· 1138 1138 tlbwe 1139 1139 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */ 1140 1140 1141 - PPC_TLBILX(0,0,0) 1141 + PPC_TLBILX(0,R0,R0) 1142 1142 sync 1143 1143 isync 1144 1144
+2 -2
arch/powerpc/kernel/misc_64.S
··· 309 309 mtmsrd r0 310 310 sync 311 311 isync 312 - LBZCIX(R3,0,R3) 312 + LBZCIX(R3,R0,R3) 313 313 isync 314 314 mtmsrd r7 315 315 sync ··· 324 324 mtmsrd r0 325 325 sync 326 326 isync 327 - STBCIX(R3,0,R4) 327 + STBCIX(R3,R0,R4) 328 328 isync 329 329 mtmsrd r7 330 330 sync
+2 -2
arch/powerpc/lib/ldstfp.S
··· 332 332 beq cr7,1f 333 333 STXVD2X(0,R1,R8) 334 334 1: li r9,-EFAULT 335 - 2: LXVD2X(0,0,R4) 335 + 2: LXVD2X(0,R0,R4) 336 336 li r9,0 337 337 3: beq cr7,4f 338 338 bl put_vsr ··· 361 361 STXVD2X(0,R1,R8) 362 362 bl get_vsr 363 363 1: li r9,-EFAULT 364 - 2: STXVD2X(0,0,R4) 364 + 2: STXVD2X(0,R0,R4) 365 365 li r9,0 366 366 3: beq cr7,4f 367 367 LXVD2X(0,R1,R8)
+5 -5
arch/powerpc/mm/tlb_nohash_low.S
··· 266 266 andi. r3,r3,MMUCSR0_TLBFI@l 267 267 bne 1b 268 268 MMU_FTR_SECTION_ELSE 269 - PPC_TLBILX_ALL(0,0) 269 + PPC_TLBILX_ALL(R0,R0) 270 270 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) 271 271 msync 272 272 isync ··· 279 279 wrteei 0 280 280 mfspr r4,SPRN_MAS6 /* save MAS6 */ 281 281 mtspr SPRN_MAS6,r3 282 - PPC_TLBILX_PID(0,0) 282 + PPC_TLBILX_PID(R0,R0) 283 283 mtspr SPRN_MAS6,r4 /* restore MAS6 */ 284 284 wrtee r10 285 285 MMU_FTR_SECTION_ELSE ··· 331 331 mfmsr r10 332 332 wrteei 0 333 333 mtspr SPRN_MAS6,r4 334 - PPC_TLBILX_PID(0,0) 334 + PPC_TLBILX_PID(R0,R0) 335 335 wrtee r10 336 336 msync 337 337 isync ··· 343 343 ori r4,r4,MAS6_SIND 344 344 wrteei 0 345 345 mtspr SPRN_MAS6,r4 346 - PPC_TLBILX_PID(0,0) 346 + PPC_TLBILX_PID(R0,R0) 347 347 wrtee r10 348 348 msync 349 349 isync 350 350 blr 351 351 352 352 _GLOBAL(_tlbil_all) 353 - PPC_TLBILX_ALL(0,0) 353 + PPC_TLBILX_ALL(R0,R0) 354 354 msync 355 355 isync 356 356 blr