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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'amlogic-drivers-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/drivers
Pull "Amlogic drivers for v4.15, round 2" from Kevin Hilman:
- add PM domain driver for GX VPU
* tag 'amlogic-drivers-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
dt-bindings: power: add amlogic meson power domain bindings
soc: amlogic: add Meson GX VPU Domains driver
+306
+61
Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
+61
Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
···
1
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Amlogic Meson Power Controller
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+
==============================
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The Amlogic Meson SoCs embeds an internal Power domain controller.
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VPU Power Domain
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----------------
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The Video Processing Unit power domain is controlled by this power controller,
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but the domain requires some external resources to meet the correct power
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sequences.
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The bindings must respect the power domain bindings as described in the file
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power_domain.txt
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+
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Device Tree Bindings:
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---------------------
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Required properties:
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- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
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- #power-domain-cells: should be 0
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- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
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- resets: phandles to the reset lines needed for this power demain sequence
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as described in ../reset/reset.txt
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- clocks: from common clock binding: handle to VPU and VAPB clocks
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- clock-names: from common clock binding: must contain "vpu", "vapb"
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corresponding to entry in the clocks property.
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Parent node should have the following properties :
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- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
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- reg: base address and size of the AO system control register space.
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Example:
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-------
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ao_sysctrl: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
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reg = <0x0 0x0 0x0 0x100>;
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pwrc_vpu: power-controller-vpu {
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compatible = "amlogic,meson-gx-pwrc-vpu";
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#power-domain-cells = <0>;
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amlogic,hhi-sysctrl = <&sysctrl>;
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resets = <&reset RESET_VIU>,
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<&reset RESET_VENC>,
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<&reset RESET_VCBUS>,
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<&reset RESET_BT656>,
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<&reset RESET_DVIN_RESET>,
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<&reset RESET_RDMA>,
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<&reset RESET_VENCI>,
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<&reset RESET_VENCP>,
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<&reset RESET_VDAC>,
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<&reset RESET_VDI6>,
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<&reset RESET_VENCL>,
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<&reset RESET_VID_LOCK>;
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clocks = <&clkc CLKID_VPU>,
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<&clkc CLKID_VAPB>;
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clock-names = "vpu", "vapb";
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};
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};
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+10
drivers/soc/amlogic/Kconfig
+10
drivers/soc/amlogic/Kconfig
···
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Say yes to support decoding of Amlogic Meson GX SoC family
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information about the type, package and version.
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config MESON_GX_PM_DOMAINS
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bool "Amlogic Meson GX Power Domains driver"
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depends on ARCH_MESON || COMPILE_TEST
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default ARCH_MESON
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select PM_GENERIC_DOMAINS
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select PM_GENERIC_DOMAINS_OF
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help
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Say yes to expose Amlogic Meson GX Power Domains as
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Generic Power Domains.
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config MESON_MX_SOCINFO
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bool "Amlogic Meson MX SoC Information driver"
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depends on ARCH_MESON || COMPILE_TEST
+1
drivers/soc/amlogic/Makefile
+1
drivers/soc/amlogic/Makefile
+234
drivers/soc/amlogic/meson-gx-pwrc-vpu.c
+234
drivers/soc/amlogic/meson-gx-pwrc-vpu.c
···
1
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/*
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* Copyright (c) 2017 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/bitfield.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/reset.h>
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#include <linux/clk.h>
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/* AO Offsets */
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#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
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#define GEN_PWR_VPU_HDMI BIT(8)
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#define GEN_PWR_VPU_HDMI_ISO BIT(9)
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/* HHI Offsets */
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#define HHI_MEM_PD_REG0 (0x40 << 2)
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#define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
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#define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
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struct meson_gx_pwrc_vpu {
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struct generic_pm_domain genpd;
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struct regmap *regmap_ao;
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struct regmap *regmap_hhi;
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struct reset_control *rstc;
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struct clk *vpu_clk;
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struct clk *vapb_clk;
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bool powered;
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};
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static inline
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struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
42
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{
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return container_of(d, struct meson_gx_pwrc_vpu, genpd);
44
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}
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static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
47
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{
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struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
49
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int i;
50
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51
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
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udelay(20);
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/* Power Down Memories */
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for (i = 0; i < 32; i += 2) {
57
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
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0x2 << i, 0x3 << i);
59
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udelay(5);
60
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}
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
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0x2 << i, 0x3 << i);
64
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udelay(5);
65
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}
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for (i = 8; i < 16; i++) {
67
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regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
68
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BIT(i), BIT(i));
69
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udelay(5);
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}
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udelay(20);
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
75
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msleep(20);
77
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78
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clk_disable_unprepare(pd->vpu_clk);
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clk_disable_unprepare(pd->vapb_clk);
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pd->powered = false;
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return 0;
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}
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static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
87
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{
88
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int ret;
89
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90
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ret = clk_prepare_enable(pd->vpu_clk);
91
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if (ret)
92
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return ret;
93
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94
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return clk_prepare_enable(pd->vapb_clk);
95
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}
96
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97
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static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
98
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{
99
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struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
100
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int ret;
101
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int i;
102
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103
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI, 0);
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udelay(20);
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/* Power Up Memories */
108
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for (i = 0; i < 32; i += 2) {
109
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
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0x2 << i, 0);
111
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udelay(5);
112
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}
113
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for (i = 0; i < 32; i += 2) {
115
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
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0x2 << i, 0);
117
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udelay(5);
118
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}
119
+
120
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for (i = 8; i < 16; i++) {
121
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regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
122
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BIT(i), 0);
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udelay(5);
124
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}
125
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udelay(20);
126
+
127
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ret = reset_control_assert(pd->rstc);
128
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if (ret)
129
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return ret;
130
+
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI_ISO, 0);
133
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134
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ret = reset_control_deassert(pd->rstc);
135
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if (ret)
136
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return ret;
137
+
138
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ret = meson_gx_pwrc_vpu_setup_clk(pd);
139
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if (ret)
140
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return ret;
141
+
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pd->powered = true;
143
+
144
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return 0;
145
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}
146
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static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
148
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{
149
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u32 reg;
150
+
151
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regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, ®);
152
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153
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return (reg & GEN_PWR_VPU_HDMI);
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}
155
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static struct meson_gx_pwrc_vpu vpu_hdmi_pd = {
157
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.genpd = {
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.name = "vpu_hdmi",
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.power_off = meson_gx_pwrc_vpu_power_off,
160
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.power_on = meson_gx_pwrc_vpu_power_on,
161
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},
162
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};
163
+
164
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static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
165
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{
166
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struct regmap *regmap_ao, *regmap_hhi;
167
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struct reset_control *rstc;
168
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struct clk *vpu_clk;
169
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struct clk *vapb_clk;
170
+
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regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
172
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if (IS_ERR(regmap_ao)) {
173
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dev_err(&pdev->dev, "failed to get regmap\n");
174
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return PTR_ERR(regmap_ao);
175
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}
176
+
177
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regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
178
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"amlogic,hhi-sysctrl");
179
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if (IS_ERR(regmap_hhi)) {
180
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dev_err(&pdev->dev, "failed to get HHI regmap\n");
181
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return PTR_ERR(regmap_hhi);
182
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}
183
+
184
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rstc = devm_reset_control_array_get(&pdev->dev, false, false);
185
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if (IS_ERR(rstc)) {
186
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dev_err(&pdev->dev, "failed to get reset lines\n");
187
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return PTR_ERR(rstc);
188
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}
189
+
190
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vpu_clk = devm_clk_get(&pdev->dev, "vpu");
191
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if (IS_ERR(vpu_clk)) {
192
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dev_err(&pdev->dev, "vpu clock request failed\n");
193
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return PTR_ERR(vpu_clk);
194
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}
195
+
196
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vapb_clk = devm_clk_get(&pdev->dev, "vapb");
197
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if (IS_ERR(vapb_clk)) {
198
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dev_err(&pdev->dev, "vapb clock request failed\n");
199
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return PTR_ERR(vapb_clk);
200
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}
201
+
202
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vpu_hdmi_pd.regmap_ao = regmap_ao;
203
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vpu_hdmi_pd.regmap_hhi = regmap_hhi;
204
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vpu_hdmi_pd.rstc = rstc;
205
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vpu_hdmi_pd.vpu_clk = vpu_clk;
206
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vpu_hdmi_pd.vapb_clk = vapb_clk;
207
+
208
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pm_genpd_init(&vpu_hdmi_pd.genpd, &simple_qos_governor,
209
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meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd));
210
+
211
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return of_genpd_add_provider_simple(pdev->dev.of_node,
212
+
&vpu_hdmi_pd.genpd);
213
+
}
214
+
215
+
static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
216
+
{
217
+
if (vpu_hdmi_pd.powered)
218
+
meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
219
+
}
220
+
221
+
static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
222
+
{ .compatible = "amlogic,meson-gx-pwrc-vpu" },
223
+
{ /* sentinel */ }
224
+
};
225
+
226
+
static struct platform_driver meson_gx_pwrc_vpu_driver = {
227
+
.probe = meson_gx_pwrc_vpu_probe,
228
+
.shutdown = meson_gx_pwrc_vpu_shutdown,
229
+
.driver = {
230
+
.name = "meson_gx_pwrc_vpu",
231
+
.of_match_table = meson_gx_pwrc_vpu_match_table,
232
+
},
233
+
};
234
+
builtin_platform_driver(meson_gx_pwrc_vpu_driver);