mfd: Add support for the MediaTek MT6359 PMIC

+24

drivers/mfd/mt6358-irq.c

··· 5 5 #include <linux/interrupt.h> 6 6 #include <linux/mfd/mt6358/core.h> 7 7 #include <linux/mfd/mt6358/registers.h> 8 + #include <linux/mfd/mt6359/core.h> 9 + #include <linux/mfd/mt6359/registers.h> 8 10 #include <linux/mfd/mt6397/core.h> 9 11 #include <linux/module.h> 10 12 #include <linux/of.h> ··· 28 26 MT6358_TOP_GEN(MISC), 29 27 }; 30 28 29 + static const struct irq_top_t mt6359_ints[] = { 30 + MT6359_TOP_GEN(BUCK), 31 + MT6359_TOP_GEN(LDO), 32 + MT6359_TOP_GEN(PSC), 33 + MT6359_TOP_GEN(SCK), 34 + MT6359_TOP_GEN(BM), 35 + MT6359_TOP_GEN(HK), 36 + MT6359_TOP_GEN(AUD), 37 + MT6359_TOP_GEN(MISC), 38 + }; 39 + 31 40 static struct pmic_irq_data mt6358_irqd = { 32 41 .num_top = ARRAY_SIZE(mt6358_ints), 33 42 .num_pmic_irqs = MT6358_IRQ_NR, 34 43 .top_int_status_reg = MT6358_TOP_INT_STATUS0, 35 44 .pmic_ints = mt6358_ints, 45 + }; 46 + 47 + static struct pmic_irq_data mt6359_irqd = { 48 + .num_top = ARRAY_SIZE(mt6359_ints), 49 + .num_pmic_irqs = MT6359_IRQ_NR, 50 + .top_int_status_reg = MT6359_TOP_INT_STATUS0, 51 + .pmic_ints = mt6359_ints, 36 52 }; 37 53 38 54 static void pmic_irq_enable(struct irq_data *data) ··· 213 193 switch (chip->chip_id) { 214 194 case MT6358_CHIP_ID: 215 195 chip->irq_data = &mt6358_irqd; 196 + break; 197 + 198 + case MT6359_CHIP_ID: 199 + chip->irq_data = &mt6359_irqd; 216 200 break; 217 201 218 202 default:

+24

drivers/mfd/mt6397-core.c

··· 13 13 #include <linux/mfd/core.h> 14 14 #include <linux/mfd/mt6323/core.h> 15 15 #include <linux/mfd/mt6358/core.h> 16 + #include <linux/mfd/mt6359/core.h> 16 17 #include <linux/mfd/mt6397/core.h> 17 18 #include <linux/mfd/mt6323/registers.h> 18 19 #include <linux/mfd/mt6358/registers.h> 20 + #include <linux/mfd/mt6359/registers.h> 19 21 #include <linux/mfd/mt6397/registers.h> 20 22 21 23 #define MT6323_RTC_BASE 0x8000 ··· 101 99 }, 102 100 }; 103 101 102 + static const struct mfd_cell mt6359_devs[] = { 103 + { .name = "mt6359-regulator", }, 104 + { 105 + .name = "mt6359-rtc", 106 + .num_resources = ARRAY_SIZE(mt6358_rtc_resources), 107 + .resources = mt6358_rtc_resources, 108 + .of_compatible = "mediatek,mt6358-rtc", 109 + }, 110 + { .name = "mt6359-sound", }, 111 + }; 112 + 104 113 static const struct mfd_cell mt6397_devs[] = { 105 114 { 106 115 .name = "mt6397-rtc", ··· 159 146 .cid_shift = 8, 160 147 .cells = mt6358_devs, 161 148 .cell_size = ARRAY_SIZE(mt6358_devs), 149 + .irq_init = mt6358_irq_init, 150 + }; 151 + 152 + static const struct chip_data mt6359_core = { 153 + .cid_addr = MT6359_SWCID, 154 + .cid_shift = 8, 155 + .cells = mt6359_devs, 156 + .cell_size = ARRAY_SIZE(mt6359_devs), 162 157 .irq_init = mt6358_irq_init, 163 158 }; 164 159 ··· 239 218 }, { 240 219 .compatible = "mediatek,mt6358", 241 220 .data = &mt6358_core, 221 + }, { 222 + .compatible = "mediatek,mt6359", 223 + .data = &mt6359_core, 242 224 }, { 243 225 .compatible = "mediatek,mt6397", 244 226 .data = &mt6397_core,

+133

include/linux/mfd/mt6359/core.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2021 MediaTek Inc. 4 + */ 5 + 6 + #ifndef __MFD_MT6359_CORE_H__ 7 + #define __MFD_MT6359_CORE_H__ 8 + 9 + enum mt6359_irq_top_status_shift { 10 + MT6359_BUCK_TOP = 0, 11 + MT6359_LDO_TOP, 12 + MT6359_PSC_TOP, 13 + MT6359_SCK_TOP, 14 + MT6359_BM_TOP, 15 + MT6359_HK_TOP, 16 + MT6359_AUD_TOP = 7, 17 + MT6359_MISC_TOP, 18 + }; 19 + 20 + enum mt6359_irq_numbers { 21 + MT6359_IRQ_VCORE_OC = 1, 22 + MT6359_IRQ_VGPU11_OC, 23 + MT6359_IRQ_VGPU12_OC, 24 + MT6359_IRQ_VMODEM_OC, 25 + MT6359_IRQ_VPROC1_OC, 26 + MT6359_IRQ_VPROC2_OC, 27 + MT6359_IRQ_VS1_OC, 28 + MT6359_IRQ_VS2_OC, 29 + MT6359_IRQ_VPA_OC = 9, 30 + MT6359_IRQ_VFE28_OC = 16, 31 + MT6359_IRQ_VXO22_OC, 32 + MT6359_IRQ_VRF18_OC, 33 + MT6359_IRQ_VRF12_OC, 34 + MT6359_IRQ_VEFUSE_OC, 35 + MT6359_IRQ_VCN33_1_OC, 36 + MT6359_IRQ_VCN33_2_OC, 37 + MT6359_IRQ_VCN13_OC, 38 + MT6359_IRQ_VCN18_OC, 39 + MT6359_IRQ_VA09_OC, 40 + MT6359_IRQ_VCAMIO_OC, 41 + MT6359_IRQ_VA12_OC, 42 + MT6359_IRQ_VAUX18_OC, 43 + MT6359_IRQ_VAUD18_OC, 44 + MT6359_IRQ_VIO18_OC, 45 + MT6359_IRQ_VSRAM_PROC1_OC, 46 + MT6359_IRQ_VSRAM_PROC2_OC, 47 + MT6359_IRQ_VSRAM_OTHERS_OC, 48 + MT6359_IRQ_VSRAM_MD_OC, 49 + MT6359_IRQ_VEMC_OC, 50 + MT6359_IRQ_VSIM1_OC, 51 + MT6359_IRQ_VSIM2_OC, 52 + MT6359_IRQ_VUSB_OC, 53 + MT6359_IRQ_VRFCK_OC, 54 + MT6359_IRQ_VBBCK_OC, 55 + MT6359_IRQ_VBIF28_OC, 56 + MT6359_IRQ_VIBR_OC, 57 + MT6359_IRQ_VIO28_OC, 58 + MT6359_IRQ_VM18_OC, 59 + MT6359_IRQ_VUFS_OC = 45, 60 + MT6359_IRQ_PWRKEY = 48, 61 + MT6359_IRQ_HOMEKEY, 62 + MT6359_IRQ_PWRKEY_R, 63 + MT6359_IRQ_HOMEKEY_R, 64 + MT6359_IRQ_NI_LBAT_INT, 65 + MT6359_IRQ_CHRDET_EDGE = 53, 66 + MT6359_IRQ_RTC = 64, 67 + MT6359_IRQ_FG_BAT_H = 80, 68 + MT6359_IRQ_FG_BAT_L, 69 + MT6359_IRQ_FG_CUR_H, 70 + MT6359_IRQ_FG_CUR_L, 71 + MT6359_IRQ_FG_ZCV = 84, 72 + MT6359_IRQ_FG_N_CHARGE_L = 87, 73 + MT6359_IRQ_FG_IAVG_H, 74 + MT6359_IRQ_FG_IAVG_L = 89, 75 + MT6359_IRQ_FG_DISCHARGE = 91, 76 + MT6359_IRQ_FG_CHARGE, 77 + MT6359_IRQ_BATON_LV = 96, 78 + MT6359_IRQ_BATON_BAT_IN = 98, 79 + MT6359_IRQ_BATON_BAT_OU, 80 + MT6359_IRQ_BIF = 100, 81 + MT6359_IRQ_BAT_H = 112, 82 + MT6359_IRQ_BAT_L, 83 + MT6359_IRQ_BAT2_H, 84 + MT6359_IRQ_BAT2_L, 85 + MT6359_IRQ_BAT_TEMP_H, 86 + MT6359_IRQ_BAT_TEMP_L, 87 + MT6359_IRQ_THR_H, 88 + MT6359_IRQ_THR_L, 89 + MT6359_IRQ_AUXADC_IMP, 90 + MT6359_IRQ_NAG_C_DLTV = 121, 91 + MT6359_IRQ_AUDIO = 128, 92 + MT6359_IRQ_ACCDET = 133, 93 + MT6359_IRQ_ACCDET_EINT0, 94 + MT6359_IRQ_ACCDET_EINT1, 95 + MT6359_IRQ_SPI_CMD_ALERT = 144, 96 + MT6359_IRQ_NR, 97 + }; 98 + 99 + #define MT6359_IRQ_BUCK_BASE MT6359_IRQ_VCORE_OC 100 + #define MT6359_IRQ_LDO_BASE MT6359_IRQ_VFE28_OC 101 + #define MT6359_IRQ_PSC_BASE MT6359_IRQ_PWRKEY 102 + #define MT6359_IRQ_SCK_BASE MT6359_IRQ_RTC 103 + #define MT6359_IRQ_BM_BASE MT6359_IRQ_FG_BAT_H 104 + #define MT6359_IRQ_HK_BASE MT6359_IRQ_BAT_H 105 + #define MT6359_IRQ_AUD_BASE MT6359_IRQ_AUDIO 106 + #define MT6359_IRQ_MISC_BASE MT6359_IRQ_SPI_CMD_ALERT 107 + 108 + #define MT6359_IRQ_BUCK_BITS (MT6359_IRQ_VPA_OC - MT6359_IRQ_BUCK_BASE + 1) 109 + #define MT6359_IRQ_LDO_BITS (MT6359_IRQ_VUFS_OC - MT6359_IRQ_LDO_BASE + 1) 110 + #define MT6359_IRQ_PSC_BITS \ 111 + (MT6359_IRQ_CHRDET_EDGE - MT6359_IRQ_PSC_BASE + 1) 112 + #define MT6359_IRQ_SCK_BITS (MT6359_IRQ_RTC - MT6359_IRQ_SCK_BASE + 1) 113 + #define MT6359_IRQ_BM_BITS (MT6359_IRQ_BIF - MT6359_IRQ_BM_BASE + 1) 114 + #define MT6359_IRQ_HK_BITS (MT6359_IRQ_NAG_C_DLTV - MT6359_IRQ_HK_BASE + 1) 115 + #define MT6359_IRQ_AUD_BITS \ 116 + (MT6359_IRQ_ACCDET_EINT1 - MT6359_IRQ_AUD_BASE + 1) 117 + #define MT6359_IRQ_MISC_BITS \ 118 + (MT6359_IRQ_SPI_CMD_ALERT - MT6359_IRQ_MISC_BASE + 1) 119 + 120 + #define MT6359_TOP_GEN(sp) \ 121 + { \ 122 + .hwirq_base = MT6359_IRQ_##sp##_BASE, \ 123 + .num_int_regs = \ 124 + ((MT6359_IRQ_##sp##_BITS - 1) / \ 125 + MTK_PMIC_REG_WIDTH) + 1, \ 126 + .en_reg = MT6359_##sp##_TOP_INT_CON0, \ 127 + .en_reg_shift = 0x6, \ 128 + .sta_reg = MT6359_##sp##_TOP_INT_STATUS0, \ 129 + .sta_reg_shift = 0x2, \ 130 + .top_offset = MT6359_##sp##_TOP, \ 131 + } 132 + 133 + #endif /* __MFD_MT6359_CORE_H__ */

+529

include/linux/mfd/mt6359/registers.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2021 MediaTek Inc. 4 + */ 5 + 6 + #ifndef __MFD_MT6359_REGISTERS_H__ 7 + #define __MFD_MT6359_REGISTERS_H__ 8 + 9 + /* PMIC Registers */ 10 + #define MT6359_SWCID 0xa 11 + #define MT6359_MISC_TOP_INT_CON0 0x188 12 + #define MT6359_MISC_TOP_INT_STATUS0 0x194 13 + #define MT6359_TOP_INT_STATUS0 0x19e 14 + #define MT6359_SCK_TOP_INT_CON0 0x528 15 + #define MT6359_SCK_TOP_INT_STATUS0 0x534 16 + #define MT6359_EOSC_CALI_CON0 0x53a 17 + #define MT6359_EOSC_CALI_CON1 0x53c 18 + #define MT6359_RTC_MIX_CON0 0x53e 19 + #define MT6359_RTC_MIX_CON1 0x540 20 + #define MT6359_RTC_MIX_CON2 0x542 21 + #define MT6359_RTC_DSN_ID 0x580 22 + #define MT6359_RTC_DSN_REV0 0x582 23 + #define MT6359_RTC_DBI 0x584 24 + #define MT6359_RTC_DXI 0x586 25 + #define MT6359_RTC_BBPU 0x588 26 + #define MT6359_RTC_IRQ_STA 0x58a 27 + #define MT6359_RTC_IRQ_EN 0x58c 28 + #define MT6359_RTC_CII_EN 0x58e 29 + #define MT6359_RTC_AL_MASK 0x590 30 + #define MT6359_RTC_TC_SEC 0x592 31 + #define MT6359_RTC_TC_MIN 0x594 32 + #define MT6359_RTC_TC_HOU 0x596 33 + #define MT6359_RTC_TC_DOM 0x598 34 + #define MT6359_RTC_TC_DOW 0x59a 35 + #define MT6359_RTC_TC_MTH 0x59c 36 + #define MT6359_RTC_TC_YEA 0x59e 37 + #define MT6359_RTC_AL_SEC 0x5a0 38 + #define MT6359_RTC_AL_MIN 0x5a2 39 + #define MT6359_RTC_AL_HOU 0x5a4 40 + #define MT6359_RTC_AL_DOM 0x5a6 41 + #define MT6359_RTC_AL_DOW 0x5a8 42 + #define MT6359_RTC_AL_MTH 0x5aa 43 + #define MT6359_RTC_AL_YEA 0x5ac 44 + #define MT6359_RTC_OSC32CON 0x5ae 45 + #define MT6359_RTC_POWERKEY1 0x5b0 46 + #define MT6359_RTC_POWERKEY2 0x5b2 47 + #define MT6359_RTC_PDN1 0x5b4 48 + #define MT6359_RTC_PDN2 0x5b6 49 + #define MT6359_RTC_SPAR0 0x5b8 50 + #define MT6359_RTC_SPAR1 0x5ba 51 + #define MT6359_RTC_PROT 0x5bc 52 + #define MT6359_RTC_DIFF 0x5be 53 + #define MT6359_RTC_CALI 0x5c0 54 + #define MT6359_RTC_WRTGR 0x5c2 55 + #define MT6359_RTC_CON 0x5c4 56 + #define MT6359_RTC_SEC_CTRL 0x5c6 57 + #define MT6359_RTC_INT_CNT 0x5c8 58 + #define MT6359_RTC_SEC_DAT0 0x5ca 59 + #define MT6359_RTC_SEC_DAT1 0x5cc 60 + #define MT6359_RTC_SEC_DAT2 0x5ce 61 + #define MT6359_RTC_SEC_DSN_ID 0x600 62 + #define MT6359_RTC_SEC_DSN_REV0 0x602 63 + #define MT6359_RTC_SEC_DBI 0x604 64 + #define MT6359_RTC_SEC_DXI 0x606 65 + #define MT6359_RTC_TC_SEC_SEC 0x608 66 + #define MT6359_RTC_TC_MIN_SEC 0x60a 67 + #define MT6359_RTC_TC_HOU_SEC 0x60c 68 + #define MT6359_RTC_TC_DOM_SEC 0x60e 69 + #define MT6359_RTC_TC_DOW_SEC 0x610 70 + #define MT6359_RTC_TC_MTH_SEC 0x612 71 + #define MT6359_RTC_TC_YEA_SEC 0x614 72 + #define MT6359_RTC_SEC_CK_PDN 0x616 73 + #define MT6359_RTC_SEC_WRTGR 0x618 74 + #define MT6359_PSC_TOP_INT_CON0 0x910 75 + #define MT6359_PSC_TOP_INT_STATUS0 0x91c 76 + #define MT6359_BM_TOP_INT_CON0 0xc32 77 + #define MT6359_BM_TOP_INT_CON1 0xc38 78 + #define MT6359_BM_TOP_INT_STATUS0 0xc4a 79 + #define MT6359_BM_TOP_INT_STATUS1 0xc4c 80 + #define MT6359_HK_TOP_INT_CON0 0xf92 81 + #define MT6359_HK_TOP_INT_STATUS0 0xf9e 82 + #define MT6359_BUCK_TOP_INT_CON0 0x1418 83 + #define MT6359_BUCK_TOP_INT_STATUS0 0x1424 84 + #define MT6359_BUCK_VPU_CON0 0x1488 85 + #define MT6359_BUCK_VPU_DBG0 0x14a6 86 + #define MT6359_BUCK_VPU_DBG1 0x14a8 87 + #define MT6359_BUCK_VPU_ELR0 0x14ac 88 + #define MT6359_BUCK_VCORE_CON0 0x1508 89 + #define MT6359_BUCK_VCORE_DBG0 0x1526 90 + #define MT6359_BUCK_VCORE_DBG1 0x1528 91 + #define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a 92 + #define MT6359_BUCK_VCORE_ELR0 0x1534 93 + #define MT6359_BUCK_VGPU11_CON0 0x1588 94 + #define MT6359_BUCK_VGPU11_DBG0 0x15a6 95 + #define MT6359_BUCK_VGPU11_DBG1 0x15a8 96 + #define MT6359_BUCK_VGPU11_ELR0 0x15ac 97 + #define MT6359_BUCK_VMODEM_CON0 0x1688 98 + #define MT6359_BUCK_VMODEM_DBG0 0x16a6 99 + #define MT6359_BUCK_VMODEM_DBG1 0x16a8 100 + #define MT6359_BUCK_VMODEM_ELR0 0x16ae 101 + #define MT6359_BUCK_VPROC1_CON0 0x1708 102 + #define MT6359_BUCK_VPROC1_DBG0 0x1726 103 + #define MT6359_BUCK_VPROC1_DBG1 0x1728 104 + #define MT6359_BUCK_VPROC1_ELR0 0x172e 105 + #define MT6359_BUCK_VPROC2_CON0 0x1788 106 + #define MT6359_BUCK_VPROC2_DBG0 0x17a6 107 + #define MT6359_BUCK_VPROC2_DBG1 0x17a8 108 + #define MT6359_BUCK_VPROC2_ELR0 0x17b2 109 + #define MT6359_BUCK_VS1_CON0 0x1808 110 + #define MT6359_BUCK_VS1_DBG0 0x1826 111 + #define MT6359_BUCK_VS1_DBG1 0x1828 112 + #define MT6359_BUCK_VS1_ELR0 0x1834 113 + #define MT6359_BUCK_VS2_CON0 0x1888 114 + #define MT6359_BUCK_VS2_DBG0 0x18a6 115 + #define MT6359_BUCK_VS2_DBG1 0x18a8 116 + #define MT6359_BUCK_VS2_ELR0 0x18b4 117 + #define MT6359_BUCK_VPA_CON0 0x1908 118 + #define MT6359_BUCK_VPA_CON1 0x190e 119 + #define MT6359_BUCK_VPA_CFG0 0x1910 120 + #define MT6359_BUCK_VPA_CFG1 0x1912 121 + #define MT6359_BUCK_VPA_DBG0 0x1914 122 + #define MT6359_BUCK_VPA_DBG1 0x1916 123 + #define MT6359_VGPUVCORE_ANA_CON2 0x198e 124 + #define MT6359_VGPUVCORE_ANA_CON13 0x19a4 125 + #define MT6359_VPROC1_ANA_CON3 0x19b2 126 + #define MT6359_VPROC2_ANA_CON3 0x1a0e 127 + #define MT6359_VMODEM_ANA_CON3 0x1a1a 128 + #define MT6359_VPU_ANA_CON3 0x1a26 129 + #define MT6359_VS1_ANA_CON0 0x1a2c 130 + #define MT6359_VS2_ANA_CON0 0x1a34 131 + #define MT6359_VPA_ANA_CON0 0x1a3c 132 + #define MT6359_LDO_TOP_INT_CON0 0x1b14 133 + #define MT6359_LDO_TOP_INT_CON1 0x1b1a 134 + #define MT6359_LDO_TOP_INT_STATUS0 0x1b28 135 + #define MT6359_LDO_TOP_INT_STATUS1 0x1b2a 136 + #define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40 137 + #define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42 138 + #define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44 139 + #define MT6359_LDO_VSRAM_MD_ELR 0x1b46 140 + #define MT6359_LDO_VFE28_CON0 0x1b88 141 + #define MT6359_LDO_VFE28_MON 0x1b8a 142 + #define MT6359_LDO_VXO22_CON0 0x1b98 143 + #define MT6359_LDO_VXO22_MON 0x1b9a 144 + #define MT6359_LDO_VRF18_CON0 0x1ba8 145 + #define MT6359_LDO_VRF18_MON 0x1baa 146 + #define MT6359_LDO_VRF12_CON0 0x1bb8 147 + #define MT6359_LDO_VRF12_MON 0x1bba 148 + #define MT6359_LDO_VEFUSE_CON0 0x1bc8 149 + #define MT6359_LDO_VEFUSE_MON 0x1bca 150 + #define MT6359_LDO_VCN33_1_CON0 0x1bd8 151 + #define MT6359_LDO_VCN33_1_MON 0x1bda 152 + #define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8 153 + #define MT6359_LDO_VCN33_2_CON0 0x1c08 154 + #define MT6359_LDO_VCN33_2_MON 0x1c0a 155 + #define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18 156 + #define MT6359_LDO_VCN13_CON0 0x1c1a 157 + #define MT6359_LDO_VCN13_MON 0x1c1c 158 + #define MT6359_LDO_VCN18_CON0 0x1c2a 159 + #define MT6359_LDO_VCN18_MON 0x1c2c 160 + #define MT6359_LDO_VA09_CON0 0x1c3a 161 + #define MT6359_LDO_VA09_MON 0x1c3c 162 + #define MT6359_LDO_VCAMIO_CON0 0x1c4a 163 + #define MT6359_LDO_VCAMIO_MON 0x1c4c 164 + #define MT6359_LDO_VA12_CON0 0x1c5a 165 + #define MT6359_LDO_VA12_MON 0x1c5c 166 + #define MT6359_LDO_VAUX18_CON0 0x1c88 167 + #define MT6359_LDO_VAUX18_MON 0x1c8a 168 + #define MT6359_LDO_VAUD18_CON0 0x1c98 169 + #define MT6359_LDO_VAUD18_MON 0x1c9a 170 + #define MT6359_LDO_VIO18_CON0 0x1ca8 171 + #define MT6359_LDO_VIO18_MON 0x1caa 172 + #define MT6359_LDO_VEMC_CON0 0x1cb8 173 + #define MT6359_LDO_VEMC_MON 0x1cba 174 + #define MT6359_LDO_VSIM1_CON0 0x1cc8 175 + #define MT6359_LDO_VSIM1_MON 0x1cca 176 + #define MT6359_LDO_VSIM2_CON0 0x1cd8 177 + #define MT6359_LDO_VSIM2_MON 0x1cda 178 + #define MT6359_LDO_VUSB_CON0 0x1d08 179 + #define MT6359_LDO_VUSB_MON 0x1d0a 180 + #define MT6359_LDO_VUSB_MULTI_SW 0x1d18 181 + #define MT6359_LDO_VRFCK_CON0 0x1d1a 182 + #define MT6359_LDO_VRFCK_MON 0x1d1c 183 + #define MT6359_LDO_VBBCK_CON0 0x1d2a 184 + #define MT6359_LDO_VBBCK_MON 0x1d2c 185 + #define MT6359_LDO_VBIF28_CON0 0x1d3a 186 + #define MT6359_LDO_VBIF28_MON 0x1d3c 187 + #define MT6359_LDO_VIBR_CON0 0x1d4a 188 + #define MT6359_LDO_VIBR_MON 0x1d4c 189 + #define MT6359_LDO_VIO28_CON0 0x1d5a 190 + #define MT6359_LDO_VIO28_MON 0x1d5c 191 + #define MT6359_LDO_VM18_CON0 0x1d88 192 + #define MT6359_LDO_VM18_MON 0x1d8a 193 + #define MT6359_LDO_VUFS_CON0 0x1d98 194 + #define MT6359_LDO_VUFS_MON 0x1d9a 195 + #define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88 196 + #define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a 197 + #define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e 198 + #define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6 199 + #define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8 200 + #define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac 201 + #define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08 202 + #define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a 203 + #define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e 204 + #define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26 205 + #define MT6359_LDO_VSRAM_MD_CON0 0x1f2c 206 + #define MT6359_LDO_VSRAM_MD_MON 0x1f2e 207 + #define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32 208 + #define MT6359_VFE28_ANA_CON0 0x1f88 209 + #define MT6359_VAUX18_ANA_CON0 0x1f8c 210 + #define MT6359_VUSB_ANA_CON0 0x1f90 211 + #define MT6359_VBIF28_ANA_CON0 0x1f94 212 + #define MT6359_VCN33_1_ANA_CON0 0x1f98 213 + #define MT6359_VCN33_2_ANA_CON0 0x1f9c 214 + #define MT6359_VEMC_ANA_CON0 0x1fa0 215 + #define MT6359_VSIM1_ANA_CON0 0x1fa4 216 + #define MT6359_VSIM2_ANA_CON0 0x1fa8 217 + #define MT6359_VIO28_ANA_CON0 0x1fac 218 + #define MT6359_VIBR_ANA_CON0 0x1fb0 219 + #define MT6359_VRF18_ANA_CON0 0x2008 220 + #define MT6359_VEFUSE_ANA_CON0 0x200c 221 + #define MT6359_VCN18_ANA_CON0 0x2010 222 + #define MT6359_VCAMIO_ANA_CON0 0x2014 223 + #define MT6359_VAUD18_ANA_CON0 0x2018 224 + #define MT6359_VIO18_ANA_CON0 0x201c 225 + #define MT6359_VM18_ANA_CON0 0x2020 226 + #define MT6359_VUFS_ANA_CON0 0x2024 227 + #define MT6359_VRF12_ANA_CON0 0x202a 228 + #define MT6359_VCN13_ANA_CON0 0x202e 229 + #define MT6359_VA09_ANA_CON0 0x2032 230 + #define MT6359_VA12_ANA_CON0 0x2036 231 + #define MT6359_VXO22_ANA_CON0 0x2088 232 + #define MT6359_VRFCK_ANA_CON0 0x208c 233 + #define MT6359_VBBCK_ANA_CON0 0x2094 234 + #define MT6359_AUD_TOP_INT_CON0 0x2328 235 + #define MT6359_AUD_TOP_INT_STATUS0 0x2334 236 + 237 + #define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0 238 + #define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0 239 + #define MT6359_RG_BUCK_VPU_LP_SHIFT 1 240 + #define MT6359_DA_VPU_VOSEL_ADDR MT6359_BUCK_VPU_DBG0 241 + #define MT6359_DA_VPU_VOSEL_MASK 0x7F 242 + #define MT6359_DA_VPU_VOSEL_SHIFT 0 243 + #define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1 244 + #define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0 245 + #define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F 246 + #define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0 247 + #define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0 248 + #define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0 249 + #define MT6359_RG_BUCK_VCORE_LP_SHIFT 1 250 + #define MT6359_DA_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_DBG0 251 + #define MT6359_DA_VCORE_VOSEL_MASK 0x7F 252 + #define MT6359_DA_VCORE_VOSEL_SHIFT 0 253 + #define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1 254 + #define MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR MT6359_BUCK_VCORE_SSHUB_CON0 255 + #define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR MT6359_BUCK_VCORE_SSHUB_CON0 256 + #define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F 257 + #define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT 4 258 + #define MT6359_RG_BUCK_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_ELR0 259 + #define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F 260 + #define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0 261 + #define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0 262 + #define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0 263 + #define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1 264 + #define MT6359_DA_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_DBG0 265 + #define MT6359_DA_VGPU11_VOSEL_MASK 0x7F 266 + #define MT6359_DA_VGPU11_VOSEL_SHIFT 0 267 + #define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1 268 + #define MT6359_RG_BUCK_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_ELR0 269 + #define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F 270 + #define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0 271 + #define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0 272 + #define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0 273 + #define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1 274 + #define MT6359_DA_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_DBG0 275 + #define MT6359_DA_VMODEM_VOSEL_MASK 0x7F 276 + #define MT6359_DA_VMODEM_VOSEL_SHIFT 0 277 + #define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1 278 + #define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0 279 + #define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F 280 + #define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0 281 + #define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0 282 + #define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0 283 + #define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1 284 + #define MT6359_DA_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_DBG0 285 + #define MT6359_DA_VPROC1_VOSEL_MASK 0x7F 286 + #define MT6359_DA_VPROC1_VOSEL_SHIFT 0 287 + #define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1 288 + #define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0 289 + #define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F 290 + #define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0 291 + #define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0 292 + #define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0 293 + #define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1 294 + #define MT6359_DA_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_DBG0 295 + #define MT6359_DA_VPROC2_VOSEL_MASK 0x7F 296 + #define MT6359_DA_VPROC2_VOSEL_SHIFT 0 297 + #define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1 298 + #define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0 299 + #define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F 300 + #define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0 301 + #define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0 302 + #define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0 303 + #define MT6359_RG_BUCK_VS1_LP_SHIFT 1 304 + #define MT6359_DA_VS1_VOSEL_ADDR MT6359_BUCK_VS1_DBG0 305 + #define MT6359_DA_VS1_VOSEL_MASK 0x7F 306 + #define MT6359_DA_VS1_VOSEL_SHIFT 0 307 + #define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1 308 + #define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0 309 + #define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F 310 + #define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0 311 + #define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0 312 + #define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0 313 + #define MT6359_RG_BUCK_VS2_LP_SHIFT 1 314 + #define MT6359_DA_VS2_VOSEL_ADDR MT6359_BUCK_VS2_DBG0 315 + #define MT6359_DA_VS2_VOSEL_MASK 0x7F 316 + #define MT6359_DA_VS2_VOSEL_SHIFT 0 317 + #define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1 318 + #define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0 319 + #define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F 320 + #define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0 321 + #define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0 322 + #define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0 323 + #define MT6359_RG_BUCK_VPA_LP_SHIFT 1 324 + #define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1 325 + #define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F 326 + #define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0 327 + #define MT6359_DA_VPA_VOSEL_ADDR MT6359_BUCK_VPA_DBG0 328 + #define MT6359_DA_VPA_VOSEL_MASK 0x3F 329 + #define MT6359_DA_VPA_VOSEL_SHIFT 0 330 + #define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1 331 + #define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2 332 + #define MT6359_RG_VGPU11_FCCM_SHIFT 9 333 + #define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13 334 + #define MT6359_RG_VCORE_FCCM_SHIFT 5 335 + #define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3 336 + #define MT6359_RG_VPROC1_FCCM_SHIFT 1 337 + #define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3 338 + #define MT6359_RG_VPROC2_FCCM_SHIFT 1 339 + #define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3 340 + #define MT6359_RG_VMODEM_FCCM_SHIFT 1 341 + #define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3 342 + #define MT6359_RG_VPU_FCCM_SHIFT 1 343 + #define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0 344 + #define MT6359_RG_VS1_FPWM_SHIFT 3 345 + #define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0 346 + #define MT6359_RG_VS2_FPWM_SHIFT 3 347 + #define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0 348 + #define MT6359_RG_VPA_MODESET_SHIFT 1 349 + #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_ELR 350 + #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F 351 + #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0 352 + #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_ELR 353 + #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F 354 + #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0 355 + #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_ELR 356 + #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F 357 + #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0 358 + #define MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_ELR 359 + #define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F 360 + #define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0 361 + #define MT6359_RG_LDO_VFE28_EN_ADDR MT6359_LDO_VFE28_CON0 362 + #define MT6359_DA_VFE28_B_EN_ADDR MT6359_LDO_VFE28_MON 363 + #define MT6359_RG_LDO_VXO22_EN_ADDR MT6359_LDO_VXO22_CON0 364 + #define MT6359_RG_LDO_VXO22_EN_SHIFT 0 365 + #define MT6359_DA_VXO22_B_EN_ADDR MT6359_LDO_VXO22_MON 366 + #define MT6359_RG_LDO_VRF18_EN_ADDR MT6359_LDO_VRF18_CON0 367 + #define MT6359_RG_LDO_VRF18_EN_SHIFT 0 368 + #define MT6359_DA_VRF18_B_EN_ADDR MT6359_LDO_VRF18_MON 369 + #define MT6359_RG_LDO_VRF12_EN_ADDR MT6359_LDO_VRF12_CON0 370 + #define MT6359_RG_LDO_VRF12_EN_SHIFT 0 371 + #define MT6359_DA_VRF12_B_EN_ADDR MT6359_LDO_VRF12_MON 372 + #define MT6359_RG_LDO_VEFUSE_EN_ADDR MT6359_LDO_VEFUSE_CON0 373 + #define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0 374 + #define MT6359_DA_VEFUSE_B_EN_ADDR MT6359_LDO_VEFUSE_MON 375 + #define MT6359_RG_LDO_VCN33_1_EN_0_ADDR MT6359_LDO_VCN33_1_CON0 376 + #define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1 377 + #define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0 378 + #define MT6359_DA_VCN33_1_B_EN_ADDR MT6359_LDO_VCN33_1_MON 379 + #define MT6359_RG_LDO_VCN33_1_EN_1_ADDR MT6359_LDO_VCN33_1_MULTI_SW 380 + #define MT6359_RG_LDO_VCN33_1_EN_1_SHIFT 15 381 + #define MT6359_RG_LDO_VCN33_2_EN_0_ADDR MT6359_LDO_VCN33_2_CON0 382 + #define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0 383 + #define MT6359_DA_VCN33_2_B_EN_ADDR MT6359_LDO_VCN33_2_MON 384 + #define MT6359_RG_LDO_VCN33_2_EN_1_ADDR MT6359_LDO_VCN33_2_MULTI_SW 385 + #define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1 386 + #define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15 387 + #define MT6359_RG_LDO_VCN13_EN_ADDR MT6359_LDO_VCN13_CON0 388 + #define MT6359_RG_LDO_VCN13_EN_SHIFT 0 389 + #define MT6359_DA_VCN13_B_EN_ADDR MT6359_LDO_VCN13_MON 390 + #define MT6359_RG_LDO_VCN18_EN_ADDR MT6359_LDO_VCN18_CON0 391 + #define MT6359_DA_VCN18_B_EN_ADDR MT6359_LDO_VCN18_MON 392 + #define MT6359_RG_LDO_VA09_EN_ADDR MT6359_LDO_VA09_CON0 393 + #define MT6359_RG_LDO_VA09_EN_SHIFT 0 394 + #define MT6359_DA_VA09_B_EN_ADDR MT6359_LDO_VA09_MON 395 + #define MT6359_RG_LDO_VCAMIO_EN_ADDR MT6359_LDO_VCAMIO_CON0 396 + #define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0 397 + #define MT6359_DA_VCAMIO_B_EN_ADDR MT6359_LDO_VCAMIO_MON 398 + #define MT6359_RG_LDO_VA12_EN_ADDR MT6359_LDO_VA12_CON0 399 + #define MT6359_RG_LDO_VA12_EN_SHIFT 0 400 + #define MT6359_DA_VA12_B_EN_ADDR MT6359_LDO_VA12_MON 401 + #define MT6359_RG_LDO_VAUX18_EN_ADDR MT6359_LDO_VAUX18_CON0 402 + #define MT6359_DA_VAUX18_B_EN_ADDR MT6359_LDO_VAUX18_MON 403 + #define MT6359_RG_LDO_VAUD18_EN_ADDR MT6359_LDO_VAUD18_CON0 404 + #define MT6359_DA_VAUD18_B_EN_ADDR MT6359_LDO_VAUD18_MON 405 + #define MT6359_RG_LDO_VIO18_EN_ADDR MT6359_LDO_VIO18_CON0 406 + #define MT6359_RG_LDO_VIO18_EN_SHIFT 0 407 + #define MT6359_DA_VIO18_B_EN_ADDR MT6359_LDO_VIO18_MON 408 + #define MT6359_RG_LDO_VEMC_EN_ADDR MT6359_LDO_VEMC_CON0 409 + #define MT6359_RG_LDO_VEMC_EN_SHIFT 0 410 + #define MT6359_DA_VEMC_B_EN_ADDR MT6359_LDO_VEMC_MON 411 + #define MT6359_RG_LDO_VSIM1_EN_ADDR MT6359_LDO_VSIM1_CON0 412 + #define MT6359_RG_LDO_VSIM1_EN_SHIFT 0 413 + #define MT6359_DA_VSIM1_B_EN_ADDR MT6359_LDO_VSIM1_MON 414 + #define MT6359_RG_LDO_VSIM2_EN_ADDR MT6359_LDO_VSIM2_CON0 415 + #define MT6359_RG_LDO_VSIM2_EN_SHIFT 0 416 + #define MT6359_DA_VSIM2_B_EN_ADDR MT6359_LDO_VSIM2_MON 417 + #define MT6359_RG_LDO_VUSB_EN_0_ADDR MT6359_LDO_VUSB_CON0 418 + #define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1 419 + #define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0 420 + #define MT6359_DA_VUSB_B_EN_ADDR MT6359_LDO_VUSB_MON 421 + #define MT6359_RG_LDO_VUSB_EN_1_ADDR MT6359_LDO_VUSB_MULTI_SW 422 + #define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1 423 + #define MT6359_RG_LDO_VUSB_EN_1_SHIFT 15 424 + #define MT6359_RG_LDO_VRFCK_EN_ADDR MT6359_LDO_VRFCK_CON0 425 + #define MT6359_RG_LDO_VRFCK_EN_SHIFT 0 426 + #define MT6359_DA_VRFCK_B_EN_ADDR MT6359_LDO_VRFCK_MON 427 + #define MT6359_RG_LDO_VBBCK_EN_ADDR MT6359_LDO_VBBCK_CON0 428 + #define MT6359_RG_LDO_VBBCK_EN_SHIFT 0 429 + #define MT6359_DA_VBBCK_B_EN_ADDR MT6359_LDO_VBBCK_MON 430 + #define MT6359_RG_LDO_VBIF28_EN_ADDR MT6359_LDO_VBIF28_CON0 431 + #define MT6359_DA_VBIF28_B_EN_ADDR MT6359_LDO_VBIF28_MON 432 + #define MT6359_RG_LDO_VIBR_EN_ADDR MT6359_LDO_VIBR_CON0 433 + #define MT6359_RG_LDO_VIBR_EN_SHIFT 0 434 + #define MT6359_DA_VIBR_B_EN_ADDR MT6359_LDO_VIBR_MON 435 + #define MT6359_RG_LDO_VIO28_EN_ADDR MT6359_LDO_VIO28_CON0 436 + #define MT6359_RG_LDO_VIO28_EN_SHIFT 0 437 + #define MT6359_DA_VIO28_B_EN_ADDR MT6359_LDO_VIO28_MON 438 + #define MT6359_RG_LDO_VM18_EN_ADDR MT6359_LDO_VM18_CON0 439 + #define MT6359_RG_LDO_VM18_EN_SHIFT 0 440 + #define MT6359_DA_VM18_B_EN_ADDR MT6359_LDO_VM18_MON 441 + #define MT6359_RG_LDO_VUFS_EN_ADDR MT6359_LDO_VUFS_CON0 442 + #define MT6359_RG_LDO_VUFS_EN_SHIFT 0 443 + #define MT6359_DA_VUFS_B_EN_ADDR MT6359_LDO_VUFS_MON 444 + #define MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359_LDO_VSRAM_PROC1_CON0 445 + #define MT6359_DA_VSRAM_PROC1_B_EN_ADDR MT6359_LDO_VSRAM_PROC1_MON 446 + #define MT6359_DA_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_VOSEL1 447 + #define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F 448 + #define MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT 8 449 + #define MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359_LDO_VSRAM_PROC2_CON0 450 + #define MT6359_DA_VSRAM_PROC2_B_EN_ADDR MT6359_LDO_VSRAM_PROC2_MON 451 + #define MT6359_DA_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_VOSEL1 452 + #define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F 453 + #define MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT 8 454 + #define MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359_LDO_VSRAM_OTHERS_CON0 455 + #define MT6359_DA_VSRAM_OTHERS_B_EN_ADDR MT6359_LDO_VSRAM_OTHERS_MON 456 + #define MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_VOSEL1 457 + #define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F 458 + #define MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT 8 459 + #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB 460 + #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB 461 + #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F 462 + #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1 463 + #define MT6359_RG_LDO_VSRAM_MD_EN_ADDR MT6359_LDO_VSRAM_MD_CON0 464 + #define MT6359_DA_VSRAM_MD_B_EN_ADDR MT6359_LDO_VSRAM_MD_MON 465 + #define MT6359_DA_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_VOSEL1 466 + #define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F 467 + #define MT6359_DA_VSRAM_MD_VOSEL_SHIFT 8 468 + #define MT6359_RG_VCN33_1_VOSEL_ADDR MT6359_VCN33_1_ANA_CON0 469 + #define MT6359_RG_VCN33_1_VOSEL_MASK 0xF 470 + #define MT6359_RG_VCN33_1_VOSEL_SHIFT 8 471 + #define MT6359_RG_VCN33_2_VOSEL_ADDR MT6359_VCN33_2_ANA_CON0 472 + #define MT6359_RG_VCN33_2_VOSEL_MASK 0xF 473 + #define MT6359_RG_VCN33_2_VOSEL_SHIFT 8 474 + #define MT6359_RG_VEMC_VOSEL_ADDR MT6359_VEMC_ANA_CON0 475 + #define MT6359_RG_VEMC_VOSEL_MASK 0xF 476 + #define MT6359_RG_VEMC_VOSEL_SHIFT 8 477 + #define MT6359_RG_VSIM1_VOSEL_ADDR MT6359_VSIM1_ANA_CON0 478 + #define MT6359_RG_VSIM1_VOSEL_MASK 0xF 479 + #define MT6359_RG_VSIM1_VOSEL_SHIFT 8 480 + #define MT6359_RG_VSIM2_VOSEL_ADDR MT6359_VSIM2_ANA_CON0 481 + #define MT6359_RG_VSIM2_VOSEL_MASK 0xF 482 + #define MT6359_RG_VSIM2_VOSEL_SHIFT 8 483 + #define MT6359_RG_VIO28_VOSEL_ADDR MT6359_VIO28_ANA_CON0 484 + #define MT6359_RG_VIO28_VOSEL_MASK 0xF 485 + #define MT6359_RG_VIO28_VOSEL_SHIFT 8 486 + #define MT6359_RG_VIBR_VOSEL_ADDR MT6359_VIBR_ANA_CON0 487 + #define MT6359_RG_VIBR_VOSEL_MASK 0xF 488 + #define MT6359_RG_VIBR_VOSEL_SHIFT 8 489 + #define MT6359_RG_VRF18_VOSEL_ADDR MT6359_VRF18_ANA_CON0 490 + #define MT6359_RG_VRF18_VOSEL_MASK 0xF 491 + #define MT6359_RG_VRF18_VOSEL_SHIFT 8 492 + #define MT6359_RG_VEFUSE_VOSEL_ADDR MT6359_VEFUSE_ANA_CON0 493 + #define MT6359_RG_VEFUSE_VOSEL_MASK 0xF 494 + #define MT6359_RG_VEFUSE_VOSEL_SHIFT 8 495 + #define MT6359_RG_VCAMIO_VOSEL_ADDR MT6359_VCAMIO_ANA_CON0 496 + #define MT6359_RG_VCAMIO_VOSEL_MASK 0xF 497 + #define MT6359_RG_VCAMIO_VOSEL_SHIFT 8 498 + #define MT6359_RG_VIO18_VOSEL_ADDR MT6359_VIO18_ANA_CON0 499 + #define MT6359_RG_VIO18_VOSEL_MASK 0xF 500 + #define MT6359_RG_VIO18_VOSEL_SHIFT 8 501 + #define MT6359_RG_VM18_VOSEL_ADDR MT6359_VM18_ANA_CON0 502 + #define MT6359_RG_VM18_VOSEL_MASK 0xF 503 + #define MT6359_RG_VM18_VOSEL_SHIFT 8 504 + #define MT6359_RG_VUFS_VOSEL_ADDR MT6359_VUFS_ANA_CON0 505 + #define MT6359_RG_VUFS_VOSEL_MASK 0xF 506 + #define MT6359_RG_VUFS_VOSEL_SHIFT 8 507 + #define MT6359_RG_VRF12_VOSEL_ADDR MT6359_VRF12_ANA_CON0 508 + #define MT6359_RG_VRF12_VOSEL_MASK 0xF 509 + #define MT6359_RG_VRF12_VOSEL_SHIFT 8 510 + #define MT6359_RG_VCN13_VOSEL_ADDR MT6359_VCN13_ANA_CON0 511 + #define MT6359_RG_VCN13_VOSEL_MASK 0xF 512 + #define MT6359_RG_VCN13_VOSEL_SHIFT 8 513 + #define MT6359_RG_VA09_VOSEL_ADDR MT6359_VA09_ANA_CON0 514 + #define MT6359_RG_VA09_VOSEL_MASK 0xF 515 + #define MT6359_RG_VA09_VOSEL_SHIFT 8 516 + #define MT6359_RG_VA12_VOSEL_ADDR MT6359_VA12_ANA_CON0 517 + #define MT6359_RG_VA12_VOSEL_MASK 0xF 518 + #define MT6359_RG_VA12_VOSEL_SHIFT 8 519 + #define MT6359_RG_VXO22_VOSEL_ADDR MT6359_VXO22_ANA_CON0 520 + #define MT6359_RG_VXO22_VOSEL_MASK 0xF 521 + #define MT6359_RG_VXO22_VOSEL_SHIFT 8 522 + #define MT6359_RG_VRFCK_VOSEL_ADDR MT6359_VRFCK_ANA_CON0 523 + #define MT6359_RG_VRFCK_VOSEL_MASK 0xF 524 + #define MT6359_RG_VRFCK_VOSEL_SHIFT 8 525 + #define MT6359_RG_VBBCK_VOSEL_ADDR MT6359_VBBCK_ANA_CON0 526 + #define MT6359_RG_VBBCK_VOSEL_MASK 0xF 527 + #define MT6359_RG_VBBCK_VOSEL_SHIFT 8 528 + 529 + #endif /* __MFD_MT6359_REGISTERS_H__ */

+1

include/linux/mfd/mt6397/core.h

··· 13 13 enum chip_id { 14 14 MT6323_CHIP_ID = 0x23, 15 15 MT6358_CHIP_ID = 0x58, 16 + MT6359_CHIP_ID = 0x59, 16 17 MT6391_CHIP_ID = 0x91, 17 18 MT6397_CHIP_ID = 0x97, 18 19 };