tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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[SUNSAB]: Defer register updates until transmitter is idle.

The chip can emit garbage characters if we touch the
settings while characters are going out.

Signed-off-by: David S. Miller <davem@davemloft.net>

David S. Miller e4fdee8e 88d7bd8c

+72 -38
+71 -38
drivers/serial/sunsab.c
··· 61 61 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */ 62 62 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */ 63 63 int type; /* SAB82532 version */ 64 + 65 + /* Setting configuration bits while the transmitter is active 66 + * can cause garbage characters to get emitted by the chip. 67 + * Therefore, we cache such writes here and do the real register 68 + * write the next time the transmitter becomes idle. 69 + */ 70 + unsigned int cached_ebrg; 71 + unsigned char cached_mode; 72 + unsigned char cached_pvr; 73 + unsigned char cached_dafo; 64 74 }; 65 75 66 76 /* ··· 246 236 } 247 237 248 238 static void sunsab_stop_tx(struct uart_port *, unsigned int); 239 + static void sunsab_tx_idle(struct uart_sunsab_port *); 249 240 250 241 static void transmit_chars(struct uart_sunsab_port *up, 251 242 union sab82532_irq_status *stat) ··· 269 258 return; 270 259 271 260 set_bit(SAB82532_XPR, &up->irqflags); 261 + sunsab_tx_idle(up); 272 262 273 263 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 274 264 up->interrupt_mask1 |= SAB82532_IMR1_XPR; ··· 409 397 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 410 398 411 399 if (mctrl & TIOCM_RTS) { 412 - writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_FRTS, 413 - &up->regs->rw.mode); 414 - writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS, 415 - &up->regs->rw.mode); 400 + up->cached_mode &= ~SAB82532_MODE_FRTS; 401 + up->cached_mode |= SAB82532_MODE_RTS; 416 402 } else { 417 - writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS, 418 - &up->regs->rw.mode); 419 - writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS, 420 - &up->regs->rw.mode); 403 + up->cached_mode |= (SAB82532_MODE_FRTS | 404 + SAB82532_MODE_RTS); 421 405 } 422 406 if (mctrl & TIOCM_DTR) { 423 - writeb(readb(&up->regs->rw.pvr) & ~(up->pvr_dtr_bit), &up->regs->rw.pvr); 407 + up->cached_pvr &= ~(up->pvr_dtr_bit); 424 408 } else { 425 - writeb(readb(&up->regs->rw.pvr) | up->pvr_dtr_bit, &up->regs->rw.pvr); 409 + up->cached_pvr |= up->pvr_dtr_bit; 426 410 } 411 + 412 + set_bit(SAB82532_REGS_PENDING, &up->irqflags); 413 + if (test_bit(SAB82532_XPR, &up->irqflags)) 414 + sunsab_tx_idle(up); 427 415 } 428 416 429 417 /* port->lock is not held. */ ··· 459 447 460 448 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 461 449 writeb(up->interrupt_mask1, &up->regs->w.imr1); 450 + } 451 + 452 + /* port->lock held by caller. */ 453 + static void sunsab_tx_idle(struct uart_sunsab_port *up) 454 + { 455 + if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) { 456 + u8 tmp; 457 + 458 + clear_bit(SAB82532_REGS_PENDING, &up->irqflags); 459 + writeb(up->cached_mode, &up->regs->rw.mode); 460 + writeb(up->cached_pvr, &up->regs->rw.pvr); 461 + writeb(up->cached_dafo, &up->regs->w.dafo); 462 + 463 + writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr); 464 + tmp = readb(&up->regs->rw.ccr2); 465 + tmp &= ~0xc0; 466 + tmp |= (up->cached_ebrg >> 2) & 0xc0; 467 + writeb(tmp, &up->regs->rw.ccr2); 468 + } 462 469 } 463 470 464 471 /* port->lock held by caller. */ ··· 548 517 549 518 spin_lock_irqsave(&up->port.lock, flags); 550 519 551 - val = readb(&up->regs->rw.dafo); 520 + val = up->cached_dafo; 552 521 if (break_state) 553 522 val |= SAB82532_DAFO_XBRK; 554 523 else 555 524 val &= ~SAB82532_DAFO_XBRK; 556 - writeb(val, &up->regs->rw.dafo); 525 + up->cached_dafo = val; 526 + 527 + set_bit(SAB82532_REGS_PENDING, &up->irqflags); 528 + if (test_bit(SAB82532_XPR, &up->irqflags)) 529 + sunsab_tx_idle(up); 557 530 558 531 spin_unlock_irqrestore(&up->port.lock, flags); 559 532 } ··· 601 566 SAB82532_CCR2_TOE, &up->regs->w.ccr2); 602 567 writeb(0, &up->regs->w.ccr3); 603 568 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4); 604 - writeb(SAB82532_MODE_RTS | SAB82532_MODE_FCTS | 605 - SAB82532_MODE_RAC, &up->regs->w.mode); 569 + up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS | 570 + SAB82532_MODE_RAC); 571 + writeb(up->cached_mode, &up->regs->w.mode); 606 572 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc); 607 573 608 574 tmp = readb(&up->regs->rw.ccr0); ··· 634 598 { 635 599 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 636 600 unsigned long flags; 637 - unsigned char tmp; 638 601 639 602 spin_lock_irqsave(&up->port.lock, flags); 640 603 ··· 644 609 writeb(up->interrupt_mask1, &up->regs->w.imr1); 645 610 646 611 /* Disable break condition */ 647 - tmp = readb(&up->regs->rw.dafo); 648 - tmp &= ~SAB82532_DAFO_XBRK; 649 - writeb(tmp, &up->regs->rw.dafo); 612 + up->cached_dafo = readb(&up->regs->rw.dafo); 613 + up->cached_dafo &= ~SAB82532_DAFO_XBRK; 614 + writeb(up->cached_dafo, &up->regs->rw.dafo); 650 615 651 616 /* Disable Receiver */ 652 - tmp = readb(&up->regs->rw.mode); 653 - tmp &= ~SAB82532_MODE_RAC; 654 - writeb(tmp, &up->regs->rw.mode); 617 + up->cached_mode &= ~SAB82532_MODE_RAC; 618 + writeb(up->cached_mode, &up->regs->rw.mode); 655 619 656 620 /* 657 621 * XXX FIXME ··· 719 685 unsigned int iflag, unsigned int baud, 720 686 unsigned int quot) 721 687 { 722 - unsigned int ebrg; 723 688 unsigned char dafo; 724 689 int bits, n, m; 725 690 ··· 747 714 } else { 748 715 dafo |= SAB82532_DAFO_PAR_EVEN; 749 716 } 717 + up->cached_dafo = dafo; 750 718 751 719 calc_ebrg(baud, &n, &m); 752 720 753 - ebrg = n | (m << 6); 721 + up->cached_ebrg = n | (m << 6); 754 722 755 723 up->tec_timeout = (10 * 1000000) / baud; 756 724 up->cec_timeout = up->tec_timeout >> 2; ··· 804 770 uart_update_timeout(&up->port, cflag, 805 771 (up->port.uartclk / (16 * quot))); 806 772 807 - /* Now bang the new settings into the chip. */ 808 - sunsab_cec_wait(up); 809 - sunsab_tec_wait(up); 810 - writeb(dafo, &up->regs->w.dafo); 811 - writeb(ebrg & 0xff, &up->regs->w.bgr); 812 - writeb((readb(&up->regs->rw.ccr2) & ~0xc0) | ((ebrg >> 2) & 0xc0), 813 - &up->regs->rw.ccr2); 814 - 815 - writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RAC, &up->regs->rw.mode); 816 - 773 + /* Now schedule a register update when the chip's 774 + * transmitter is idle. 775 + */ 776 + up->cached_mode |= SAB82532_MODE_RAC; 777 + set_bit(SAB82532_REGS_PENDING, &up->irqflags); 778 + if (test_bit(SAB82532_XPR, &up->irqflags)) 779 + sunsab_tx_idle(up); 817 780 } 818 781 819 782 /* port->lock is not held. */ ··· 1115 1084 up->pvr_dsr_bit = (1 << 3); 1116 1085 up->pvr_dtr_bit = (1 << 2); 1117 1086 } 1118 - writeb((1 << 1) | (1 << 2) | (1 << 4), &up->regs->w.pvr); 1119 - writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS, 1120 - &up->regs->rw.mode); 1121 - writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS, 1122 - &up->regs->rw.mode); 1087 + up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4); 1088 + writeb(up->cached_pvr, &up->regs->w.pvr); 1089 + up->cached_mode = readb(&up->regs->rw.mode); 1090 + up->cached_mode |= SAB82532_MODE_FRTS; 1091 + writeb(up->cached_mode, &up->regs->rw.mode); 1092 + up->cached_mode |= SAB82532_MODE_RTS; 1093 + writeb(up->cached_mode, &up->regs->rw.mode); 1123 1094 1124 1095 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT; 1125 1096 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
+1
drivers/serial/sunsab.h
··· 126 126 /* irqflags bits */ 127 127 #define SAB82532_ALLS 0x00000001 128 128 #define SAB82532_XPR 0x00000002 129 + #define SAB82532_REGS_PENDING 0x00000004 129 130 130 131 /* RFIFO Status Byte */ 131 132 #define SAB82532_RSTAT_PE 0x80