MIPS: Convert the irq functions to the new names

tjh.dev / kernel

fork atom

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

fork atom

MIPS: Convert the irq functions to the new names

Scripted with coccinelle.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

Thomas Gleixner 15 years ago e4ec7989 9efbc3fb

+185 -167

59 changed files

expand all collapse all

arch

mips

alchemy

devboards

bcsr.c

db1200

setup.c

db1x00

board_setup.c

pb1000

board_setup.c

pb1100

board_setup.c

pb1200

board_setup.c

pb1500

board_setup.c

pb1550

board_setup.c

mtx-1

board_setup.c

xxs1500

board_setup.c

ar7

irq.c

ath79

irq.c

bcm63xx

irq.c

dec

ioasic-irq.c

kn02-irq.c

emma

markeins

irq.c

jazz

irq.c

jz4740

gpio.c

irq.c

kernel

i8259.c

irq-gic.c

irq-gt641xx.c

irq-msc01.c

irq-rm7000.c

irq-rm9000.c

irq.c

irq_cpu.c

irq_txx9.c

smtc.c

lasat

interrupt.c

loongson

common

bonito-irq.c

mti-malta

malta-int.c

malta-time.c

pci

msi-octeon.c

pmc-sierra

msp71xx

msp_irq_cic.c

msp_irq_slp.c

msp_smp.c

pnx833x

common

interrupts.c

pnx8550

common

int.c

powertv

asic

irq_asic.c

rb532

irq.c

sgi-ip22

ip22-int.c

sgi-ip27

ip27-irq.c

ip27-timer.c

sgi-ip32

ip32-irq.c

sibyte

bcm1480

irq.c

sb1250

irq.c

sni

a20r.c

pcimt.c

pcit.c

rm200.c

txx9

generic

irq_tx4927.c

irq_tx4938.c

irq_tx4939.c

jmr3927

irq.c

rbtx4927

irq.c

rbtx4938

irq.c

rbtx4939

irq.c

vr41xx

common

icu.c

+3 -3

arch/mips/alchemy/devboards/bcsr.c

reviewed

··· 142 142 bcsr_csc_base = csc_start; 143 143 144 144 for (irq = csc_start; irq <= csc_end; irq++) 145 145 - set_irq_chip_and_handler_name(irq, &bcsr_irq_type, 146 146 - handle_level_irq, "level"); 145 145 + irq_set_chip_and_handler_name(irq, &bcsr_irq_type, 146 146 + handle_level_irq, "level"); 147 147 148 148 - set_irq_chained_handler(hook_irq, bcsr_csc_handler); 148 148 + irq_set_chained_handler(hook_irq, bcsr_csc_handler); 149 149 }

+1 -1

arch/mips/alchemy/devboards/db1200/setup.c

reviewed

··· 63 63 static int __init db1200_arch_init(void) 64 64 { 65 65 /* GPIO7 is low-level triggered CPLD cascade */ 66 66 - set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); 66 66 + irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); 67 67 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 68 68 69 69 /* insert/eject pairs: one of both is always screaming. To avoid

+25 -25

arch/mips/alchemy/devboards/db1x00/board_setup.c

reviewed

··· 215 215 static int __init db1x00_init_irq(void) 216 216 { 217 217 #if defined(CONFIG_MIPS_MIRAGE) 218 218 - set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ 218 218 + irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ 219 219 #elif defined(CONFIG_MIPS_DB1550) 220 220 - set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 221 221 - set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ 222 222 - set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 223 223 - set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 224 224 - set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 225 225 - set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 220 220 + irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 221 221 + irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ 222 222 + irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 223 223 + irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 224 224 + irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 225 225 + irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 226 226 #elif defined(CONFIG_MIPS_DB1500) 227 227 - set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 228 228 - set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 229 229 - set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 230 230 - set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 231 231 - set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 232 232 - set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 227 227 + irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 228 228 + irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 229 229 + irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 230 230 + irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 231 231 + irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 232 232 + irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 233 233 #elif defined(CONFIG_MIPS_DB1100) 234 234 - set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 235 235 - set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 236 236 - set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 237 237 - set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 238 238 - set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 239 239 - set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 234 234 + irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 235 235 + irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 236 236 + irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 237 237 + irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 238 238 + irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 239 239 + irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 240 240 #elif defined(CONFIG_MIPS_DB1000) 241 241 - set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 242 242 - set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 243 243 - set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 244 244 - set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 245 245 - set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 246 246 - set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 241 241 + irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 242 242 + irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 243 243 + irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 244 244 + irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 245 245 + irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 246 246 + irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 247 247 #endif 248 248 return 0; 249 249 }

+1 -1

arch/mips/alchemy/devboards/pb1000/board_setup.c

reviewed

··· 197 197 198 198 static int __init pb1000_init_irq(void) 199 199 { 200 200 - set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW); 200 200 + irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW); 201 201 return 0; 202 202 } 203 203 arch_initcall(pb1000_init_irq);

+4 -4

arch/mips/alchemy/devboards/pb1100/board_setup.c

reviewed

··· 117 117 118 118 static int __init pb1100_init_irq(void) 119 119 { 120 120 - set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ 121 121 - set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ 122 122 - set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ 123 123 - set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ 120 120 + irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ 121 121 + irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ 122 122 + irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ 123 123 + irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ 124 124 125 125 return 0; 126 126 }

+1 -1

arch/mips/alchemy/devboards/pb1200/board_setup.c

reviewed

··· 142 142 panic("Game over. Your score is 0."); 143 143 } 144 144 145 145 - set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); 145 145 + irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); 146 146 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); 147 147 148 148 return 0;

+8 -8

arch/mips/alchemy/devboards/pb1500/board_setup.c

reviewed

··· 134 134 135 135 static int __init pb1500_init_irq(void) 136 136 { 137 137 - set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ 138 138 - set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ 139 139 - set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 140 140 - set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 141 141 - set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 142 142 - set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 143 143 - set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 144 144 - set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 137 137 + irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ 138 138 + irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ 139 139 + irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 140 140 + irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 141 141 + irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 142 142 + irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 143 143 + irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 144 144 + irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 145 145 146 146 return 0; 147 147 }

+3 -3

arch/mips/alchemy/devboards/pb1550/board_setup.c

reviewed

··· 73 73 74 74 static int __init pb1550_init_irq(void) 75 75 { 76 76 - set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); 77 77 - set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); 78 78 - set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); 76 76 + irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); 77 77 + irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); 78 78 + irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); 79 79 80 80 /* enable both PCMCIA card irqs in the shared line */ 81 81 alchemy_gpio2_enable_int(201);

+5 -5

arch/mips/alchemy/mtx-1/board_setup.c

reviewed

··· 123 123 124 124 static int __init mtx1_init_irq(void) 125 125 { 126 126 - set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 127 127 - set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 128 128 - set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 129 129 - set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 130 130 - set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 126 126 + irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 127 127 + irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 128 128 + irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 129 129 + irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 130 130 + irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 131 131 132 132 return 0; 133 133 }

+12 -12

arch/mips/alchemy/xxs1500/board_setup.c

reviewed

··· 85 85 86 86 static int __init xxs1500_init_irq(void) 87 87 { 88 88 - set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 89 89 - set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 90 90 - set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 91 91 - set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 92 92 - set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 93 93 - set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW); 88 88 + irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 89 89 + irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 90 90 + irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 91 91 + irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 92 92 + irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 93 93 + irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW); 94 94 95 95 - set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); 96 96 - set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); 97 97 - set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); 98 98 - set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); 99 99 - set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */ 100 100 - set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); 95 95 + irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); 96 96 + irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); 97 97 + irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); 98 98 + irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); 99 99 + irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */ 100 100 + irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); 101 101 102 102 return 0; 103 103 }

+2 -2

arch/mips/ar7/irq.c

reviewed

··· 119 119 for (i = 0; i < 40; i++) { 120 120 writel(i, REG(CHNL_OFFSET(i))); 121 121 /* Primary IRQ's */ 122 122 - set_irq_chip_and_handler(base + i, &ar7_irq_type, 122 122 + irq_set_chip_and_handler(base + i, &ar7_irq_type, 123 123 handle_level_irq); 124 124 /* Secondary IRQ's */ 125 125 if (i < 32) 126 126 - set_irq_chip_and_handler(base + i + 40, 126 126 + irq_set_chip_and_handler(base + i + 40, 127 127 &ar7_sec_irq_type, 128 128 handle_level_irq); 129 129 }

+2 -2

arch/mips/ath79/irq.c

reviewed

··· 124 124 125 125 for (i = ATH79_MISC_IRQ_BASE; 126 126 i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { 127 127 - set_irq_chip_and_handler(i, &ath79_misc_irq_chip, 127 127 + irq_set_chip_and_handler(i, &ath79_misc_irq_chip, 128 128 handle_level_irq); 129 129 } 130 130 131 131 - set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); 131 131 + irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); 132 132 } 133 133 134 134 asmlinkage void plat_irq_dispatch(void)

+2 -2

arch/mips/bcm63xx/irq.c

reviewed

··· 230 230 231 231 mips_cpu_irq_init(); 232 232 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) 233 233 - set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip, 233 233 + irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, 234 234 handle_level_irq); 235 235 236 236 for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) 237 237 - set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip, 237 237 + irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, 238 238 handle_edge_irq); 239 239 240 240 setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);

+2 -2

arch/mips/dec/ioasic-irq.c

reviewed

··· 68 68 fast_iob(); 69 69 70 70 for (i = base; i < base + IO_INR_DMA; i++) 71 71 - set_irq_chip_and_handler(i, &ioasic_irq_type, 71 71 + irq_set_chip_and_handler(i, &ioasic_irq_type, 72 72 handle_level_irq); 73 73 for (; i < base + IO_IRQ_LINES; i++) 74 74 - set_irq_chip(i, &ioasic_dma_irq_type); 74 74 + irq_set_chip(i, &ioasic_dma_irq_type); 75 75 76 76 ioasic_irq_base = base; 77 77 }

+1 -1

arch/mips/dec/kn02-irq.c

reviewed

··· 73 73 iob(); 74 74 75 75 for (i = base; i < base + KN02_IRQ_LINES; i++) 76 76 - set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq); 76 76 + irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq); 77 77 78 78 kn02_irq_base = base; 79 79 }

+3 -3

arch/mips/emma/markeins/irq.c

reviewed

··· 69 69 u32 i; 70 70 71 71 for (i = 0; i < NUM_EMMA2RH_IRQ; i++) 72 72 - set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, 72 72 + irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, 73 73 &emma2rh_irq_controller, 74 74 handle_level_irq, "level"); 75 75 } ··· 105 105 u32 i; 106 106 107 107 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) 108 108 - set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, 108 108 + irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, 109 109 &emma2rh_sw_irq_controller, 110 110 handle_level_irq, "level"); 111 111 } ··· 162 162 u32 i; 163 163 164 164 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) 165 165 - set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, 165 165 + irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, 166 166 &emma2rh_gpio_irq_controller, 167 167 handle_edge_irq, "edge"); 168 168 }

+1 -1

arch/mips/jazz/irq.c

reviewed

··· 56 56 int i; 57 57 58 58 for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++) 59 59 - set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); 59 59 + irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq); 60 60 61 61 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); 62 62 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */

+7 -7

arch/mips/jz4740/gpio.c

reviewed

··· 306 306 uint32_t flag; 307 307 unsigned int gpio_irq; 308 308 unsigned int gpio_bank; 309 309 - struct jz_gpio_chip *chip = get_irq_desc_data(desc); 309 309 + struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc); 310 310 311 311 gpio_bank = JZ4740_IRQ_GPIO0 - irq; 312 312 ··· 416 416 chip->wakeup &= ~IRQ_TO_BIT(data->irq); 417 417 spin_unlock(&chip->lock); 418 418 419 419 - set_irq_wake(chip->irq, on); 419 419 + irq_set_irq_wake(chip->irq, on); 420 420 return 0; 421 421 } 422 422 ··· 510 510 gpiochip_add(&chip->gpio_chip); 511 511 512 512 chip->irq = JZ4740_IRQ_INTC_GPIO(id); 513 513 - set_irq_data(chip->irq, chip); 514 514 - set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler); 513 513 + irq_set_handler_data(chip->irq, chip); 514 514 + irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler); 515 515 516 516 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { 517 517 irq_set_lockdep_class(irq, &gpio_lock_class); 518 518 - set_irq_chip_data(irq, chip); 519 519 - set_irq_chip_and_handler(irq, &jz_gpio_irq_chip, 520 520 - handle_level_irq); 518 518 + irq_set_chip_data(irq, chip); 519 519 + irq_set_chip_and_handler(irq, &jz_gpio_irq_chip, 520 520 + handle_level_irq); 521 521 } 522 522 523 523 return 0;

+2 -2

arch/mips/jz4740/irq.c

reviewed

··· 104 104 writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); 105 105 106 106 for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { 107 107 - set_irq_chip_data(i, (void *)IRQ_BIT(i)); 108 108 - set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); 107 107 + irq_set_chip_data(i, (void *)IRQ_BIT(i)); 108 108 + irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq); 109 109 } 110 110 111 111 setup_irq(2, &jz4740_cascade_action);

+3 -3

arch/mips/kernel/i8259.c

reviewed

··· 110 110 void make_8259A_irq(unsigned int irq) 111 111 { 112 112 disable_irq_nosync(irq); 113 113 - set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); 113 113 + irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq); 114 114 enable_irq(irq); 115 115 } 116 116 ··· 336 336 init_8259A(0); 337 337 338 338 for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) { 339 339 - set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq); 340 340 - set_irq_probe(i); 339 339 + irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq); 340 340 + irq_set_probe(i); 341 341 } 342 342 343 343 setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);

+1 -1

arch/mips/kernel/irq-gic.c

reviewed

··· 229 229 vpe_local_setup(numvpes); 230 230 231 231 for (i = _irqbase; i < (_irqbase + numintrs); i++) 232 232 - set_irq_chip(i, &gic_irq_controller); 232 232 + irq_set_chip(i, &gic_irq_controller); 233 233 } 234 234 235 235 void __init gic_init(unsigned long gic_base_addr,

+2 -2

arch/mips/kernel/irq-gt641xx.c

reviewed

··· 126 126 * bit31: logical or of bits[25:1]. 127 127 */ 128 128 for (i = 1; i < 30; i++) 129 129 - set_irq_chip_and_handler(GT641XX_IRQ_BASE + i, 130 130 - &gt641xx_irq_chip, handle_level_irq); 129 129 + irq_set_chip_and_handler(GT641XX_IRQ_BASE + i, 130 130 + &gt641xx_irq_chip, handle_level_irq); 131 131 }

+8 -4

arch/mips/kernel/irq-msc01.c

reviewed

··· 137 137 138 138 switch (imp->im_type) { 139 139 case MSC01_IRQ_EDGE: 140 140 - set_irq_chip_and_handler_name(irqbase + n, 141 141 - &msc_edgeirq_type, handle_edge_irq, "edge"); 140 140 + irq_set_chip_and_handler_name(irqbase + n, 141 141 + &msc_edgeirq_type, 142 142 + handle_edge_irq, 143 143 + "edge"); 142 144 if (cpu_has_veic) 143 145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 144 146 else 145 147 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 146 148 break; 147 149 case MSC01_IRQ_LEVEL: 148 148 - set_irq_chip_and_handler_name(irqbase+n, 149 149 - &msc_levelirq_type, handle_level_irq, "level"); 150 150 + irq_set_chip_and_handler_name(irqbase + n, 151 151 + &msc_levelirq_type, 152 152 + handle_level_irq, 153 153 + "level"); 150 154 if (cpu_has_veic) 151 155 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 152 156 else

+1 -1

arch/mips/kernel/irq-rm7000.c

reviewed

··· 45 45 clear_c0_intcontrol(0x00000f00); /* Mask all */ 46 46 47 47 for (i = base; i < base + 4; i++) 48 48 - set_irq_chip_and_handler(i, &rm7k_irq_controller, 48 48 + irq_set_chip_and_handler(i, &rm7k_irq_controller, 49 49 handle_percpu_irq); 50 50 }

+2 -2

arch/mips/kernel/irq-rm9000.c

reviewed

··· 98 98 clear_c0_intcontrol(0x0000f000); /* Mask all */ 99 99 100 100 for (i = base; i < base + 4; i++) 101 101 - set_irq_chip_and_handler(i, &rm9k_irq_controller, 101 101 + irq_set_chip_and_handler(i, &rm9k_irq_controller, 102 102 handle_level_irq); 103 103 104 104 rm9000_perfcount_irq = base + 1; 105 105 - set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, 105 105 + irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, 106 106 handle_percpu_irq); 107 107 }

+1 -1

arch/mips/kernel/irq.c

reviewed

··· 102 102 #endif 103 103 104 104 for (i = 0; i < NR_IRQS; i++) 105 105 - set_irq_noprobe(i); 105 105 + irq_set_noprobe(i); 106 106 107 107 arch_init_irq(); 108 108

+2 -2

arch/mips/kernel/irq_cpu.c

reviewed

··· 109 109 */ 110 110 if (cpu_has_mipsmt) 111 111 for (i = irq_base; i < irq_base + 2; i++) 112 112 - set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller, 112 112 + irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller, 113 113 handle_percpu_irq); 114 114 115 115 for (i = irq_base + 2; i < irq_base + 8; i++) 116 116 - set_irq_chip_and_handler(i, &mips_cpu_irq_controller, 116 116 + irq_set_chip_and_handler(i, &mips_cpu_irq_controller, 117 117 handle_percpu_irq); 118 118 }

+2 -2

arch/mips/kernel/irq_txx9.c

reviewed

··· 154 154 for (i = 0; i < TXx9_MAX_IR; i++) { 155 155 txx9irq[i].level = 4; /* middle level */ 156 156 txx9irq[i].mode = TXx9_IRCR_LOW; 157 157 - set_irq_chip_and_handler(TXX9_IRQ_BASE + i, 158 158 - &txx9_irq_chip, handle_level_irq); 157 157 + irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip, 158 158 + handle_level_irq); 159 159 } 160 160 161 161 /* mask all IRC interrupts */

+1 -1

arch/mips/kernel/smtc.c

reviewed

··· 1146 1146 1147 1147 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); 1148 1148 1149 1149 - set_irq_handler(cpu_ipi_irq, handle_percpu_irq); 1149 1149 + irq_set_handler(cpu_ipi_irq, handle_percpu_irq); 1150 1150 } 1151 1151 1152 1152 /*

+1 -1

arch/mips/lasat/interrupt.c

reviewed

··· 128 128 mips_cpu_irq_init(); 129 129 130 130 for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++) 131 131 - set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq); 131 131 + irq_set_chip_and_handler(i, &lasat_irq_type, handle_level_irq); 132 132 133 133 setup_irq(LASAT_CASCADE_IRQ, &cascade); 134 134 }

+2 -1

arch/mips/loongson/common/bonito-irq.c

reviewed

··· 44 44 u32 i; 45 45 46 46 for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) 47 47 - set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); 47 47 + irq_set_chip_and_handler(i, &bonito_irq_type, 48 48 + handle_level_irq); 48 49 49 50 #ifdef CONFIG_CPU_LOONGSON2E 50 51 setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);

+1 -1

arch/mips/mti-malta/malta-int.c

reviewed

··· 472 472 void __init arch_init_ipiirq(int irq, struct irqaction *action) 473 473 { 474 474 setup_irq(irq, action); 475 475 - set_irq_handler(irq, handle_percpu_irq); 475 475 + irq_set_handler(irq, handle_percpu_irq); 476 476 } 477 477 478 478 void __init arch_init_irq(void)

+1 -1

arch/mips/mti-malta/malta-time.c

reviewed

··· 119 119 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); 120 120 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 121 121 #ifdef CONFIG_SMP 122 122 - set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); 122 122 + irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq); 123 123 #endif 124 124 } 125 125 }

+2 -2

arch/mips/pci/msi-octeon.c

reviewed

··· 172 172 pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, 173 173 control); 174 174 175 175 - set_irq_msi(irq, desc); 175 175 + irq_set_msi_desc(irq, desc); 176 176 write_msi_msg(irq, &msg); 177 177 return 0; 178 178 } ··· 388 388 } 389 389 390 390 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) 391 391 - set_irq_chip_and_handler(irq, msi, handle_simple_irq); 391 391 + irq_set_chip_and_handler(irq, msi, handle_simple_irq); 392 392 393 393 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { 394 394 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,

+1 -1

arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c

reviewed

··· 182 182 183 183 /* initialize all the IRQ descriptors */ 184 184 for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) { 185 185 - set_irq_chip_and_handler(i, &msp_cic_irq_controller, 185 185 + irq_set_chip_and_handler(i, &msp_cic_irq_controller, 186 186 handle_level_irq); 187 187 #ifdef CONFIG_MIPS_MT_SMTC 188 188 /* Mask of CIC interrupt */

+1 -1

arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c

reviewed

··· 77 77 78 78 /* initialize all the IRQ descriptors */ 79 79 for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++) 80 80 - set_irq_chip_and_handler(i, &msp_slp_irq_controller, 80 80 + irq_set_chip_and_handler(i, &msp_slp_irq_controller, 81 81 handle_level_irq); 82 82 } 83 83

+1 -1

arch/mips/pmc-sierra/msp71xx/msp_smp.c

reviewed

··· 64 64 void __init arch_init_ipiirq(int irq, struct irqaction *action) 65 65 { 66 66 setup_irq(irq, action); 67 67 - set_irq_handler(irq, handle_percpu_irq); 67 67 + irq_set_handler(irq, handle_percpu_irq); 68 68 } 69 69 70 70 void __init msp_vsmp_int_init(void)

+4 -2

arch/mips/pnx833x/common/interrupts.c

reviewed

··· 259 259 /* Set IRQ information in irq_desc */ 260 260 for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) { 261 261 pnx833x_hard_disable_pic_irq(irq); 262 262 - set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq); 262 262 + irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type, 263 263 + handle_simple_irq); 263 264 } 264 265 265 266 for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++) 266 266 - set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq); 267 267 + irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type, 268 268 + handle_simple_irq); 267 269 268 270 /* Set PIC priority limiter register to 0 */ 269 271 PNX833X_PIC_INT_PRIORITY = 0;

+5 -5

arch/mips/pnx8550/common/int.c

reviewed

··· 183 183 int configPR; 184 184 185 185 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) 186 186 - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 186 186 + irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); 187 187 188 188 /* init of GIC/IPC interrupts */ 189 189 /* should be done before cp0 since cp0 init enables the GIC int */ ··· 206 206 /* mask/priority is still 0 so we will not get any 207 207 * interrupts until it is unmasked */ 208 208 209 209 - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 209 209 + irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); 210 210 } 211 211 212 212 /* Priority level 0 */ ··· 215 215 /* Set int vector table address */ 216 216 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; 217 217 218 218 - set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, 218 218 + irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, 219 219 handle_level_irq); 220 220 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); 221 221 222 222 /* init of Timer interrupts */ 223 223 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) 224 224 - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 224 224 + irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); 225 225 226 226 /* Stop Timer 1-3 */ 227 227 configPR = read_c0_config7(); 228 228 configPR |= 0x00000038; 229 229 write_c0_config7(configPR); 230 230 231 231 - set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, 231 231 + irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, 232 232 handle_level_irq); 233 233 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); 234 234 }

+1 -1

arch/mips/powertv/asic/irq_asic.c

reviewed

··· 112 112 * Initialize interrupt handlers. 113 113 */ 114 114 for (i = 0; i < NR_IRQS; i++) 115 115 - set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq); 115 115 + irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq); 116 116 }

+2 -2

arch/mips/rb532/irq.c

reviewed

··· 207 207 pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS); 208 208 209 209 for (i = 0; i < RC32434_NR_IRQS; i++) 210 210 - set_irq_chip_and_handler(i, &rc32434_irq_type, 211 211 - handle_level_irq); 210 210 + irq_set_chip_and_handler(i, &rc32434_irq_type, 211 211 + handle_level_irq); 212 212 } 213 213 214 214 /* Main Interrupt dispatcher */

+1 -1

arch/mips/sgi-ip22/ip22-int.c

reviewed

··· 312 312 else 313 313 handler = &ip22_local3_irq_type; 314 314 315 315 - set_irq_chip_and_handler(i, handler, handle_level_irq); 315 315 + irq_set_chip_and_handler(i, handler, handle_level_irq); 316 316 } 317 317 318 318 /* vector handler. this register the IRQ as non-sharable */

+1 -1

arch/mips/sgi-ip27/ip27-irq.c

reviewed

··· 337 337 338 338 void __devinit register_bridge_irq(unsigned int irq) 339 339 { 340 340 - set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); 340 340 + irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); 341 341 } 342 342 343 343 int __devinit request_bridge_irq(struct bridge_controller *bc)

+1 -1

arch/mips/sgi-ip27/ip27-timer.c

reviewed

··· 153 153 panic("Allocation of irq number for timer failed"); 154 154 } while (xchg(&rt_timer_irq, irq)); 155 155 156 156 - set_irq_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq); 156 156 + irq_set_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq); 157 157 setup_irq(irq, &hub_rt_irqaction); 158 158 } 159 159

+24 -16

arch/mips/sgi-ip32/ip32-irq.c

reviewed

··· 451 451 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { 452 452 switch (irq) { 453 453 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: 454 454 - set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt, 455 455 - handle_level_irq, "level"); 454 454 + irq_set_chip_and_handler_name(irq, 455 455 + &ip32_mace_interrupt, 456 456 + handle_level_irq, 457 457 + "level"); 456 458 break; 457 459 458 460 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: 459 459 - set_irq_chip_and_handler_name(irq, 460 460 - &ip32_macepci_interrupt, handle_level_irq, 461 461 - "level"); 461 461 + irq_set_chip_and_handler_name(irq, 462 462 + &ip32_macepci_interrupt, 463 463 + handle_level_irq, 464 464 + "level"); 462 465 break; 463 466 464 467 case CRIME_CPUERR_IRQ: 465 468 case CRIME_MEMERR_IRQ: 466 466 - set_irq_chip_and_handler_name(irq, 467 467 - &crime_level_interrupt, handle_level_irq, 468 468 - "level"); 469 469 + irq_set_chip_and_handler_name(irq, 470 470 + &crime_level_interrupt, 471 471 + handle_level_irq, 472 472 + "level"); 469 473 break; 470 474 471 475 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: 472 476 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: 473 477 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: 474 478 case CRIME_VICE_IRQ: 475 475 - set_irq_chip_and_handler_name(irq, 476 476 - &crime_edge_interrupt, handle_edge_irq, "edge"); 479 479 + irq_set_chip_and_handler_name(irq, 480 480 + &crime_edge_interrupt, 481 481 + handle_edge_irq, 482 482 + "edge"); 477 483 break; 478 484 479 485 case MACEISA_PARALLEL_IRQ: 480 486 case MACEISA_SERIAL1_TDMAPR_IRQ: 481 487 case MACEISA_SERIAL2_TDMAPR_IRQ: 482 482 - set_irq_chip_and_handler_name(irq, 483 483 - &ip32_maceisa_edge_interrupt, handle_edge_irq, 484 484 - "edge"); 488 488 + irq_set_chip_and_handler_name(irq, 489 489 + &ip32_maceisa_edge_interrupt, 490 490 + handle_edge_irq, 491 491 + "edge"); 485 492 break; 486 493 487 494 default: 488 488 - set_irq_chip_and_handler_name(irq, 489 489 - &ip32_maceisa_level_interrupt, handle_level_irq, 490 490 - "level"); 495 495 + irq_set_chip_and_handler_name(irq, 496 496 + &ip32_maceisa_level_interrupt, 497 497 + handle_level_irq, 498 498 + "level"); 491 499 break; 492 500 } 493 501 }

+2 -1

arch/mips/sibyte/bcm1480/irq.c

reviewed

··· 216 216 int i; 217 217 218 218 for (i = 0; i < BCM1480_NR_IRQS; i++) { 219 219 - set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq); 219 219 + irq_set_chip_and_handler(i, &bcm1480_irq_type, 220 220 + handle_level_irq); 220 221 bcm1480_irq_owner[i] = 0; 221 222 } 222 223 }

+2 -1

arch/mips/sibyte/sb1250/irq.c

reviewed

··· 190 190 int i; 191 191 192 192 for (i = 0; i < SB1250_NR_IRQS; i++) { 193 193 - set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq); 193 193 + irq_set_chip_and_handler(i, &sb1250_irq_type, 194 194 + handle_level_irq); 194 195 sb1250_irq_owner[i] = 0; 195 196 } 196 197 }

+1 -1

arch/mips/sni/a20r.c

reviewed

··· 209 209 int i; 210 210 211 211 for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++) 212 212 - set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq); 212 212 + irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq); 213 213 sni_hwint = a20r_hwint; 214 214 change_c0_status(ST0_IM, IE_IRQ0); 215 215 setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);

+1 -1

arch/mips/sni/pcimt.c

reviewed

··· 296 296 mips_cpu_irq_init(); 297 297 /* Actually we've got more interrupts to handle ... */ 298 298 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++) 299 299 - set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq); 299 299 + irq_set_chip_and_handler(i, &pcimt_irq_type, handle_level_irq); 300 300 sni_hwint = sni_pcimt_hwint; 301 301 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); 302 302 }

+2 -2

arch/mips/sni/pcit.c

reviewed

··· 238 238 239 239 mips_cpu_irq_init(); 240 240 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) 241 241 - set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); 241 241 + irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); 242 242 *(volatile u32 *)SNI_PCIT_INT_REG = 0; 243 243 sni_hwint = sni_pcit_hwint; 244 244 change_c0_status(ST0_IM, IE_IRQ1); ··· 251 251 252 252 mips_cpu_irq_init(); 253 253 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) 254 254 - set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); 254 254 + irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); 255 255 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; 256 256 sni_hwint = sni_pcit_hwint_cplus; 257 257 change_c0_status(ST0_IM, IE_IRQ0);

+2 -2

arch/mips/sni/rm200.c

reviewed

··· 413 413 sni_rm200_init_8259A(); 414 414 415 415 for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++) 416 416 - set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip, 416 416 + irq_set_chip_and_handler(i, &sni_rm200_i8259A_chip, 417 417 handle_level_irq); 418 418 419 419 setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2); ··· 477 477 mips_cpu_irq_init(); 478 478 /* Actually we've got more interrupts to handle ... */ 479 479 for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) 480 480 - set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq); 480 480 + irq_set_chip_and_handler(i, &rm200_irq_type, handle_level_irq); 481 481 sni_hwint = sni_rm200_hwint; 482 482 change_c0_status(ST0_IM, IE_IRQ0); 483 483 setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);

+1 -1

arch/mips/txx9/generic/irq_tx4927.c

reviewed

··· 35 35 36 36 mips_cpu_irq_init(); 37 37 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); 38 38 - set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, 38 38 + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, 39 39 handle_simple_irq); 40 40 /* raise priority for errors, timers, SIO */ 41 41 txx9_irq_set_pri(TX4927_IR_ECCERR, 7);

+1 -1

arch/mips/txx9/generic/irq_tx4938.c

reviewed

··· 23 23 24 24 mips_cpu_irq_init(); 25 25 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); 26 26 - set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, 26 26 + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, 27 27 handle_simple_irq); 28 28 /* raise priority for errors, timers, SIO */ 29 29 txx9_irq_set_pri(TX4938_IR_ECCERR, 7);

+3 -3

arch/mips/txx9/generic/irq_tx4939.c

reviewed

··· 176 176 for (i = 1; i < TX4939_NUM_IR; i++) { 177 177 tx4939irq[i].level = 4; /* middle level */ 178 178 tx4939irq[i].mode = TXx9_IRCR_LOW; 179 179 - set_irq_chip_and_handler(TXX9_IRQ_BASE + i, 180 180 - &tx4939_irq_chip, handle_level_irq); 179 179 + irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip, 180 180 + handle_level_irq); 181 181 } 182 182 183 183 /* mask all IRC interrupts */ ··· 193 193 __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r); 194 194 __raw_writel(irc_elevel, &tx4939_ircptr->msk.r); 195 195 196 196 - set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, 196 196 + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, 197 197 handle_simple_irq); 198 198 199 199 /* raise priority for errors, timers, sio */

+3 -2

arch/mips/txx9/jmr3927/irq.c

reviewed

··· 120 120 121 121 tx3927_irq_init(); 122 122 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) 123 123 - set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); 123 123 + irq_set_chip_and_handler(i, &jmr3927_irq_ioc, 124 124 + handle_level_irq); 124 125 125 126 /* setup IOC interrupt 1 (PCI, MODEM) */ 126 126 - set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); 127 127 + irq_set_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); 127 128 }

+3 -3

arch/mips/txx9/rbtx4927/irq.c

reviewed

··· 164 164 165 165 for (i = RBTX4927_IRQ_IOC; 166 166 i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) 167 167 - set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, 167 167 + irq_set_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, 168 168 handle_level_irq); 169 169 - set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq); 169 169 + irq_set_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq); 170 170 } 171 171 172 172 static int rbtx4927_irq_dispatch(int pending) ··· 194 194 tx4927_irq_init(); 195 195 toshiba_rbtx4927_irq_ioc_init(); 196 196 /* Onboard 10M Ether: High Active */ 197 197 - set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); 197 197 + irq_set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); 198 198 }

+3 -3

arch/mips/txx9/rbtx4938/irq.c

reviewed

··· 132 132 133 133 for (i = RBTX4938_IRQ_IOC; 134 134 i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++) 135 135 - set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, 135 135 + irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, 136 136 handle_level_irq); 137 137 138 138 - set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq); 138 138 + irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq); 139 139 } 140 140 141 141 void __init rbtx4938_irq_setup(void) ··· 153 153 tx4938_irq_init(); 154 154 toshiba_rbtx4938_irq_ioc_init(); 155 155 /* Onboard 10M Ether: High Active */ 156 156 - set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); 156 156 + irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); 157 157 }

+2 -2

arch/mips/txx9/rbtx4939/irq.c

reviewed

··· 88 88 tx4939_irq_init(); 89 89 for (i = RBTX4939_IRQ_IOC; 90 90 i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++) 91 91 - set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip, 91 91 + irq_set_chip_and_handler(i, &rbtx4939_ioc_irq_chip, 92 92 handle_level_irq); 93 93 94 94 - set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq); 94 94 + irq_set_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq); 95 95 }

+2 -2

arch/mips/vr41xx/common/icu.c

reviewed

··· 710 710 icu2_write(MGIUINTHREG, 0xffff); 711 711 712 712 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) 713 713 - set_irq_chip_and_handler(i, &sysint1_irq_type, 713 713 + irq_set_chip_and_handler(i, &sysint1_irq_type, 714 714 handle_level_irq); 715 715 716 716 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) 717 717 - set_irq_chip_and_handler(i, &sysint2_irq_type, 717 717 + irq_set_chip_and_handler(i, &sysint2_irq_type, 718 718 handle_level_irq); 719 719 720 720 cascade_irq(INT0_IRQ, icu_get_irq);