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dt-bindings: PCI: tegra194: Convert to json-schema

Convert the Tegra194 PCIe bindings from the free-form text format to
json-schema.

Link: https://lore.kernel.org/r/20220721142052.25971-2-vidyas@nvidia.com
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>

authored by

Vidya Sagar and committed by
Bjorn Helgaas
e4dffb67 e8fbd344

+478 -247
+225
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based) 8 + 9 + maintainers: 10 + - Thierry Reding <thierry.reding@gmail.com> 11 + - Jon Hunter <jonathanh@nvidia.com> 12 + - Vidya Sagar <vidyas@nvidia.com> 13 + 14 + description: | 15 + This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16 + inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some 17 + of the controller instances are dual mode; they can work either in Root 18 + Port mode or Endpoint mode but one at a time. 19 + 20 + On Tegra194, controllers C0, C4 and C5 support Endpoint mode. 21 + 22 + Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to 23 + operate in the Endpoint mode because of the way the platform is designed. 24 + 25 + properties: 26 + compatible: 27 + enum: 28 + - nvidia,tegra194-pcie-ep 29 + 30 + reg: 31 + items: 32 + - description: controller's application logic registers 33 + - description: iATU and DMA registers. This is where the iATU (internal 34 + Address Translation Unit) registers of the PCIe core are made 35 + available for software access. 36 + - description: aperture where the Root Port's own configuration 37 + registers are available. 38 + - description: aperture used to map the remote Root Complex address space 39 + 40 + reg-names: 41 + items: 42 + - const: appl 43 + - const: atu_dma 44 + - const: dbi 45 + - const: addr_space 46 + 47 + interrupts: 48 + items: 49 + - description: controller interrupt 50 + 51 + interrupt-names: 52 + items: 53 + - const: intr 54 + 55 + clocks: 56 + items: 57 + - description: module clock 58 + 59 + clock-names: 60 + items: 61 + - const: core 62 + 63 + resets: 64 + items: 65 + - description: APB bus interface reset 66 + - description: module reset 67 + 68 + reset-names: 69 + items: 70 + - const: apb 71 + - const: core 72 + 73 + reset-gpios: 74 + description: Must contain a phandle to a GPIO controller followed by GPIO 75 + that is being used as PERST input signal. Please refer to pci.txt. 76 + 77 + phys: 78 + minItems: 1 79 + maxItems: 8 80 + 81 + phy-names: 82 + minItems: 1 83 + items: 84 + - const: p2u-0 85 + - const: p2u-1 86 + - const: p2u-2 87 + - const: p2u-3 88 + - const: p2u-4 89 + - const: p2u-5 90 + - const: p2u-6 91 + - const: p2u-7 92 + 93 + power-domains: 94 + maxItems: 1 95 + description: | 96 + A phandle to the node that controls power to the respective PCIe 97 + controller and a specifier name for the PCIe controller. 98 + 99 + Specifiers defined in "include/dt-bindings/power/tegra194-powergate.h". 100 + 101 + interconnects: 102 + items: 103 + - description: memory read client 104 + - description: memory write client 105 + 106 + interconnect-names: 107 + items: 108 + - const: dma-mem # read 109 + - const: write 110 + 111 + dma-coherent: true 112 + 113 + nvidia,bpmp: 114 + $ref: /schemas/types.yaml#/definitions/phandle-array 115 + description: | 116 + Must contain a pair of phandles to BPMP controller node followed by 117 + controller ID. Following are the controller IDs for each controller: 118 + 119 + 0: C0 120 + 1: C1 121 + 2: C2 122 + 3: C3 123 + 4: C4 124 + 5: C5 125 + items: 126 + - items: 127 + - description: phandle to BPMP controller node 128 + - description: PCIe controller ID 129 + maximum: 5 130 + 131 + nvidia,aspm-cmrt-us: 132 + description: Common Mode Restore Time for proper operation of ASPM to be 133 + specified in microseconds 134 + 135 + nvidia,aspm-pwr-on-t-us: 136 + description: Power On time for proper operation of ASPM to be specified in 137 + microseconds 138 + 139 + nvidia,aspm-l0s-entrance-latency-us: 140 + description: ASPM L0s entrance latency to be specified in microseconds 141 + 142 + vddio-pex-ctl-supply: 143 + description: A phandle to the regulator supply for PCIe side band signals 144 + 145 + nvidia,refclk-select-gpios: 146 + maxItems: 1 147 + description: GPIO used to enable REFCLK to controller from the host 148 + 149 + allOf: 150 + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# 151 + 152 + unevaluatedProperties: false 153 + 154 + required: 155 + - interrupts 156 + - interrupt-names 157 + - clocks 158 + - clock-names 159 + - resets 160 + - reset-names 161 + - power-domains 162 + - reset-gpios 163 + - vddio-pex-ctl-supply 164 + - num-lanes 165 + - phys 166 + - phy-names 167 + - nvidia,bpmp 168 + 169 + examples: 170 + - | 171 + #include <dt-bindings/clock/tegra194-clock.h> 172 + #include <dt-bindings/gpio/tegra194-gpio.h> 173 + #include <dt-bindings/interrupt-controller/arm-gic.h> 174 + #include <dt-bindings/power/tegra194-powergate.h> 175 + #include <dt-bindings/reset/tegra194-reset.h> 176 + 177 + bus@0 { 178 + #address-cells = <2>; 179 + #size-cells = <2>; 180 + ranges = <0x0 0x0 0x0 0x8 0x0>; 181 + 182 + pcie-ep@141a0000 { 183 + compatible = "nvidia,tegra194-pcie-ep"; 184 + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 185 + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 186 + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 187 + <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 188 + reg-names = "appl", "atu_dma", "dbi", "addr_space"; 189 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 190 + interrupt-names = "intr"; 191 + 192 + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 193 + clock-names = "core"; 194 + 195 + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 196 + <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 197 + reset-names = "apb", "core"; 198 + 199 + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 200 + pinctrl-names = "default"; 201 + pinctrl-0 = <&clkreq_c5_bi_dir_state>; 202 + 203 + nvidia,bpmp = <&bpmp 5>; 204 + 205 + nvidia,aspm-cmrt-us = <60>; 206 + nvidia,aspm-pwr-on-t-us = <20>; 207 + nvidia,aspm-l0s-entrance-latency-us = <3>; 208 + 209 + vddio-pex-ctl-supply = <&vdd_1v8ao>; 210 + 211 + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; 212 + 213 + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) 214 + GPIO_ACTIVE_HIGH>; 215 + 216 + num-lanes = <8>; 217 + 218 + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 219 + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 220 + <&p2u_nvhs_6>, <&p2u_nvhs_7>; 221 + 222 + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 223 + "p2u-5", "p2u-6", "p2u-7"; 224 + }; 225 + };
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Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
··· 1 - NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) 2 - 3 - This PCIe controller is based on the Synopsis Designware PCIe IP 4 - and thus inherits all the common properties defined in snps,dw-pcie.yaml and 5 - snps,dw-pcie-ep.yaml. 6 - Some of the controller instances are dual mode where in they can work either 7 - in root port mode or endpoint mode but one at a time. 8 - 9 - Required properties: 10 - - power-domains: A phandle to the node that controls power to the respective 11 - PCIe controller and a specifier name for the PCIe controller. Following are 12 - the specifiers for the different PCIe controllers 13 - TEGRA194_POWER_DOMAIN_PCIEX8B: C0 14 - TEGRA194_POWER_DOMAIN_PCIEX1A: C1 15 - TEGRA194_POWER_DOMAIN_PCIEX1A: C2 16 - TEGRA194_POWER_DOMAIN_PCIEX1A: C3 17 - TEGRA194_POWER_DOMAIN_PCIEX4A: C4 18 - TEGRA194_POWER_DOMAIN_PCIEX8A: C5 19 - these specifiers are defined in 20 - "include/dt-bindings/power/tegra194-powergate.h" file. 21 - - reg: A list of physical base address and length pairs for each set of 22 - controller registers. Must contain an entry for each entry in the reg-names 23 - property. 24 - - reg-names: Must include the following entries: 25 - "appl": Controller's application logic registers 26 - "config": As per the definition in snps,dw-pcie.yaml 27 - "atu_dma": iATU and DMA registers. This is where the iATU (internal Address 28 - Translation Unit) registers of the PCIe core are made available 29 - for SW access. 30 - "dbi": The aperture where root port's own configuration registers are 31 - available 32 - - interrupts: A list of interrupt outputs of the controller. Must contain an 33 - entry for each entry in the interrupt-names property. 34 - - interrupt-names: Must include the following entries: 35 - "intr": The Tegra interrupt that is asserted for controller interrupts 36 - - clocks: Must contain an entry for each entry in clock-names. 37 - See ../clocks/clock-bindings.txt for details. 38 - - clock-names: Must include the following entries: 39 - - core 40 - - resets: Must contain an entry for each entry in reset-names. 41 - See ../reset/reset.txt for details. 42 - - reset-names: Must include the following entries: 43 - - apb 44 - - core 45 - - phys: Must contain a phandle to P2U PHY for each entry in phy-names. 46 - - phy-names: Must include an entry for each active lane. 47 - "p2u-N": where N ranges from 0 to one less than the total number of lanes 48 - - nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed 49 - by controller-id. Following are the controller ids for each controller. 50 - 0: C0 51 - 1: C1 52 - 2: C2 53 - 3: C3 54 - 4: C4 55 - 5: C5 56 - - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals 57 - 58 - RC mode: 59 - - compatible: Tegra19x must contain "nvidia,tegra194-pcie" 60 - - device_type: Must be "pci" for RC mode 61 - - interrupt-names: Must include the following entries: 62 - "msi": The Tegra interrupt that is asserted when an MSI is received 63 - - bus-range: Range of bus numbers associated with this controller 64 - - #address-cells: Address representation for root ports (must be 3) 65 - - cell 0 specifies the bus and device numbers of the root port: 66 - [23:16]: bus number 67 - [15:11]: device number 68 - - cell 1 denotes the upper 32 address bits and should be 0 69 - - cell 2 contains the lower 32 address bits and is used to translate to the 70 - CPU address space 71 - - #size-cells: Size representation for root ports (must be 2) 72 - - ranges: Describes the translation of addresses for root ports and standard 73 - PCI regions. The entries must be 7 cells each, where the first three cells 74 - correspond to the address as described for the #address-cells property 75 - above, the fourth and fifth cells are for the physical CPU address to 76 - translate to and the sixth and seventh cells are as described for the 77 - #size-cells property above. 78 - - Entries setup the mapping for the standard I/O, memory and 79 - prefetchable PCI regions. The first cell determines the type of region 80 - that is setup: 81 - - 0x81000000: I/O memory region 82 - - 0x82000000: non-prefetchable memory region 83 - - 0xc2000000: prefetchable memory region 84 - Please refer to the standard PCI bus binding document for a more detailed 85 - explanation. 86 - - #interrupt-cells: Size representation for interrupts (must be 1) 87 - - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 88 - Please refer to the standard PCI bus binding document for a more detailed 89 - explanation. 90 - 91 - EP mode: 92 - In Tegra194, Only controllers C0, C4 & C5 support EP mode. 93 - - compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep" 94 - - reg-names: Must include the following entries: 95 - "addr_space": Used to map remote RC address space 96 - - reset-gpios: Must contain a phandle to a GPIO controller followed by 97 - GPIO that is being used as PERST input signal. Please refer to pci.txt 98 - document. 99 - 100 - Optional properties: 101 - - pinctrl-names: A list of pinctrl state names. 102 - It is mandatory for C5 controller and optional for other controllers. 103 - - "default": Configures PCIe I/O for proper operation. 104 - - pinctrl-0: phandle for the 'default' state of pin configuration. 105 - It is mandatory for C5 controller and optional for other controllers. 106 - - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt 107 - - nvidia,update-fc-fixup: This is a boolean property and needs to be present to 108 - improve performance when a platform is designed in such a way that it 109 - satisfies at least one of the following conditions thereby enabling root 110 - port to exchange optimum number of FC (Flow Control) credits with 111 - downstream devices 112 - 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) 113 - 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and 114 - a) speed is Gen-2 and MPS is 256B 115 - b) speed is >= Gen-3 with any MPS 116 - - nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM 117 - to be specified in microseconds 118 - - nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be 119 - specified in microseconds 120 - - nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be 121 - specified in microseconds 122 - 123 - RC mode: 124 - - vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot 125 - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller 126 - in p2972-0000 platform). 127 - - vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot 128 - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller 129 - in p2972-0000 platform). 130 - 131 - EP mode: 132 - - nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller 133 - followed by GPIO that is being used to enable REFCLK to controller from host 134 - 135 - NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to 136 - operate in the endpoint mode because of the way the platform is designed. 137 - 138 - Examples: 139 - ========= 140 - 141 - Tegra194 RC mode: 142 - ----------------- 143 - 144 - pcie@14180000 { 145 - compatible = "nvidia,tegra194-pcie"; 146 - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 147 - reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 148 - 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 149 - 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */ 150 - reg-names = "appl", "config", "atu_dma"; 151 - 152 - #address-cells = <3>; 153 - #size-cells = <2>; 154 - device_type = "pci"; 155 - num-lanes = <8>; 156 - linux,pci-domain = <0>; 157 - 158 - pinctrl-names = "default"; 159 - pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 160 - 161 - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 162 - clock-names = "core"; 163 - 164 - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 165 - <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 166 - reset-names = "apb", "core"; 167 - 168 - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 169 - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 170 - interrupt-names = "intr", "msi"; 171 - 172 - #interrupt-cells = <1>; 173 - interrupt-map-mask = <0 0 0 0>; 174 - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 175 - 176 - nvidia,bpmp = <&bpmp 0>; 177 - 178 - supports-clkreq; 179 - nvidia,aspm-cmrt-us = <60>; 180 - nvidia,aspm-pwr-on-t-us = <20>; 181 - nvidia,aspm-l0s-entrance-latency-us = <3>; 182 - 183 - bus-range = <0x0 0xff>; 184 - ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 185 - 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */ 186 - 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */ 187 - 188 - vddio-pex-ctl-supply = <&vdd_1v8ao>; 189 - vpcie3v3-supply = <&vdd_3v3_pcie>; 190 - vpcie12v-supply = <&vdd_12v_pcie>; 191 - 192 - phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, 193 - <&p2u_hsio_5>; 194 - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 195 - }; 196 - 197 - Tegra194 EP mode: 198 - ----------------- 199 - 200 - pcie-ep@141a0000 { 201 - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 202 - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 203 - reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 204 - 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 205 - 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ 206 - 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 207 - reg-names = "appl", "atu_dma", "dbi", "addr_space"; 208 - 209 - num-lanes = <8>; 210 - num-ib-windows = <2>; 211 - num-ob-windows = <8>; 212 - 213 - pinctrl-names = "default"; 214 - pinctrl-0 = <&clkreq_c5_bi_dir_state>; 215 - 216 - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 217 - clock-names = "core"; 218 - 219 - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 220 - <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 221 - reset-names = "apb", "core"; 222 - 223 - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 224 - interrupt-names = "intr"; 225 - 226 - nvidia,bpmp = <&bpmp 5>; 227 - 228 - nvidia,aspm-cmrt-us = <60>; 229 - nvidia,aspm-pwr-on-t-us = <20>; 230 - nvidia,aspm-l0s-entrance-latency-us = <3>; 231 - 232 - vddio-pex-ctl-supply = <&vdd_1v8ao>; 233 - 234 - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; 235 - 236 - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) 237 - GPIO_ACTIVE_HIGH>; 238 - 239 - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 240 - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 241 - <&p2u_nvhs_6>, <&p2u_nvhs_7>; 242 - 243 - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 244 - "p2u-5", "p2u-6", "p2u-7"; 245 - };
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Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based) 8 + 9 + maintainers: 10 + - Thierry Reding <thierry.reding@gmail.com> 11 + - Jon Hunter <jonathanh@nvidia.com> 12 + - Vidya Sagar <vidyas@nvidia.com> 13 + 14 + description: | 15 + This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16 + inherits all the common properties defined in snps,dw-pcie.yaml. Some of 17 + the controller instances are dual mode where in they can work either in 18 + Root Port mode or Endpoint mode but one at a time. 19 + 20 + See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device 21 + tree bindings. 22 + 23 + properties: 24 + compatible: 25 + enum: 26 + - nvidia,tegra194-pcie 27 + 28 + reg: 29 + items: 30 + - description: controller's application logic registers 31 + - description: configuration registers 32 + - description: iATU and DMA registers. This is where the iATU (internal 33 + Address Translation Unit) registers of the PCIe core are made 34 + available for software access. 35 + - description: aperture where the Root Port's own configuration 36 + registers are available. 37 + 38 + reg-names: 39 + items: 40 + - const: appl 41 + - const: config 42 + - const: atu_dma 43 + - const: dbi 44 + 45 + interrupts: 46 + items: 47 + - description: controller interrupt 48 + - description: MSI interrupt 49 + 50 + interrupt-names: 51 + items: 52 + - const: intr 53 + - const: msi 54 + 55 + clocks: 56 + items: 57 + - description: module clock 58 + 59 + clock-names: 60 + items: 61 + - const: core 62 + 63 + resets: 64 + items: 65 + - description: APB bus interface reset 66 + - description: module reset 67 + 68 + reset-names: 69 + items: 70 + - const: apb 71 + - const: core 72 + 73 + phys: 74 + minItems: 1 75 + maxItems: 8 76 + 77 + phy-names: 78 + minItems: 1 79 + items: 80 + - const: p2u-0 81 + - const: p2u-1 82 + - const: p2u-2 83 + - const: p2u-3 84 + - const: p2u-4 85 + - const: p2u-5 86 + - const: p2u-6 87 + - const: p2u-7 88 + 89 + power-domains: 90 + maxItems: 1 91 + description: | 92 + A phandle to the node that controls power to the respective PCIe 93 + controller and a specifier name for the PCIe controller. 94 + 95 + specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file. 96 + 97 + interconnects: 98 + items: 99 + - description: memory read client 100 + - description: memory write client 101 + 102 + interconnect-names: 103 + items: 104 + - const: dma-mem # read 105 + - const: write 106 + 107 + dma-coherent: true 108 + 109 + nvidia,bpmp: 110 + $ref: /schemas/types.yaml#/definitions/phandle-array 111 + description: | 112 + Must contain a pair of phandles to BPMP controller node followed by 113 + controller ID. Following are the controller IDs for each controller: 114 + 115 + 0: C0 116 + 1: C1 117 + 2: C2 118 + 3: C3 119 + 4: C4 120 + 5: C5 121 + items: 122 + - items: 123 + - description: phandle to BPMP controller node 124 + - description: PCIe controller ID 125 + maximum: 5 126 + 127 + nvidia,update-fc-fixup: 128 + description: | 129 + This is a boolean property and needs to be present to improve performance 130 + when a platform is designed in such a way that it satisfies at least one 131 + of the following conditions thereby enabling Root Port to exchange 132 + optimum number of FC (Flow Control) credits with downstream devices: 133 + 134 + 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) 135 + 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and 136 + a) speed is Gen-2 and MPS is 256B 137 + b) speed is >= Gen-3 with any MPS 138 + 139 + $ref: /schemas/types.yaml#/definitions/flag 140 + 141 + nvidia,aspm-cmrt-us: 142 + description: Common Mode Restore Time for proper operation of ASPM to be 143 + specified in microseconds 144 + 145 + nvidia,aspm-pwr-on-t-us: 146 + description: Power On time for proper operation of ASPM to be specified in 147 + microseconds 148 + 149 + nvidia,aspm-l0s-entrance-latency-us: 150 + description: ASPM L0s entrance latency to be specified in microseconds 151 + 152 + vddio-pex-ctl-supply: 153 + description: A phandle to the regulator supply for PCIe side band signals. 154 + 155 + vpcie3v3-supply: 156 + description: A phandle to the regulator node that supplies 3.3V to the slot 157 + if the platform has one such slot, e.g., x16 slot owned by C5 controller 158 + in p2972-0000 platform. 159 + 160 + vpcie12v-supply: 161 + description: A phandle to the regulator node that supplies 12V to the slot 162 + if the platform has one such slot, e.g., x16 slot owned by C5 controller 163 + in p2972-0000 platform. 164 + 165 + allOf: 166 + - $ref: /schemas/pci/snps,dw-pcie.yaml# 167 + 168 + unevaluatedProperties: false 169 + 170 + required: 171 + - interrupts 172 + - interrupt-names 173 + - interrupt-map 174 + - interrupt-map-mask 175 + - clocks 176 + - clock-names 177 + - resets 178 + - reset-names 179 + - power-domains 180 + - vddio-pex-ctl-supply 181 + - num-lanes 182 + - phys 183 + - phy-names 184 + - nvidia,bpmp 185 + 186 + examples: 187 + - | 188 + #include <dt-bindings/clock/tegra194-clock.h> 189 + #include <dt-bindings/interrupt-controller/arm-gic.h> 190 + #include <dt-bindings/power/tegra194-powergate.h> 191 + #include <dt-bindings/reset/tegra194-reset.h> 192 + 193 + bus@0 { 194 + #address-cells = <2>; 195 + #size-cells = <2>; 196 + ranges = <0x0 0x0 0x0 0x8 0x0>; 197 + 198 + pcie@14180000 { 199 + compatible = "nvidia,tegra194-pcie"; 200 + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 201 + reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 202 + <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 203 + <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 204 + <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 205 + reg-names = "appl", "config", "atu_dma", "dbi"; 206 + 207 + #address-cells = <3>; 208 + #size-cells = <2>; 209 + device_type = "pci"; 210 + num-lanes = <8>; 211 + linux,pci-domain = <0>; 212 + 213 + pinctrl-names = "default"; 214 + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 215 + 216 + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 217 + clock-names = "core"; 218 + 219 + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 220 + <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 221 + reset-names = "apb", "core"; 222 + 223 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 224 + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 225 + interrupt-names = "intr", "msi"; 226 + 227 + #interrupt-cells = <1>; 228 + interrupt-map-mask = <0 0 0 0>; 229 + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 230 + 231 + nvidia,bpmp = <&bpmp 0>; 232 + 233 + supports-clkreq; 234 + nvidia,aspm-cmrt-us = <60>; 235 + nvidia,aspm-pwr-on-t-us = <20>; 236 + nvidia,aspm-l0s-entrance-latency-us = <3>; 237 + 238 + bus-range = <0x0 0xff>; 239 + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */ 240 + <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */ 241 + <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */ 242 + 243 + vddio-pex-ctl-supply = <&vdd_1v8ao>; 244 + vpcie3v3-supply = <&vdd_3v3_pcie>; 245 + vpcie12v-supply = <&vdd_12v_pcie>; 246 + 247 + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, 248 + <&p2u_hsio_5>; 249 + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 250 + }; 251 + };
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Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
··· 34 34 minItems: 2 35 35 maxItems: 5 36 36 items: 37 - enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link, 38 - ulreg, smu, mpu, apb, phy ] 37 + enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl, 38 + parf, cfg, link, ulreg, smu, mpu, apb, phy ] 39 39 40 40 num-lanes: 41 41 description: |