Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: sifive: Use reset-simple in prci driver for PCIe driver

We use reset-simple in this patch so that pcie driver can use
devm_reset_control_get() to get this reset data structure and use
reset_control_deassert() to deassert pcie_power_up_rst_n.

Link: https://lore.kernel.org/r/20210504105940.100004-3-greentime.hu@sifive.com
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>

authored by

Greentime Hu and committed by
Lorenzo Pieralisi
e4d368e0 c61287bf

+20
+2
drivers/clk/sifive/Kconfig
··· 10 10 11 11 config CLK_SIFIVE_PRCI 12 12 bool "PRCI driver for SiFive SoCs" 13 + select RESET_CONTROLLER 14 + select RESET_SIMPLE 13 15 select CLK_ANALOGBITS_WRPLL_CLN28HPC 14 16 help 15 17 Supports the Power Reset Clock interface (PRCI) IP block found in
+13
drivers/clk/sifive/sifive-prci.c
··· 588 588 if (IS_ERR(pd->va)) 589 589 return PTR_ERR(pd->va); 590 590 591 + pd->reset.rcdev.owner = THIS_MODULE; 592 + pd->reset.rcdev.nr_resets = PRCI_RST_NR; 593 + pd->reset.rcdev.ops = &reset_simple_ops; 594 + pd->reset.rcdev.of_node = pdev->dev.of_node; 595 + pd->reset.active_low = true; 596 + pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET; 597 + spin_lock_init(&pd->reset.lock); 598 + 599 + r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev); 600 + if (r) { 601 + dev_err(dev, "could not register reset controller: %d\n", r); 602 + return r; 603 + } 591 604 r = __prci_register_clocks(dev, pd, desc); 592 605 if (r) { 593 606 dev_err(dev, "could not register clocks: %d\n", r);
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drivers/clk/sifive/sifive-prci.h
··· 11 11 12 12 #include <linux/clk/analogbits-wrpll-cln28hpc.h> 13 13 #include <linux/clk-provider.h> 14 + #include <linux/reset/reset-simple.h> 14 15 #include <linux/platform_device.h> 15 16 16 17 /* ··· 122 121 #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ 123 122 (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) 124 123 124 + #define PRCI_RST_NR 7 125 + 125 126 /* CLKMUXSTATUSREG */ 126 127 #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c 127 128 #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 ··· 224 221 */ 225 222 struct __prci_data { 226 223 void __iomem *va; 224 + struct reset_simple_data reset; 227 225 struct clk_hw_onecell_data hw_clks; 228 226 }; 229 227
+1
drivers/reset/Kconfig
··· 197 197 - RCC reset controller in STM32 MCUs 198 198 - Allwinner SoCs 199 199 - ZTE's zx2967 family 200 + - SiFive FU740 SoCs 200 201 201 202 config RESET_STM32MP157 202 203 bool "STM32MP157 Reset Driver" if COMPILE_TEST