tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: Lantiq: Add PCI controller support.
The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds
the driver that allows us to use the EBU as a PCI controller. In order for
PCI to work the EBU is set to endianess swap all the data. In addition we
need to make use of SWAP_IO_SPACE for device->host DMA to work.
The clock of the PCI works in several modes (internal/external). If this
is not configured correctly the SoC will hang.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2250/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
John Crispin
and committed by
Ralf Baechle
e47d4889
8ec6d935
+478
+46
arch/mips/include/asm/mach-lantiq/lantiq_platform.h
+46
arch/mips/include/asm/mach-lantiq/lantiq_platform.h
···
1
+
/*
2
+
* This program is free software; you can redistribute it and/or modify it
3
+
* under the terms of the GNU General Public License version 2 as published
4
+
* by the Free Software Foundation.
5
+
*
6
+
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7
+
*/
8
+
9
+
#ifndef _LANTIQ_PLATFORM_H__
10
+
#define _LANTIQ_PLATFORM_H__
11
+
12
+
#include <linux/mtd/partitions.h>
13
+
14
+
/* struct used to pass info to the pci core */
15
+
enum {
16
+
PCI_CLOCK_INT = 0,
17
+
PCI_CLOCK_EXT
18
+
};
19
+
20
+
#define PCI_EXIN0 0x0001
21
+
#define PCI_EXIN1 0x0002
22
+
#define PCI_EXIN2 0x0004
23
+
#define PCI_EXIN3 0x0008
24
+
#define PCI_EXIN4 0x0010
25
+
#define PCI_EXIN5 0x0020
26
+
#define PCI_EXIN_MAX 6
27
+
28
+
#define PCI_GNT1 0x0040
29
+
#define PCI_GNT2 0x0080
30
+
#define PCI_GNT3 0x0100
31
+
#define PCI_GNT4 0x0200
32
+
33
+
#define PCI_REQ1 0x0400
34
+
#define PCI_REQ2 0x0800
35
+
#define PCI_REQ3 0x1000
36
+
#define PCI_REQ4 0x2000
37
+
#define PCI_REQ_SHIFT 10
38
+
#define PCI_REQ_MASK 0xf
39
+
40
+
struct ltq_pci_data {
41
+
int clock;
42
+
int gpio;
43
+
int irq[16];
44
+
};
45
+
46
+
#endif
+1
arch/mips/pci/Makefile
+1
arch/mips/pci/Makefile
···
41
41
obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
42
42
obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
43
43
obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
44
+
obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o
44
45
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
45
46
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
46
47
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
+116
arch/mips/pci/ops-lantiq.c
+116
arch/mips/pci/ops-lantiq.c
···
1
+
/*
2
+
* This program is free software; you can redistribute it and/or modify it
3
+
* under the terms of the GNU General Public License version 2 as published
4
+
* by the Free Software Foundation.
5
+
*
6
+
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7
+
*/
8
+
9
+
#include <linux/types.h>
10
+
#include <linux/pci.h>
11
+
#include <linux/kernel.h>
12
+
#include <linux/init.h>
13
+
#include <linux/delay.h>
14
+
#include <linux/mm.h>
15
+
#include <asm/addrspace.h>
16
+
#include <linux/vmalloc.h>
17
+
18
+
#include <lantiq_soc.h>
19
+
20
+
#include "pci-lantiq.h"
21
+
22
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#define LTQ_PCI_CFG_BUSNUM_SHF 16
23
+
#define LTQ_PCI_CFG_DEVNUM_SHF 11
24
+
#define LTQ_PCI_CFG_FUNNUM_SHF 8
25
+
26
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#define PCI_ACCESS_READ 0
27
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#define PCI_ACCESS_WRITE 1
28
+
29
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static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
30
+
unsigned int devfn, unsigned int where, u32 *data)
31
+
{
32
+
unsigned long cfg_base;
33
+
unsigned long flags;
34
+
u32 temp;
35
+
36
+
/* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the
37
+
SoC itself */
38
+
if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
39
+
|| ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
40
+
return 1;
41
+
42
+
spin_lock_irqsave(&ebu_lock, flags);
43
+
44
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cfg_base = (unsigned long) ltq_pci_mapped_cfg;
45
+
cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
46
+
LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
47
+
48
+
/* Perform access */
49
+
if (access_type == PCI_ACCESS_WRITE) {
50
+
ltq_w32(swab32(*data), ((u32 *)cfg_base));
51
+
} else {
52
+
*data = ltq_r32(((u32 *)(cfg_base)));
53
+
*data = swab32(*data);
54
+
}
55
+
wmb();
56
+
57
+
/* clean possible Master abort */
58
+
cfg_base = (unsigned long) ltq_pci_mapped_cfg;
59
+
cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
60
+
temp = ltq_r32(((u32 *)(cfg_base)));
61
+
temp = swab32(temp);
62
+
cfg_base = (unsigned long) ltq_pci_mapped_cfg;
63
+
cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
64
+
ltq_w32(temp, ((u32 *)cfg_base));
65
+
66
+
spin_unlock_irqrestore(&ebu_lock, flags);
67
+
68
+
if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
69
+
return 1;
70
+
71
+
return 0;
72
+
}
73
+
74
+
int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
75
+
int where, int size, u32 *val)
76
+
{
77
+
u32 data = 0;
78
+
79
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if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
80
+
return PCIBIOS_DEVICE_NOT_FOUND;
81
+
82
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if (size == 1)
83
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*val = (data >> ((where & 3) << 3)) & 0xff;
84
+
else if (size == 2)
85
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*val = (data >> ((where & 3) << 3)) & 0xffff;
86
+
else
87
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*val = data;
88
+
89
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return PCIBIOS_SUCCESSFUL;
90
+
}
91
+
92
+
int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
93
+
int where, int size, u32 val)
94
+
{
95
+
u32 data = 0;
96
+
97
+
if (size == 4) {
98
+
data = val;
99
+
} else {
100
+
if (ltq_pci_config_access(PCI_ACCESS_READ, bus,
101
+
devfn, where, &data))
102
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return PCIBIOS_DEVICE_NOT_FOUND;
103
+
104
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if (size == 1)
105
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data = (data & ~(0xff << ((where & 3) << 3))) |
106
+
(val << ((where & 3) << 3));
107
+
else if (size == 2)
108
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data = (data & ~(0xffff << ((where & 3) << 3))) |
109
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(val << ((where & 3) << 3));
110
+
}
111
+
112
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if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
113
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return PCIBIOS_DEVICE_NOT_FOUND;
114
+
115
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return PCIBIOS_SUCCESSFUL;
116
+
}
+297
arch/mips/pci/pci-lantiq.c
+297
arch/mips/pci/pci-lantiq.c
···
1
+
/*
2
+
* This program is free software; you can redistribute it and/or modify it
3
+
* under the terms of the GNU General Public License version 2 as published
4
+
* by the Free Software Foundation.
5
+
*
6
+
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7
+
*/
8
+
9
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#include <linux/types.h>
10
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#include <linux/pci.h>
11
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#include <linux/kernel.h>
12
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#include <linux/init.h>
13
+
#include <linux/delay.h>
14
+
#include <linux/mm.h>
15
+
#include <linux/vmalloc.h>
16
+
#include <linux/platform_device.h>
17
+
18
+
#include <asm/pci.h>
19
+
#include <asm/gpio.h>
20
+
#include <asm/addrspace.h>
21
+
22
+
#include <lantiq_soc.h>
23
+
#include <lantiq_irq.h>
24
+
#include <lantiq_platform.h>
25
+
26
+
#include "pci-lantiq.h"
27
+
28
+
#define LTQ_PCI_CFG_BASE 0x17000000
29
+
#define LTQ_PCI_CFG_SIZE 0x00008000
30
+
#define LTQ_PCI_MEM_BASE 0x18000000
31
+
#define LTQ_PCI_MEM_SIZE 0x02000000
32
+
#define LTQ_PCI_IO_BASE 0x1AE00000
33
+
#define LTQ_PCI_IO_SIZE 0x00200000
34
+
35
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#define PCI_CR_FCI_ADDR_MAP0 0x00C0
36
+
#define PCI_CR_FCI_ADDR_MAP1 0x00C4
37
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#define PCI_CR_FCI_ADDR_MAP2 0x00C8
38
+
#define PCI_CR_FCI_ADDR_MAP3 0x00CC
39
+
#define PCI_CR_FCI_ADDR_MAP4 0x00D0
40
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#define PCI_CR_FCI_ADDR_MAP5 0x00D4
41
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#define PCI_CR_FCI_ADDR_MAP6 0x00D8
42
+
#define PCI_CR_FCI_ADDR_MAP7 0x00DC
43
+
#define PCI_CR_CLK_CTRL 0x0000
44
+
#define PCI_CR_PCI_MOD 0x0030
45
+
#define PCI_CR_PC_ARB 0x0080
46
+
#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4
47
+
#define PCI_CR_BAR11MASK 0x0044
48
+
#define PCI_CR_BAR12MASK 0x0048
49
+
#define PCI_CR_BAR13MASK 0x004C
50
+
#define PCI_CS_BASE_ADDR1 0x0010
51
+
#define PCI_CR_PCI_ADDR_MAP11 0x0064
52
+
#define PCI_CR_FCI_BURST_LENGTH 0x00E8
53
+
#define PCI_CR_PCI_EOI 0x002C
54
+
#define PCI_CS_STS_CMD 0x0004
55
+
56
+
#define PCI_MASTER0_REQ_MASK_2BITS 8
57
+
#define PCI_MASTER1_REQ_MASK_2BITS 10
58
+
#define PCI_MASTER2_REQ_MASK_2BITS 12
59
+
#define INTERNAL_ARB_ENABLE_BIT 0
60
+
61
+
#define LTQ_CGU_IFCCR 0x0018
62
+
#define LTQ_CGU_PCICR 0x0034
63
+
64
+
#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
65
+
#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
66
+
67
+
#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
68
+
#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
69
+
70
+
struct ltq_pci_gpio_map {
71
+
int pin;
72
+
int alt0;
73
+
int alt1;
74
+
int dir;
75
+
char *name;
76
+
};
77
+
78
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/* the pci core can make use of the following gpios */
79
+
static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
80
+
{ 0, 1, 0, 0, "pci-exin0" },
81
+
{ 1, 1, 0, 0, "pci-exin1" },
82
+
{ 2, 1, 0, 0, "pci-exin2" },
83
+
{ 39, 1, 0, 0, "pci-exin3" },
84
+
{ 10, 1, 0, 0, "pci-exin4" },
85
+
{ 9, 1, 0, 0, "pci-exin5" },
86
+
{ 30, 1, 0, 1, "pci-gnt1" },
87
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{ 23, 1, 0, 1, "pci-gnt2" },
88
+
{ 19, 1, 0, 1, "pci-gnt3" },
89
+
{ 38, 1, 0, 1, "pci-gnt4" },
90
+
{ 29, 1, 0, 0, "pci-req1" },
91
+
{ 31, 1, 0, 0, "pci-req2" },
92
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{ 3, 1, 0, 0, "pci-req3" },
93
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{ 37, 1, 0, 0, "pci-req4" },
94
+
};
95
+
96
+
__iomem void *ltq_pci_mapped_cfg;
97
+
static __iomem void *ltq_pci_membase;
98
+
99
+
int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
100
+
101
+
/* Since the PCI REQ pins can be reused for other functionality, make it
102
+
possible to exclude those from interpretation by the PCI controller */
103
+
static int ltq_pci_req_mask = 0xf;
104
+
105
+
static int *ltq_pci_irq_map;
106
+
107
+
struct pci_ops ltq_pci_ops = {
108
+
.read = ltq_pci_read_config_dword,
109
+
.write = ltq_pci_write_config_dword
110
+
};
111
+
112
+
static struct resource pci_io_resource = {
113
+
.name = "pci io space",
114
+
.start = LTQ_PCI_IO_BASE,
115
+
.end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1,
116
+
.flags = IORESOURCE_IO
117
+
};
118
+
119
+
static struct resource pci_mem_resource = {
120
+
.name = "pci memory space",
121
+
.start = LTQ_PCI_MEM_BASE,
122
+
.end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1,
123
+
.flags = IORESOURCE_MEM
124
+
};
125
+
126
+
static struct pci_controller ltq_pci_controller = {
127
+
.pci_ops = <q_pci_ops,
128
+
.mem_resource = &pci_mem_resource,
129
+
.mem_offset = 0x00000000UL,
130
+
.io_resource = &pci_io_resource,
131
+
.io_offset = 0x00000000UL,
132
+
};
133
+
134
+
int pcibios_plat_dev_init(struct pci_dev *dev)
135
+
{
136
+
if (ltqpci_plat_dev_init)
137
+
return ltqpci_plat_dev_init(dev);
138
+
139
+
return 0;
140
+
}
141
+
142
+
static u32 ltq_calc_bar11mask(void)
143
+
{
144
+
u32 mem, bar11mask;
145
+
146
+
/* BAR11MASK value depends on available memory on system. */
147
+
mem = num_physpages * PAGE_SIZE;
148
+
bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
149
+
150
+
return bar11mask;
151
+
}
152
+
153
+
static void ltq_pci_setup_gpio(int gpio)
154
+
{
155
+
int i;
156
+
for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
157
+
if (gpio & (1 << i)) {
158
+
ltq_gpio_request(ltq_pci_gpio_map[i].pin,
159
+
ltq_pci_gpio_map[i].alt0,
160
+
ltq_pci_gpio_map[i].alt1,
161
+
ltq_pci_gpio_map[i].dir,
162
+
ltq_pci_gpio_map[i].name);
163
+
}
164
+
}
165
+
ltq_gpio_request(21, 0, 0, 1, "pci-reset");
166
+
ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
167
+
}
168
+
169
+
static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
170
+
{
171
+
u32 temp_buffer;
172
+
173
+
/* set clock to 33Mhz */
174
+
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
175
+
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
176
+
177
+
/* external or internal clock ? */
178
+
if (conf->clock) {
179
+
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16),
180
+
LTQ_CGU_IFCCR);
181
+
ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR);
182
+
} else {
183
+
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16),
184
+
LTQ_CGU_IFCCR);
185
+
ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR);
186
+
}
187
+
188
+
/* setup pci clock and gpis used by pci */
189
+
ltq_pci_setup_gpio(conf->gpio);
190
+
191
+
/* enable auto-switching between PCI and EBU */
192
+
ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
193
+
194
+
/* busy, i.e. configuration is not done, PCI access has to be retried */
195
+
ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
196
+
wmb();
197
+
/* BUS Master/IO/MEM access */
198
+
ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
199
+
200
+
/* enable external 2 PCI masters */
201
+
temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
202
+
temp_buffer &= (~(ltq_pci_req_mask << 16));
203
+
/* enable internal arbiter */
204
+
temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
205
+
/* enable internal PCI master reqest */
206
+
temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
207
+
208
+
/* enable EBU request */
209
+
temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
210
+
211
+
/* enable all external masters request */
212
+
temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
213
+
ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
214
+
wmb();
215
+
216
+
/* setup BAR memory regions */
217
+
ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
218
+
ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
219
+
ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
220
+
ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
221
+
ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
222
+
ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
223
+
ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
224
+
ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
225
+
ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
226
+
ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
227
+
ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
228
+
ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
229
+
/* both TX and RX endian swap are enabled */
230
+
ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
231
+
wmb();
232
+
ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
233
+
PCI_CR_BAR12MASK);
234
+
ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
235
+
PCI_CR_BAR13MASK);
236
+
/*use 8 dw burst length */
237
+
ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
238
+
ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
239
+
wmb();
240
+
241
+
/* setup irq line */
242
+
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
243
+
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
244
+
245
+
/* toggle reset pin */
246
+
__gpio_set_value(21, 0);
247
+
wmb();
248
+
mdelay(1);
249
+
__gpio_set_value(21, 1);
250
+
return 0;
251
+
}
252
+
253
+
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
254
+
{
255
+
if (ltq_pci_irq_map[slot])
256
+
return ltq_pci_irq_map[slot];
257
+
printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
258
+
slot);
259
+
260
+
return 0;
261
+
}
262
+
263
+
static int __devinit ltq_pci_probe(struct platform_device *pdev)
264
+
{
265
+
struct ltq_pci_data *ltq_pci_data =
266
+
(struct ltq_pci_data *) pdev->dev.platform_data;
267
+
pci_probe_only = 0;
268
+
ltq_pci_irq_map = ltq_pci_data->irq;
269
+
ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
270
+
ltq_pci_mapped_cfg =
271
+
ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
272
+
ltq_pci_controller.io_map_base =
273
+
(unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
274
+
ltq_pci_startup(ltq_pci_data);
275
+
register_pci_controller(<q_pci_controller);
276
+
277
+
return 0;
278
+
}
279
+
280
+
static struct platform_driver
281
+
ltq_pci_driver = {
282
+
.probe = ltq_pci_probe,
283
+
.driver = {
284
+
.name = "ltq_pci",
285
+
.owner = THIS_MODULE,
286
+
},
287
+
};
288
+
289
+
int __init pcibios_init(void)
290
+
{
291
+
int ret = platform_driver_register(<q_pci_driver);
292
+
if (ret)
293
+
printk(KERN_INFO "ltq_pci: Error registering platfom driver!");
294
+
return ret;
295
+
}
296
+
297
+
arch_initcall(pcibios_init);
+18
arch/mips/pci/pci-lantiq.h
+18
arch/mips/pci/pci-lantiq.h
···
1
+
/*
2
+
* This program is free software; you can redistribute it and/or modify it
3
+
* under the terms of the GNU General Public License version 2 as published
4
+
* by the Free Software Foundation.
5
+
*
6
+
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7
+
*/
8
+
9
+
#ifndef _LTQ_PCI_H__
10
+
#define _LTQ_PCI_H__
11
+
12
+
extern __iomem void *ltq_pci_mapped_cfg;
13
+
extern int ltq_pci_read_config_dword(struct pci_bus *bus,
14
+
unsigned int devfn, int where, int size, u32 *val);
15
+
extern int ltq_pci_write_config_dword(struct pci_bus *bus,
16
+
unsigned int devfn, int where, int size, u32 val);
17
+
18
+
#endif