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arm64/mm: Add FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2]

PAGE_SIZE support is tested against possible minimum and maximum values for
its respective ID_AA64MMFR0.TGRAN field, depending on whether it is signed
or unsigned. But then FEAT_LPA2 implementation needs to be validated for 4K
and 16K page sizes via feature specific ID_AA64MMFR0.TGRAN values. Hence it
adds FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] values per ARM ARM (0487G.A).

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20231127111737.1897081-5-ryan.roberts@arm.com

authored by

Anshuman Khandual and committed by
Marc Zyngier e477c8c4 c910f2b6

+5
+5
arch/arm64/include/asm/sysreg.h
··· 871 871 872 872 /* id_aa64mmfr0 */ 873 873 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 874 + #define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT 874 875 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 875 876 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 876 877 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 877 878 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 879 + #define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT 878 880 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf 879 881 880 882 #define ARM64_MIN_PARANGE_BITS 32 ··· 884 882 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 885 883 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 886 884 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 885 + #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3 887 886 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 888 887 889 888 #ifdef CONFIG_ARM64_PA_BITS_52 ··· 895 892 896 893 #if defined(CONFIG_ARM64_4K_PAGES) 897 894 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT 895 + #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT 898 896 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 899 897 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 900 898 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 901 899 #elif defined(CONFIG_ARM64_16K_PAGES) 902 900 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT 901 + #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT 903 902 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 904 903 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 905 904 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT