tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro

Convert the boilerplate code for manual addition of the watchdog clock
to the new SGRF_GATE macro for all affected socs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Heiko Stuebner e4488e45 b3b723d8

+12 -36
+3 -9
drivers/clk/rockchip/clk-px30.c
··· 803 803 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS), 804 804 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS), 805 805 806 + /* aclk_dmac is controlled by sgrf_soc_con1[11]. */ 807 + SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"), 808 + 806 809 GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS), 807 810 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS), 808 811 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS), ··· 969 966 { 970 967 struct rockchip_clk_provider *ctx; 971 968 void __iomem *reg_base; 972 - struct clk *clk; 973 969 974 970 reg_base = of_iomap(np, 0); 975 971 if (!reg_base) { ··· 982 980 iounmap(reg_base); 983 981 return; 984 982 } 985 - 986 - /* aclk_dmac is controlled by sgrf_soc_con1[11]. */ 987 - clk = clk_register_fixed_factor(NULL, "aclk_dmac", "aclk_bus_pre", 0, 1, 1); 988 - if (IS_ERR(clk)) 989 - pr_warn("%s: could not register clock aclk_dmac: %ld\n", 990 - __func__, PTR_ERR(clk)); 991 - else 992 - rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC); 993 983 994 984 rockchip_clk_register_plls(ctx, px30_pll_clks, 995 985 ARRAY_SIZE(px30_pll_clks),
+3 -9
drivers/clk/rockchip/clk-rk3288.c
··· 775 775 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS), 776 776 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS), 777 777 778 + /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ 779 + SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"), 780 + 778 781 /* pclk_pd_pmu gates */ 779 782 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS), 780 783 GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS), ··· 926 923 static void __init rk3288_clk_init(struct device_node *np) 927 924 { 928 925 struct rockchip_clk_provider *ctx; 929 - struct clk *clk; 930 926 931 927 rk3288_cru_base = of_iomap(np, 0); 932 928 if (!rk3288_cru_base) { ··· 939 937 iounmap(rk3288_cru_base); 940 938 return; 941 939 } 942 - 943 - /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ 944 - clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1); 945 - if (IS_ERR(clk)) 946 - pr_warn("%s: could not register clock pclk_wdt: %ld\n", 947 - __func__, PTR_ERR(clk)); 948 - else 949 - rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); 950 940 951 941 rockchip_clk_register_plls(ctx, rk3288_pll_clks, 952 942 ARRAY_SIZE(rk3288_pll_clks),
+3 -9
drivers/clk/rockchip/clk-rk3368.c
··· 820 820 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS), 821 821 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS), 822 822 823 + /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */ 824 + SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"), 825 + 823 826 /* 824 827 * pclk_vio gates 825 828 * pclk_vio comes from the exactly same source as hclk_vio ··· 874 871 { 875 872 struct rockchip_clk_provider *ctx; 876 873 void __iomem *reg_base; 877 - struct clk *clk; 878 874 879 875 reg_base = of_iomap(np, 0); 880 876 if (!reg_base) { ··· 887 885 iounmap(reg_base); 888 886 return; 889 887 } 890 - 891 - /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */ 892 - clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1); 893 - if (IS_ERR(clk)) 894 - pr_warn("%s: could not register clock pclk_wdt: %ld\n", 895 - __func__, PTR_ERR(clk)); 896 - else 897 - rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); 898 888 899 889 rockchip_clk_register_plls(ctx, rk3368_pll_clks, 900 890 ARRAY_SIZE(rk3368_pll_clks),
+3 -9
drivers/clk/rockchip/clk-rk3399.c
··· 1304 1304 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS), 1305 1305 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS), 1306 1306 1307 + /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ 1308 + SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"), 1309 + 1307 1310 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS), 1308 1311 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS), 1309 1312 ··· 1534 1531 { 1535 1532 struct rockchip_clk_provider *ctx; 1536 1533 void __iomem *reg_base; 1537 - struct clk *clk; 1538 1534 1539 1535 reg_base = of_iomap(np, 0); 1540 1536 if (!reg_base) { ··· 1547 1545 iounmap(reg_base); 1548 1546 return; 1549 1547 } 1550 - 1551 - /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ 1552 - clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1); 1553 - if (IS_ERR(clk)) 1554 - pr_warn("%s: could not register clock pclk_wdt: %ld\n", 1555 - __func__, PTR_ERR(clk)); 1556 - else 1557 - rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); 1558 1548 1559 1549 rockchip_clk_register_plls(ctx, rk3399_pll_clks, 1560 1550 ARRAY_SIZE(rk3399_pll_clks), -1);