···8080 seg_ptr = skb->data;8181 /*8282 * Transform from little endian to big endian8383- * and pending zero8383+ * and pending zero8484 */8585 for(i=0 ; i < frag_length; i+=4) {8686 *seg_ptr++ = ((i+0)<frag_length)?code_virtual_address[i+3]:0;···218218{219219 bool rt_status = true;220220 int check_putcodeOK_time = 200000, check_bootOk_time = 200000;221221- u32 CPU_status = 0;221221+ u32 CPU_status = 0;222222223223 /* Check whether put code OK */224224 do {···299299 bool rt_status = TRUE;300300301301 u8 *firmware_img_buf[3] = { &rtl8190_fwboot_array[0],302302- &rtl8190_fwmain_array[0],303303- &rtl8190_fwdata_array[0]};302302+ &rtl8190_fwmain_array[0],303303+ &rtl8190_fwdata_array[0]};304304305305 u32 firmware_img_len[3] = { sizeof(rtl8190_fwboot_array),306306- sizeof(rtl8190_fwmain_array),307307- sizeof(rtl8190_fwdata_array)};306306+ sizeof(rtl8190_fwmain_array),307307+ sizeof(rtl8190_fwdata_array)};308308 u32 file_length = 0;309309 u8 *mapped_file = NULL;310310 u32 init_step = 0;···314314 rt_firmware *pfirmware = priv->pFirmware;315315 const struct firmware *fw_entry;316316 const char *fw_name[3] = { "RTL8192U/boot.img",317317- "RTL8192U/main.img",317317+ "RTL8192U/main.img",318318 "RTL8192U/data.img"};319319 int rc;320320···490490#if 0491491/*492492 * Procedure: (1) Transform firmware code from little endian to big endian if required.493493- * (2) Number of bytes in Firmware downloading should be multiple494494- * of 4 bytes. If length is not multiple of 4 bytes, appending of zeros is required493493+ * (2) Number of bytes in Firmware downloading should be multiple494494+ * of 4 bytes. If length is not multiple of 4 bytes, appending of zeros is required495495 *496496 */497497void CmdAppendZeroAndEndianTransform(
+11-11
drivers/staging/rtl8192u/r819xU_phy.c
···9494 {//if not "double word" write9595 OriginalValue = read_nic_dword(dev, dwRegAddr);9696 BitShift = rtl8192_CalculateBitShift(dwBitMask);9797- NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));9797+ NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));9898 write_nic_dword(dev, dwRegAddr, NewValue);9999 }else100100 write_nic_dword(dev, dwRegAddr, dwData);···265265 priv->RfReg0Value[eRFPath] = Data;266266267267 // Switch back to Reg_Mode0;268268- if(priv->rf_chip == RF_8256)268268+ if(priv->rf_chip == RF_8256)269269 {270270 if(Offset != 0)271271 {···320320 else321321 {322322 if (BitMask != bMask12Bits) // RF data is 12 bits only323323- {323323+ {324324 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);325325- BitShift = rtl8192_CalculateBitShift(BitMask);326326- New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));325325+ BitShift = rtl8192_CalculateBitShift(BitMask);326326+ New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));327327328328 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);329329- }else329329+ }else330330 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);331331 }332332 return;···360360 else361361 {362362 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);363363- BitShift = rtl8192_CalculateBitShift(BitMask);364364- Readback_Value = (Original_Value & BitMask) >> BitShift;363363+ BitShift = rtl8192_CalculateBitShift(BitMask);364364+ Readback_Value = (Original_Value & BitMask) >> BitShift;365365 return (Readback_Value);366366 }367367}···800800 dwRegValue = read_nic_dword(dev, CPU_GEN);801801 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));802802803803- /*----BB AGC table Initialization----*/803803+ /*----BB AGC table Initialization----*/804804 //==m==>Set PHY REG From Header<==m==805805 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);806806···1563156315641564 case HT_CHANNEL_WIDTH_20_40:15651565 regBwOpMode &= ~BW_OPMODE_20MHZ;15661566- // 2007/02/07 Mark by Emily becasue we have not verify whether this register works15661566+ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works15671567 write_nic_byte(dev, BW_OPMODE, regBwOpMode);15681568 break;15691569···16151615 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);16161616 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);16171617 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));16181618- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);16181618+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);16191619 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);16201620#if 016211621 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207