tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next
* clk-renesas: (42 commits)
clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
clk: renesas: r9a09g057: Add XSPI clock/reset
clk: renesas: r9a09g056: Add XSPI clock/reset
clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
clk: renesas: r9a09g057: Add support for xspi mux and divider
clk: renesas: r9a09g056: Add support for xspi mux and divider
clk: renesas: r9a09g077: Add RIIC module clocks
clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
clk: renesas: r9a09g057: Add entries for the RSPIs
dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
clk: renesas: rzv2h: Add missing include file
clk: renesas: rzv2h: Use devm_kmemdup_array()
clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
clk: renesas: r9a09g077: Add PCLKL core clock
dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
...
* clk-samsung:
clk: samsung: exynosautov920: add block hsi2 clock support
dt-bindings: clock: exynosautov920: add hsi2 clock definitions
dt-bindings: clock: exynosautov920: sort clock definitions
clk: samsung: exynos850: fix a comment
clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock
clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD
* clk-spacemit:
clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
reset: spacemit: add support for SpacemiT CCU resets
clk: spacemit: mark K1 pll1_d8 as critical
clk: spacemit: define three reset-only CCUs
clk: spacemit: set up reset auxiliary devices
soc: spacemit: create a header for clock/reset registers
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
* clk-allwinner:
clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
clk: sunxi-ng: v3s: Fix de clock definition
clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
* clk-amlogic:
clk: amlogic: s4: remove unused data
clk: amlogic: drop clk_regmap tables
clk: amlogic: get regmap with clk_regmap_init
clk: amlogic: remove unnecessary headers
clk: amlogic: axg-audio: use the auxiliary reset driver
+3346
-4250
+38
-11
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+38
-11
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
···
52
52
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
53
53
- renesas,r8a779g0-cpg-mssr # R-Car V4H
54
54
- renesas,r8a779h0-cpg-mssr # R-Car V4M
55
+
- renesas,r9a09g077-cpg-mssr # RZ/T2H
56
+
- renesas,r9a09g087-cpg-mssr # RZ/N2H
55
57
56
58
reg:
57
-
maxItems: 1
59
+
minItems: 1
60
+
items:
61
+
- description: base address of register block 0
62
+
- description: base address of register block 1
63
+
description: base addresses of clock controller. Some controllers
64
+
(like r9a09g077) use two blocks instead of a single one.
58
65
59
66
clocks:
60
67
minItems: 1
···
99
92
the datasheet.
100
93
const: 1
101
94
102
-
if:
103
-
not:
104
-
properties:
105
-
compatible:
106
-
items:
107
-
enum:
108
-
- renesas,r7s9210-cpg-mssr
109
-
then:
110
-
required:
111
-
- '#reset-cells'
112
95
113
96
required:
114
97
- compatible
···
107
110
- clock-names
108
111
- '#clock-cells'
109
112
- '#power-domain-cells'
113
+
114
+
allOf:
115
+
- if:
116
+
properties:
117
+
compatible:
118
+
contains:
119
+
enum:
120
+
- renesas,r9a09g077-cpg-mssr
121
+
- renesas,r9a09g087-cpg-mssr
122
+
then:
123
+
properties:
124
+
reg:
125
+
minItems: 2
126
+
clock-names:
127
+
items:
128
+
- const: extal
129
+
else:
130
+
properties:
131
+
reg:
132
+
maxItems: 1
133
+
- if:
134
+
not:
135
+
properties:
136
+
compatible:
137
+
items:
138
+
enum:
139
+
- renesas,r7s9210-cpg-mssr
140
+
then:
141
+
required:
142
+
- '#reset-cells'
110
143
111
144
additionalProperties: false
112
145
+1
-17
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+1
-17
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
···
57
57
can be power-managed through Module Standby should refer to the CPG device
58
58
node in their "power-domains" property, as documented by the generic PM
59
59
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
60
-
The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
61
-
be used to reference individual CPG power domains.
60
+
const: 0
62
61
63
62
'#reset-cells':
64
63
description:
···
75
76
- '#reset-cells'
76
77
77
78
additionalProperties: false
78
-
79
-
allOf:
80
-
- if:
81
-
properties:
82
-
compatible:
83
-
contains:
84
-
const: renesas,r9a08g045-cpg
85
-
then:
86
-
properties:
87
-
'#power-domain-cells':
88
-
const: 1
89
-
else:
90
-
properties:
91
-
'#power-domain-cells':
92
-
const: 0
93
79
94
80
examples:
95
81
- |
+31
-6
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
+31
-6
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
···
32
32
properties:
33
33
compatible:
34
34
enum:
35
-
- samsung,exynosautov920-cmu-top
36
35
- samsung,exynosautov920-cmu-cpucl0
37
36
- samsung,exynosautov920-cmu-cpucl1
38
37
- samsung,exynosautov920-cmu-cpucl2
39
-
- samsung,exynosautov920-cmu-peric0
40
-
- samsung,exynosautov920-cmu-peric1
41
-
- samsung,exynosautov920-cmu-misc
42
38
- samsung,exynosautov920-cmu-hsi0
43
39
- samsung,exynosautov920-cmu-hsi1
40
+
- samsung,exynosautov920-cmu-hsi2
41
+
- samsung,exynosautov920-cmu-misc
42
+
- samsung,exynosautov920-cmu-peric0
43
+
- samsung,exynosautov920-cmu-peric1
44
+
- samsung,exynosautov920-cmu-top
44
45
45
46
clocks:
46
47
minItems: 1
47
-
maxItems: 4
48
+
maxItems: 5
48
49
49
50
clock-names:
50
51
minItems: 1
51
-
maxItems: 4
52
+
maxItems: 5
52
53
53
54
"#clock-cells":
54
55
const: 1
···
201
200
- const: noc
202
201
- const: usbdrd
203
202
- const: mmc_card
203
+
204
+
- if:
205
+
properties:
206
+
compatible:
207
+
contains:
208
+
const: samsung,exynosautov920-cmu-hsi2
209
+
210
+
then:
211
+
properties:
212
+
clocks:
213
+
items:
214
+
- description: External reference clock (38.4 MHz)
215
+
- description: CMU_HSI2 NOC clock (from CMU_TOP)
216
+
- description: CMU_HSI2 NOC UFS clock (from CMU_TOP)
217
+
- description: CMU_HSI2 UFS EMBD clock (from CMU_TOP)
218
+
- description: CMU_HSI2 ETHERNET clock (from CMU_TOP)
219
+
220
+
clock-names:
221
+
items:
222
+
- const: oscclk
223
+
- const: noc
224
+
- const: ufs
225
+
- const: embd
226
+
- const: ethernet
204
227
205
228
required:
206
229
- compatible
+10
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+10
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
···
602
602
- renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
603
603
- const: renesas,r9a09g077
604
604
605
+
- description: RZ/N2H (R9A09G087)
606
+
items:
607
+
- enum:
608
+
- renesas,rzn2h-evk # RZ/N2H Evaluation Board (RTK9RZN2H0S00000BJ)
609
+
- enum:
610
+
- renesas,r9a09g087m04 # RZ/N2H with Single Cortex-A55 + Dual Cortex-R52 - no security
611
+
- renesas,r9a09g087m24 # RZ/N2H with Dual Cortex-A55 + Dual Cortex-R52 - no security
612
+
- renesas,r9a09g087m44 # RZ/N2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
613
+
- const: renesas,r9a09g087
614
+
605
615
additionalProperties: true
606
616
607
617
...
+22
-7
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
+22
-7
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
···
19
19
- spacemit,k1-syscon-apbc
20
20
- spacemit,k1-syscon-apmu
21
21
- spacemit,k1-syscon-mpmu
22
+
- spacemit,k1-syscon-rcpu
23
+
- spacemit,k1-syscon-rcpu2
24
+
- spacemit,k1-syscon-apbc2
22
25
23
26
reg:
24
27
maxItems: 1
···
50
47
required:
51
48
- compatible
52
49
- reg
53
-
- clocks
54
-
- clock-names
55
-
- "#clock-cells"
56
50
- "#reset-cells"
57
51
58
52
allOf:
···
57
57
properties:
58
58
compatible:
59
59
contains:
60
-
const: spacemit,k1-syscon-apbc
60
+
enum:
61
+
- spacemit,k1-syscon-apmu
62
+
- spacemit,k1-syscon-mpmu
61
63
then:
62
-
properties:
63
-
"#power-domain-cells": false
64
-
else:
65
64
required:
66
65
- "#power-domain-cells"
66
+
else:
67
+
properties:
68
+
"#power-domain-cells": false
69
+
- if:
70
+
properties:
71
+
compatible:
72
+
contains:
73
+
enum:
74
+
- spacemit,k1-syscon-apbc
75
+
- spacemit,k1-syscon-apmu
76
+
- spacemit,k1-syscon-mpmu
77
+
then:
78
+
required:
79
+
- clocks
80
+
- clock-names
81
+
- "#clock-cells"
67
82
68
83
additionalProperties: false
69
84
+3
-1
drivers/clk/meson/Kconfig
+3
-1
drivers/clk/meson/Kconfig
···
5
5
config COMMON_CLK_MESON_REGMAP
6
6
tristate
7
7
select REGMAP
8
+
select MFD_SYSCON
8
9
9
10
config COMMON_CLK_MESON_DUALDIV
10
11
tristate
···
107
106
select COMMON_CLK_MESON_SCLK_DIV
108
107
select COMMON_CLK_MESON_CLKC_UTILS
109
108
select REGMAP_MMIO
110
-
select RESET_CONTROLLER
109
+
select AUXILIARY_BUS
110
+
imply RESET_MESON_AUX
111
111
help
112
112
Support for the audio clock controller on AmLogic A113D devices,
113
113
aka axg, Say Y if you want audio subsystem to work.
+31
-163
drivers/clk/meson/a1-peripherals.c
+31
-163
drivers/clk/meson/a1-peripherals.c
···
10
10
#include <linux/clk-provider.h>
11
11
#include <linux/mod_devicetable.h>
12
12
#include <linux/platform_device.h>
13
-
#include "a1-peripherals.h"
14
13
#include "clk-dualdiv.h"
15
14
#include "clk-regmap.h"
16
15
#include "meson-clkc-utils.h"
17
16
18
17
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
18
+
19
+
#define SYS_OSCIN_CTRL 0x0
20
+
#define RTC_BY_OSCIN_CTRL0 0x4
21
+
#define RTC_BY_OSCIN_CTRL1 0x8
22
+
#define RTC_CTRL 0xc
23
+
#define SYS_CLK_CTRL0 0x10
24
+
#define SYS_CLK_EN0 0x1c
25
+
#define SYS_CLK_EN1 0x20
26
+
#define AXI_CLK_EN 0x24
27
+
#define DSPA_CLK_EN 0x28
28
+
#define DSPB_CLK_EN 0x2c
29
+
#define DSPA_CLK_CTRL0 0x30
30
+
#define DSPB_CLK_CTRL0 0x34
31
+
#define CLK12_24_CTRL 0x38
32
+
#define GEN_CLK_CTRL 0x3c
33
+
#define SAR_ADC_CLK_CTRL 0xc0
34
+
#define PWM_CLK_AB_CTRL 0xc4
35
+
#define PWM_CLK_CD_CTRL 0xc8
36
+
#define PWM_CLK_EF_CTRL 0xcc
37
+
#define SPICC_CLK_CTRL 0xd0
38
+
#define TS_CLK_CTRL 0xd4
39
+
#define SPIFC_CLK_CTRL 0xd8
40
+
#define USB_BUSCLK_CTRL 0xdc
41
+
#define SD_EMMC_CLK_CTRL 0xe0
42
+
#define CECA_CLK_CTRL0 0xe4
43
+
#define CECA_CLK_CTRL1 0xe8
44
+
#define CECB_CLK_CTRL0 0xec
45
+
#define CECB_CLK_CTRL1 0xf0
46
+
#define PSRAM_CLK_CTRL 0xf4
47
+
#define DMC_CLK_CTRL 0xf8
19
48
20
49
static struct clk_regmap xtal_in = {
21
50
.data = &(struct clk_regmap_gate_data){
···
2055
2026
[CLKID_DMC_SEL2] = &dmc_sel2.hw,
2056
2027
};
2057
2028
2058
-
/* Convenience table to populate regmap in .probe */
2059
-
static struct clk_regmap *const a1_periphs_regmaps[] = {
2060
-
&xtal_in,
2061
-
&fixpll_in,
2062
-
&usb_phy_in,
2063
-
&usb_ctrl_in,
2064
-
&hifipll_in,
2065
-
&syspll_in,
2066
-
&dds_in,
2067
-
&sys,
2068
-
&clktree,
2069
-
&reset_ctrl,
2070
-
&analog_ctrl,
2071
-
&pwr_ctrl,
2072
-
&pad_ctrl,
2073
-
&sys_ctrl,
2074
-
&temp_sensor,
2075
-
&am2axi_dev,
2076
-
&spicc_b,
2077
-
&spicc_a,
2078
-
&msr,
2079
-
&audio,
2080
-
&jtag_ctrl,
2081
-
&saradc_en,
2082
-
&pwm_ef,
2083
-
&pwm_cd,
2084
-
&pwm_ab,
2085
-
&cec,
2086
-
&i2c_s,
2087
-
&ir_ctrl,
2088
-
&i2c_m_d,
2089
-
&i2c_m_c,
2090
-
&i2c_m_b,
2091
-
&i2c_m_a,
2092
-
&acodec,
2093
-
&otp,
2094
-
&sd_emmc_a,
2095
-
&usb_phy,
2096
-
&usb_ctrl,
2097
-
&sys_dspb,
2098
-
&sys_dspa,
2099
-
&dma,
2100
-
&irq_ctrl,
2101
-
&nic,
2102
-
&gic,
2103
-
&uart_c,
2104
-
&uart_b,
2105
-
&uart_a,
2106
-
&sys_psram,
2107
-
&rsa,
2108
-
&coresight,
2109
-
&am2axi_vad,
2110
-
&audio_vad,
2111
-
&axi_dmc,
2112
-
&axi_psram,
2113
-
&ramb,
2114
-
&rama,
2115
-
&axi_spifc,
2116
-
&axi_nic,
2117
-
&axi_dma,
2118
-
&cpu_ctrl,
2119
-
&rom,
2120
-
&prod_i2c,
2121
-
&dspa_sel,
2122
-
&dspb_sel,
2123
-
&dspa_en,
2124
-
&dspa_en_nic,
2125
-
&dspb_en,
2126
-
&dspb_en_nic,
2127
-
&rtc,
2128
-
&ceca_32k_out,
2129
-
&cecb_32k_out,
2130
-
&clk_24m,
2131
-
&clk_12m,
2132
-
&fclk_div2_divn,
2133
-
&gen,
2134
-
&saradc_sel,
2135
-
&saradc,
2136
-
&pwm_a,
2137
-
&pwm_b,
2138
-
&pwm_c,
2139
-
&pwm_d,
2140
-
&pwm_e,
2141
-
&pwm_f,
2142
-
&spicc,
2143
-
&ts,
2144
-
&spifc,
2145
-
&usb_bus,
2146
-
&sd_emmc,
2147
-
&psram,
2148
-
&dmc,
2149
-
&sys_a_sel,
2150
-
&sys_a_div,
2151
-
&sys_a,
2152
-
&sys_b_sel,
2153
-
&sys_b_div,
2154
-
&sys_b,
2155
-
&dspa_a_sel,
2156
-
&dspa_a_div,
2157
-
&dspa_a,
2158
-
&dspa_b_sel,
2159
-
&dspa_b_div,
2160
-
&dspa_b,
2161
-
&dspb_a_sel,
2162
-
&dspb_a_div,
2163
-
&dspb_a,
2164
-
&dspb_b_sel,
2165
-
&dspb_b_div,
2166
-
&dspb_b,
2167
-
&rtc_32k_in,
2168
-
&rtc_32k_div,
2169
-
&rtc_32k_xtal,
2170
-
&rtc_32k_sel,
2171
-
&cecb_32k_in,
2172
-
&cecb_32k_div,
2173
-
&cecb_32k_sel_pre,
2174
-
&cecb_32k_sel,
2175
-
&ceca_32k_in,
2176
-
&ceca_32k_div,
2177
-
&ceca_32k_sel_pre,
2178
-
&ceca_32k_sel,
2179
-
&fclk_div2_divn_pre,
2180
-
&gen_sel,
2181
-
&gen_div,
2182
-
&saradc_div,
2183
-
&pwm_a_sel,
2184
-
&pwm_a_div,
2185
-
&pwm_b_sel,
2186
-
&pwm_b_div,
2187
-
&pwm_c_sel,
2188
-
&pwm_c_div,
2189
-
&pwm_d_sel,
2190
-
&pwm_d_div,
2191
-
&pwm_e_sel,
2192
-
&pwm_e_div,
2193
-
&pwm_f_sel,
2194
-
&pwm_f_div,
2195
-
&spicc_sel,
2196
-
&spicc_div,
2197
-
&spicc_sel2,
2198
-
&ts_div,
2199
-
&spifc_sel,
2200
-
&spifc_div,
2201
-
&spifc_sel2,
2202
-
&usb_bus_sel,
2203
-
&usb_bus_div,
2204
-
&sd_emmc_sel,
2205
-
&sd_emmc_div,
2206
-
&sd_emmc_sel2,
2207
-
&psram_sel,
2208
-
&psram_div,
2209
-
&psram_sel2,
2210
-
&dmc_sel,
2211
-
&dmc_div,
2212
-
&dmc_sel2,
2213
-
};
2214
-
2215
2029
static const struct regmap_config a1_periphs_regmap_cfg = {
2216
2030
.reg_bits = 32,
2217
2031
.val_bits = 32,
···
2072
2200
struct device *dev = &pdev->dev;
2073
2201
void __iomem *base;
2074
2202
struct regmap *map;
2075
-
int clkid, i, err;
2203
+
int clkid, err;
2076
2204
2077
2205
base = devm_platform_ioremap_resource(pdev, 0);
2078
2206
if (IS_ERR(base))
···
2083
2211
if (IS_ERR(map))
2084
2212
return dev_err_probe(dev, PTR_ERR(map),
2085
2213
"can't init regmap mmio region\n");
2086
-
2087
-
/* Populate regmap for the regmap backed clocks */
2088
-
for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++)
2089
-
a1_periphs_regmaps[i]->map = map;
2090
2214
2091
2215
for (clkid = 0; clkid < a1_periphs_clks.num; clkid++) {
2092
2216
err = devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]);
-46
drivers/clk/meson/a1-peripherals.h
-46
drivers/clk/meson/a1-peripherals.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0+ */
2
-
/*
3
-
* Amlogic A1 Peripherals Clock Controller internals
4
-
*
5
-
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
6
-
* Author: Jian Hu <jian.hu@amlogic.com>
7
-
*
8
-
* Copyright (c) 2023, SberDevices. All Rights Reserved.
9
-
* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
10
-
*/
11
-
12
-
#ifndef __A1_PERIPHERALS_H
13
-
#define __A1_PERIPHERALS_H
14
-
15
-
/* peripherals clock controller register offset */
16
-
#define SYS_OSCIN_CTRL 0x0
17
-
#define RTC_BY_OSCIN_CTRL0 0x4
18
-
#define RTC_BY_OSCIN_CTRL1 0x8
19
-
#define RTC_CTRL 0xc
20
-
#define SYS_CLK_CTRL0 0x10
21
-
#define SYS_CLK_EN0 0x1c
22
-
#define SYS_CLK_EN1 0x20
23
-
#define AXI_CLK_EN 0x24
24
-
#define DSPA_CLK_EN 0x28
25
-
#define DSPB_CLK_EN 0x2c
26
-
#define DSPA_CLK_CTRL0 0x30
27
-
#define DSPB_CLK_CTRL0 0x34
28
-
#define CLK12_24_CTRL 0x38
29
-
#define GEN_CLK_CTRL 0x3c
30
-
#define SAR_ADC_CLK_CTRL 0xc0
31
-
#define PWM_CLK_AB_CTRL 0xc4
32
-
#define PWM_CLK_CD_CTRL 0xc8
33
-
#define PWM_CLK_EF_CTRL 0xcc
34
-
#define SPICC_CLK_CTRL 0xd0
35
-
#define TS_CLK_CTRL 0xd4
36
-
#define SPIFC_CLK_CTRL 0xd8
37
-
#define USB_BUSCLK_CTRL 0xdc
38
-
#define SD_EMMC_CLK_CTRL 0xe0
39
-
#define CECA_CLK_CTRL0 0xe4
40
-
#define CECA_CLK_CTRL1 0xe8
41
-
#define CECB_CLK_CTRL0 0xec
42
-
#define CECB_CLK_CTRL1 0xf0
43
-
#define PSRAM_CLK_CTRL 0xf4
44
-
#define DMC_CLK_CTRL 0xf8
45
-
46
-
#endif /* __A1_PERIPHERALS_H */
+12
-16
drivers/clk/meson/a1-pll.c
+12
-16
drivers/clk/meson/a1-pll.c
···
10
10
#include <linux/clk-provider.h>
11
11
#include <linux/mod_devicetable.h>
12
12
#include <linux/platform_device.h>
13
-
#include "a1-pll.h"
13
+
#include "clk-pll.h"
14
14
#include "clk-regmap.h"
15
15
#include "meson-clkc-utils.h"
16
+
17
+
#define ANACTRL_FIXPLL_CTRL0 0x0
18
+
#define ANACTRL_FIXPLL_CTRL1 0x4
19
+
#define ANACTRL_FIXPLL_STS 0x14
20
+
#define ANACTRL_HIFIPLL_CTRL0 0xc0
21
+
#define ANACTRL_HIFIPLL_CTRL1 0xc4
22
+
#define ANACTRL_HIFIPLL_CTRL2 0xc8
23
+
#define ANACTRL_HIFIPLL_CTRL3 0xcc
24
+
#define ANACTRL_HIFIPLL_CTRL4 0xd0
25
+
#define ANACTRL_HIFIPLL_STS 0xd4
16
26
17
27
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
18
28
···
295
285
[CLKID_HIFI_PLL] = &hifi_pll.hw,
296
286
};
297
287
298
-
static struct clk_regmap *const a1_pll_regmaps[] = {
299
-
&fixed_pll_dco,
300
-
&fixed_pll,
301
-
&fclk_div2,
302
-
&fclk_div3,
303
-
&fclk_div5,
304
-
&fclk_div7,
305
-
&hifi_pll,
306
-
};
307
-
308
288
static const struct regmap_config a1_pll_regmap_cfg = {
309
289
.reg_bits = 32,
310
290
.val_bits = 32,
···
312
312
struct device *dev = &pdev->dev;
313
313
void __iomem *base;
314
314
struct regmap *map;
315
-
int clkid, i, err;
315
+
int clkid, err;
316
316
317
317
base = devm_platform_ioremap_resource(pdev, 0);
318
318
if (IS_ERR(base))
···
323
323
if (IS_ERR(map))
324
324
return dev_err_probe(dev, PTR_ERR(map),
325
325
"can't init regmap mmio region\n");
326
-
327
-
/* Populate regmap for the regmap backed clocks */
328
-
for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++)
329
-
a1_pll_regmaps[i]->map = map;
330
326
331
327
/* Register clocks */
332
328
for (clkid = 0; clkid < a1_pll_clks.num; clkid++) {
-28
drivers/clk/meson/a1-pll.h
-28
drivers/clk/meson/a1-pll.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0+ */
2
-
/*
3
-
* Amlogic A1 PLL Clock Controller internals
4
-
*
5
-
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
6
-
* Author: Jian Hu <jian.hu@amlogic.com>
7
-
*
8
-
* Copyright (c) 2023, SberDevices. All Rights Reserved.
9
-
* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
10
-
*/
11
-
12
-
#ifndef __A1_PLL_H
13
-
#define __A1_PLL_H
14
-
15
-
#include "clk-pll.h"
16
-
17
-
/* PLL register offset */
18
-
#define ANACTRL_FIXPLL_CTRL0 0x0
19
-
#define ANACTRL_FIXPLL_CTRL1 0x4
20
-
#define ANACTRL_FIXPLL_STS 0x14
21
-
#define ANACTRL_HIFIPLL_CTRL0 0xc0
22
-
#define ANACTRL_HIFIPLL_CTRL1 0xc4
23
-
#define ANACTRL_HIFIPLL_CTRL2 0xc8
24
-
#define ANACTRL_HIFIPLL_CTRL3 0xcc
25
-
#define ANACTRL_HIFIPLL_CTRL4 0xd0
26
-
#define ANACTRL_HIFIPLL_STS 0xd4
27
-
28
-
#endif /* __A1_PLL_H */
-22
drivers/clk/meson/axg-aoclk.c
-22
drivers/clk/meson/axg-aoclk.c
···
270
270
[RESET_AO_IR_BLASTER] = 23,
271
271
};
272
272
273
-
static struct clk_regmap *axg_aoclk_regmap[] = {
274
-
&axg_aoclk_remote,
275
-
&axg_aoclk_i2c_master,
276
-
&axg_aoclk_i2c_slave,
277
-
&axg_aoclk_uart1,
278
-
&axg_aoclk_uart2,
279
-
&axg_aoclk_ir_blaster,
280
-
&axg_aoclk_saradc,
281
-
&axg_aoclk_cts_oscin,
282
-
&axg_aoclk_32k_pre,
283
-
&axg_aoclk_32k_div,
284
-
&axg_aoclk_32k_sel,
285
-
&axg_aoclk_32k,
286
-
&axg_aoclk_cts_rtc_oscin,
287
-
&axg_aoclk_clk81,
288
-
&axg_aoclk_saradc_mux,
289
-
&axg_aoclk_saradc_div,
290
-
&axg_aoclk_saradc_gate,
291
-
};
292
-
293
273
static struct clk_hw *axg_aoclk_hw_clks[] = {
294
274
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
295
275
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
···
294
314
.reset_reg = AO_RTI_GEN_CNTL_REG0,
295
315
.num_reset = ARRAY_SIZE(axg_aoclk_reset),
296
316
.reset = axg_aoclk_reset,
297
-
.num_clks = ARRAY_SIZE(axg_aoclk_regmap),
298
-
.clks = axg_aoclk_regmap,
299
317
.hw_clks = {
300
318
.hws = axg_aoclk_hw_clks,
301
319
.num = ARRAY_SIZE(axg_aoclk_hw_clks),
+68
-535
drivers/clk/meson/axg-audio.c
+68
-535
drivers/clk/meson/axg-audio.c
···
4
4
* Author: Jerome Brunet <jbrunet@baylibre.com>
5
5
*/
6
6
7
+
#include <linux/auxiliary_bus.h>
7
8
#include <linux/clk.h>
8
9
#include <linux/clk-provider.h>
9
10
#include <linux/init.h>
···
13
12
#include <linux/platform_device.h>
14
13
#include <linux/regmap.h>
15
14
#include <linux/reset.h>
16
-
#include <linux/reset-controller.h>
17
15
#include <linux/slab.h>
18
16
19
17
#include "meson-clkc-utils.h"
20
-
#include "axg-audio.h"
21
18
#include "clk-regmap.h"
22
19
#include "clk-phase.h"
23
20
#include "sclk-div.h"
24
21
25
22
#include <dt-bindings/clock/axg-audio-clkc.h>
23
+
24
+
/* Audio clock register offsets */
25
+
#define AUDIO_CLK_GATE_EN 0x000
26
+
#define AUDIO_MCLK_A_CTRL 0x004
27
+
#define AUDIO_MCLK_B_CTRL 0x008
28
+
#define AUDIO_MCLK_C_CTRL 0x00C
29
+
#define AUDIO_MCLK_D_CTRL 0x010
30
+
#define AUDIO_MCLK_E_CTRL 0x014
31
+
#define AUDIO_MCLK_F_CTRL 0x018
32
+
#define AUDIO_MST_PAD_CTRL0 0x01c
33
+
#define AUDIO_MST_PAD_CTRL1 0x020
34
+
#define AUDIO_SW_RESET 0x024
35
+
#define AUDIO_MST_A_SCLK_CTRL0 0x040
36
+
#define AUDIO_MST_A_SCLK_CTRL1 0x044
37
+
#define AUDIO_MST_B_SCLK_CTRL0 0x048
38
+
#define AUDIO_MST_B_SCLK_CTRL1 0x04C
39
+
#define AUDIO_MST_C_SCLK_CTRL0 0x050
40
+
#define AUDIO_MST_C_SCLK_CTRL1 0x054
41
+
#define AUDIO_MST_D_SCLK_CTRL0 0x058
42
+
#define AUDIO_MST_D_SCLK_CTRL1 0x05C
43
+
#define AUDIO_MST_E_SCLK_CTRL0 0x060
44
+
#define AUDIO_MST_E_SCLK_CTRL1 0x064
45
+
#define AUDIO_MST_F_SCLK_CTRL0 0x068
46
+
#define AUDIO_MST_F_SCLK_CTRL1 0x06C
47
+
#define AUDIO_CLK_TDMIN_A_CTRL 0x080
48
+
#define AUDIO_CLK_TDMIN_B_CTRL 0x084
49
+
#define AUDIO_CLK_TDMIN_C_CTRL 0x088
50
+
#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C
51
+
#define AUDIO_CLK_TDMOUT_A_CTRL 0x090
52
+
#define AUDIO_CLK_TDMOUT_B_CTRL 0x094
53
+
#define AUDIO_CLK_TDMOUT_C_CTRL 0x098
54
+
#define AUDIO_CLK_SPDIFIN_CTRL 0x09C
55
+
#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0
56
+
#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4
57
+
#define AUDIO_CLK_LOCKER_CTRL 0x0A8
58
+
#define AUDIO_CLK_PDMIN_CTRL0 0x0AC
59
+
#define AUDIO_CLK_PDMIN_CTRL1 0x0B0
60
+
#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
61
+
62
+
/* SM1 introduce new register and some shifts :( */
63
+
#define AUDIO_CLK_GATE_EN1 0x004
64
+
#define AUDIO_SM1_MCLK_A_CTRL 0x008
65
+
#define AUDIO_SM1_MCLK_B_CTRL 0x00C
66
+
#define AUDIO_SM1_MCLK_C_CTRL 0x010
67
+
#define AUDIO_SM1_MCLK_D_CTRL 0x014
68
+
#define AUDIO_SM1_MCLK_E_CTRL 0x018
69
+
#define AUDIO_SM1_MCLK_F_CTRL 0x01C
70
+
#define AUDIO_SM1_MST_PAD_CTRL0 0x020
71
+
#define AUDIO_SM1_MST_PAD_CTRL1 0x024
72
+
#define AUDIO_SM1_SW_RESET0 0x028
73
+
#define AUDIO_SM1_SW_RESET1 0x02C
74
+
#define AUDIO_CLK81_CTRL 0x030
75
+
#define AUDIO_CLK81_EN 0x034
76
+
#define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0
77
+
#define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4
26
78
27
79
#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
28
80
.data = &(struct clk_regmap_gate_data){ \
···
1311
1257
[AUD_CLKID_EARCRX_DMAC] = &sm1_earcrx_dmac_clk.hw,
1312
1258
};
1313
1259
1314
-
1315
-
/* Convenience table to populate regmap in .probe(). */
1316
-
static struct clk_regmap *const axg_clk_regmaps[] = {
1317
-
&ddr_arb,
1318
-
&pdm,
1319
-
&tdmin_a,
1320
-
&tdmin_b,
1321
-
&tdmin_c,
1322
-
&tdmin_lb,
1323
-
&tdmout_a,
1324
-
&tdmout_b,
1325
-
&tdmout_c,
1326
-
&frddr_a,
1327
-
&frddr_b,
1328
-
&frddr_c,
1329
-
&toddr_a,
1330
-
&toddr_b,
1331
-
&toddr_c,
1332
-
&loopback,
1333
-
&spdifin,
1334
-
&spdifout,
1335
-
&resample,
1336
-
&power_detect,
1337
-
&mst_a_mclk_sel,
1338
-
&mst_b_mclk_sel,
1339
-
&mst_c_mclk_sel,
1340
-
&mst_d_mclk_sel,
1341
-
&mst_e_mclk_sel,
1342
-
&mst_f_mclk_sel,
1343
-
&mst_a_mclk_div,
1344
-
&mst_b_mclk_div,
1345
-
&mst_c_mclk_div,
1346
-
&mst_d_mclk_div,
1347
-
&mst_e_mclk_div,
1348
-
&mst_f_mclk_div,
1349
-
&mst_a_mclk,
1350
-
&mst_b_mclk,
1351
-
&mst_c_mclk,
1352
-
&mst_d_mclk,
1353
-
&mst_e_mclk,
1354
-
&mst_f_mclk,
1355
-
&spdifout_clk_sel,
1356
-
&spdifout_clk_div,
1357
-
&spdifout_clk,
1358
-
&spdifin_clk_sel,
1359
-
&spdifin_clk_div,
1360
-
&spdifin_clk,
1361
-
&pdm_dclk_sel,
1362
-
&pdm_dclk_div,
1363
-
&pdm_dclk,
1364
-
&pdm_sysclk_sel,
1365
-
&pdm_sysclk_div,
1366
-
&pdm_sysclk,
1367
-
&mst_a_sclk_pre_en,
1368
-
&mst_b_sclk_pre_en,
1369
-
&mst_c_sclk_pre_en,
1370
-
&mst_d_sclk_pre_en,
1371
-
&mst_e_sclk_pre_en,
1372
-
&mst_f_sclk_pre_en,
1373
-
&mst_a_sclk_div,
1374
-
&mst_b_sclk_div,
1375
-
&mst_c_sclk_div,
1376
-
&mst_d_sclk_div,
1377
-
&mst_e_sclk_div,
1378
-
&mst_f_sclk_div,
1379
-
&mst_a_sclk_post_en,
1380
-
&mst_b_sclk_post_en,
1381
-
&mst_c_sclk_post_en,
1382
-
&mst_d_sclk_post_en,
1383
-
&mst_e_sclk_post_en,
1384
-
&mst_f_sclk_post_en,
1385
-
&mst_a_sclk,
1386
-
&mst_b_sclk,
1387
-
&mst_c_sclk,
1388
-
&mst_d_sclk,
1389
-
&mst_e_sclk,
1390
-
&mst_f_sclk,
1391
-
&mst_a_lrclk_div,
1392
-
&mst_b_lrclk_div,
1393
-
&mst_c_lrclk_div,
1394
-
&mst_d_lrclk_div,
1395
-
&mst_e_lrclk_div,
1396
-
&mst_f_lrclk_div,
1397
-
&mst_a_lrclk,
1398
-
&mst_b_lrclk,
1399
-
&mst_c_lrclk,
1400
-
&mst_d_lrclk,
1401
-
&mst_e_lrclk,
1402
-
&mst_f_lrclk,
1403
-
&tdmin_a_sclk_sel,
1404
-
&tdmin_b_sclk_sel,
1405
-
&tdmin_c_sclk_sel,
1406
-
&tdmin_lb_sclk_sel,
1407
-
&tdmout_a_sclk_sel,
1408
-
&tdmout_b_sclk_sel,
1409
-
&tdmout_c_sclk_sel,
1410
-
&tdmin_a_sclk_pre_en,
1411
-
&tdmin_b_sclk_pre_en,
1412
-
&tdmin_c_sclk_pre_en,
1413
-
&tdmin_lb_sclk_pre_en,
1414
-
&tdmout_a_sclk_pre_en,
1415
-
&tdmout_b_sclk_pre_en,
1416
-
&tdmout_c_sclk_pre_en,
1417
-
&tdmin_a_sclk_post_en,
1418
-
&tdmin_b_sclk_post_en,
1419
-
&tdmin_c_sclk_post_en,
1420
-
&tdmin_lb_sclk_post_en,
1421
-
&tdmout_a_sclk_post_en,
1422
-
&tdmout_b_sclk_post_en,
1423
-
&tdmout_c_sclk_post_en,
1424
-
&tdmin_a_sclk,
1425
-
&tdmin_b_sclk,
1426
-
&tdmin_c_sclk,
1427
-
&tdmin_lb_sclk,
1428
-
&axg_tdmout_a_sclk,
1429
-
&axg_tdmout_b_sclk,
1430
-
&axg_tdmout_c_sclk,
1431
-
&tdmin_a_lrclk,
1432
-
&tdmin_b_lrclk,
1433
-
&tdmin_c_lrclk,
1434
-
&tdmin_lb_lrclk,
1435
-
&tdmout_a_lrclk,
1436
-
&tdmout_b_lrclk,
1437
-
&tdmout_c_lrclk,
1438
-
};
1439
-
1440
-
static struct clk_regmap *const g12a_clk_regmaps[] = {
1441
-
&ddr_arb,
1442
-
&pdm,
1443
-
&tdmin_a,
1444
-
&tdmin_b,
1445
-
&tdmin_c,
1446
-
&tdmin_lb,
1447
-
&tdmout_a,
1448
-
&tdmout_b,
1449
-
&tdmout_c,
1450
-
&frddr_a,
1451
-
&frddr_b,
1452
-
&frddr_c,
1453
-
&toddr_a,
1454
-
&toddr_b,
1455
-
&toddr_c,
1456
-
&loopback,
1457
-
&spdifin,
1458
-
&spdifout,
1459
-
&resample,
1460
-
&power_detect,
1461
-
&spdifout_b,
1462
-
&mst_a_mclk_sel,
1463
-
&mst_b_mclk_sel,
1464
-
&mst_c_mclk_sel,
1465
-
&mst_d_mclk_sel,
1466
-
&mst_e_mclk_sel,
1467
-
&mst_f_mclk_sel,
1468
-
&mst_a_mclk_div,
1469
-
&mst_b_mclk_div,
1470
-
&mst_c_mclk_div,
1471
-
&mst_d_mclk_div,
1472
-
&mst_e_mclk_div,
1473
-
&mst_f_mclk_div,
1474
-
&mst_a_mclk,
1475
-
&mst_b_mclk,
1476
-
&mst_c_mclk,
1477
-
&mst_d_mclk,
1478
-
&mst_e_mclk,
1479
-
&mst_f_mclk,
1480
-
&spdifout_clk_sel,
1481
-
&spdifout_clk_div,
1482
-
&spdifout_clk,
1483
-
&spdifin_clk_sel,
1484
-
&spdifin_clk_div,
1485
-
&spdifin_clk,
1486
-
&pdm_dclk_sel,
1487
-
&pdm_dclk_div,
1488
-
&pdm_dclk,
1489
-
&pdm_sysclk_sel,
1490
-
&pdm_sysclk_div,
1491
-
&pdm_sysclk,
1492
-
&mst_a_sclk_pre_en,
1493
-
&mst_b_sclk_pre_en,
1494
-
&mst_c_sclk_pre_en,
1495
-
&mst_d_sclk_pre_en,
1496
-
&mst_e_sclk_pre_en,
1497
-
&mst_f_sclk_pre_en,
1498
-
&mst_a_sclk_div,
1499
-
&mst_b_sclk_div,
1500
-
&mst_c_sclk_div,
1501
-
&mst_d_sclk_div,
1502
-
&mst_e_sclk_div,
1503
-
&mst_f_sclk_div,
1504
-
&mst_a_sclk_post_en,
1505
-
&mst_b_sclk_post_en,
1506
-
&mst_c_sclk_post_en,
1507
-
&mst_d_sclk_post_en,
1508
-
&mst_e_sclk_post_en,
1509
-
&mst_f_sclk_post_en,
1510
-
&mst_a_sclk,
1511
-
&mst_b_sclk,
1512
-
&mst_c_sclk,
1513
-
&mst_d_sclk,
1514
-
&mst_e_sclk,
1515
-
&mst_f_sclk,
1516
-
&mst_a_lrclk_div,
1517
-
&mst_b_lrclk_div,
1518
-
&mst_c_lrclk_div,
1519
-
&mst_d_lrclk_div,
1520
-
&mst_e_lrclk_div,
1521
-
&mst_f_lrclk_div,
1522
-
&mst_a_lrclk,
1523
-
&mst_b_lrclk,
1524
-
&mst_c_lrclk,
1525
-
&mst_d_lrclk,
1526
-
&mst_e_lrclk,
1527
-
&mst_f_lrclk,
1528
-
&tdmin_a_sclk_sel,
1529
-
&tdmin_b_sclk_sel,
1530
-
&tdmin_c_sclk_sel,
1531
-
&tdmin_lb_sclk_sel,
1532
-
&tdmout_a_sclk_sel,
1533
-
&tdmout_b_sclk_sel,
1534
-
&tdmout_c_sclk_sel,
1535
-
&tdmin_a_sclk_pre_en,
1536
-
&tdmin_b_sclk_pre_en,
1537
-
&tdmin_c_sclk_pre_en,
1538
-
&tdmin_lb_sclk_pre_en,
1539
-
&tdmout_a_sclk_pre_en,
1540
-
&tdmout_b_sclk_pre_en,
1541
-
&tdmout_c_sclk_pre_en,
1542
-
&tdmin_a_sclk_post_en,
1543
-
&tdmin_b_sclk_post_en,
1544
-
&tdmin_c_sclk_post_en,
1545
-
&tdmin_lb_sclk_post_en,
1546
-
&tdmout_a_sclk_post_en,
1547
-
&tdmout_b_sclk_post_en,
1548
-
&tdmout_c_sclk_post_en,
1549
-
&tdmin_a_sclk,
1550
-
&tdmin_b_sclk,
1551
-
&tdmin_c_sclk,
1552
-
&tdmin_lb_sclk,
1553
-
&g12a_tdmout_a_sclk,
1554
-
&g12a_tdmout_b_sclk,
1555
-
&g12a_tdmout_c_sclk,
1556
-
&tdmin_a_lrclk,
1557
-
&tdmin_b_lrclk,
1558
-
&tdmin_c_lrclk,
1559
-
&tdmin_lb_lrclk,
1560
-
&tdmout_a_lrclk,
1561
-
&tdmout_b_lrclk,
1562
-
&tdmout_c_lrclk,
1563
-
&spdifout_b_clk_sel,
1564
-
&spdifout_b_clk_div,
1565
-
&spdifout_b_clk,
1566
-
&g12a_tdm_mclk_pad_0,
1567
-
&g12a_tdm_mclk_pad_1,
1568
-
&g12a_tdm_lrclk_pad_0,
1569
-
&g12a_tdm_lrclk_pad_1,
1570
-
&g12a_tdm_lrclk_pad_2,
1571
-
&g12a_tdm_sclk_pad_0,
1572
-
&g12a_tdm_sclk_pad_1,
1573
-
&g12a_tdm_sclk_pad_2,
1574
-
&toram,
1575
-
&eqdrc,
1576
-
};
1577
-
1578
-
static struct clk_regmap *const sm1_clk_regmaps[] = {
1579
-
&ddr_arb,
1580
-
&pdm,
1581
-
&tdmin_a,
1582
-
&tdmin_b,
1583
-
&tdmin_c,
1584
-
&tdmin_lb,
1585
-
&tdmout_a,
1586
-
&tdmout_b,
1587
-
&tdmout_c,
1588
-
&frddr_a,
1589
-
&frddr_b,
1590
-
&frddr_c,
1591
-
&toddr_a,
1592
-
&toddr_b,
1593
-
&toddr_c,
1594
-
&loopback,
1595
-
&spdifin,
1596
-
&spdifout,
1597
-
&resample,
1598
-
&spdifout_b,
1599
-
&sm1_mst_a_mclk_sel,
1600
-
&sm1_mst_b_mclk_sel,
1601
-
&sm1_mst_c_mclk_sel,
1602
-
&sm1_mst_d_mclk_sel,
1603
-
&sm1_mst_e_mclk_sel,
1604
-
&sm1_mst_f_mclk_sel,
1605
-
&sm1_mst_a_mclk_div,
1606
-
&sm1_mst_b_mclk_div,
1607
-
&sm1_mst_c_mclk_div,
1608
-
&sm1_mst_d_mclk_div,
1609
-
&sm1_mst_e_mclk_div,
1610
-
&sm1_mst_f_mclk_div,
1611
-
&sm1_mst_a_mclk,
1612
-
&sm1_mst_b_mclk,
1613
-
&sm1_mst_c_mclk,
1614
-
&sm1_mst_d_mclk,
1615
-
&sm1_mst_e_mclk,
1616
-
&sm1_mst_f_mclk,
1617
-
&spdifout_clk_sel,
1618
-
&spdifout_clk_div,
1619
-
&spdifout_clk,
1620
-
&spdifin_clk_sel,
1621
-
&spdifin_clk_div,
1622
-
&spdifin_clk,
1623
-
&pdm_dclk_sel,
1624
-
&pdm_dclk_div,
1625
-
&pdm_dclk,
1626
-
&pdm_sysclk_sel,
1627
-
&pdm_sysclk_div,
1628
-
&pdm_sysclk,
1629
-
&mst_a_sclk_pre_en,
1630
-
&mst_b_sclk_pre_en,
1631
-
&mst_c_sclk_pre_en,
1632
-
&mst_d_sclk_pre_en,
1633
-
&mst_e_sclk_pre_en,
1634
-
&mst_f_sclk_pre_en,
1635
-
&mst_a_sclk_div,
1636
-
&mst_b_sclk_div,
1637
-
&mst_c_sclk_div,
1638
-
&mst_d_sclk_div,
1639
-
&mst_e_sclk_div,
1640
-
&mst_f_sclk_div,
1641
-
&mst_a_sclk_post_en,
1642
-
&mst_b_sclk_post_en,
1643
-
&mst_c_sclk_post_en,
1644
-
&mst_d_sclk_post_en,
1645
-
&mst_e_sclk_post_en,
1646
-
&mst_f_sclk_post_en,
1647
-
&mst_a_sclk,
1648
-
&mst_b_sclk,
1649
-
&mst_c_sclk,
1650
-
&mst_d_sclk,
1651
-
&mst_e_sclk,
1652
-
&mst_f_sclk,
1653
-
&mst_a_lrclk_div,
1654
-
&mst_b_lrclk_div,
1655
-
&mst_c_lrclk_div,
1656
-
&mst_d_lrclk_div,
1657
-
&mst_e_lrclk_div,
1658
-
&mst_f_lrclk_div,
1659
-
&mst_a_lrclk,
1660
-
&mst_b_lrclk,
1661
-
&mst_c_lrclk,
1662
-
&mst_d_lrclk,
1663
-
&mst_e_lrclk,
1664
-
&mst_f_lrclk,
1665
-
&tdmin_a_sclk_sel,
1666
-
&tdmin_b_sclk_sel,
1667
-
&tdmin_c_sclk_sel,
1668
-
&tdmin_lb_sclk_sel,
1669
-
&tdmout_a_sclk_sel,
1670
-
&tdmout_b_sclk_sel,
1671
-
&tdmout_c_sclk_sel,
1672
-
&tdmin_a_sclk_pre_en,
1673
-
&tdmin_b_sclk_pre_en,
1674
-
&tdmin_c_sclk_pre_en,
1675
-
&tdmin_lb_sclk_pre_en,
1676
-
&tdmout_a_sclk_pre_en,
1677
-
&tdmout_b_sclk_pre_en,
1678
-
&tdmout_c_sclk_pre_en,
1679
-
&tdmin_a_sclk_post_en,
1680
-
&tdmin_b_sclk_post_en,
1681
-
&tdmin_c_sclk_post_en,
1682
-
&tdmin_lb_sclk_post_en,
1683
-
&tdmout_a_sclk_post_en,
1684
-
&tdmout_b_sclk_post_en,
1685
-
&tdmout_c_sclk_post_en,
1686
-
&tdmin_a_sclk,
1687
-
&tdmin_b_sclk,
1688
-
&tdmin_c_sclk,
1689
-
&tdmin_lb_sclk,
1690
-
&g12a_tdmout_a_sclk,
1691
-
&g12a_tdmout_b_sclk,
1692
-
&g12a_tdmout_c_sclk,
1693
-
&tdmin_a_lrclk,
1694
-
&tdmin_b_lrclk,
1695
-
&tdmin_c_lrclk,
1696
-
&tdmin_lb_lrclk,
1697
-
&tdmout_a_lrclk,
1698
-
&tdmout_b_lrclk,
1699
-
&tdmout_c_lrclk,
1700
-
&spdifout_b_clk_sel,
1701
-
&spdifout_b_clk_div,
1702
-
&spdifout_b_clk,
1703
-
&sm1_tdm_mclk_pad_0,
1704
-
&sm1_tdm_mclk_pad_1,
1705
-
&sm1_tdm_lrclk_pad_0,
1706
-
&sm1_tdm_lrclk_pad_1,
1707
-
&sm1_tdm_lrclk_pad_2,
1708
-
&sm1_tdm_sclk_pad_0,
1709
-
&sm1_tdm_sclk_pad_1,
1710
-
&sm1_tdm_sclk_pad_2,
1711
-
&sm1_aud_top,
1712
-
&toram,
1713
-
&eqdrc,
1714
-
&resample_b,
1715
-
&tovad,
1716
-
&locker,
1717
-
&spdifin_lb,
1718
-
&frddr_d,
1719
-
&toddr_d,
1720
-
&loopback_b,
1721
-
&sm1_clk81_en,
1722
-
&sm1_sysclk_a_div,
1723
-
&sm1_sysclk_a_en,
1724
-
&sm1_sysclk_b_div,
1725
-
&sm1_sysclk_b_en,
1726
-
&earcrx,
1727
-
&sm1_earcrx_cmdc_clk_sel,
1728
-
&sm1_earcrx_cmdc_clk_div,
1729
-
&sm1_earcrx_cmdc_clk,
1730
-
&sm1_earcrx_dmac_clk_sel,
1731
-
&sm1_earcrx_dmac_clk_div,
1732
-
&sm1_earcrx_dmac_clk,
1733
-
};
1734
-
1735
-
struct axg_audio_reset_data {
1736
-
struct reset_controller_dev rstc;
1737
-
struct regmap *map;
1738
-
unsigned int offset;
1739
-
};
1740
-
1741
-
static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
1742
-
unsigned long id,
1743
-
unsigned int *reg,
1744
-
unsigned int *bit)
1745
-
{
1746
-
unsigned int stride = regmap_get_reg_stride(rst->map);
1747
-
1748
-
*reg = (id / (stride * BITS_PER_BYTE)) * stride;
1749
-
*reg += rst->offset;
1750
-
*bit = id % (stride * BITS_PER_BYTE);
1751
-
}
1752
-
1753
-
static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
1754
-
unsigned long id, bool assert)
1755
-
{
1756
-
struct axg_audio_reset_data *rst =
1757
-
container_of(rcdev, struct axg_audio_reset_data, rstc);
1758
-
unsigned int offset, bit;
1759
-
1760
-
axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1761
-
1762
-
regmap_update_bits(rst->map, offset, BIT(bit),
1763
-
assert ? BIT(bit) : 0);
1764
-
1765
-
return 0;
1766
-
}
1767
-
1768
-
static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
1769
-
unsigned long id)
1770
-
{
1771
-
struct axg_audio_reset_data *rst =
1772
-
container_of(rcdev, struct axg_audio_reset_data, rstc);
1773
-
unsigned int val, offset, bit;
1774
-
1775
-
axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1776
-
1777
-
regmap_read(rst->map, offset, &val);
1778
-
1779
-
return !!(val & BIT(bit));
1780
-
}
1781
-
1782
-
static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
1783
-
unsigned long id)
1784
-
{
1785
-
return axg_audio_reset_update(rcdev, id, true);
1786
-
}
1787
-
1788
-
static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
1789
-
unsigned long id)
1790
-
{
1791
-
return axg_audio_reset_update(rcdev, id, false);
1792
-
}
1793
-
1794
-
static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
1795
-
unsigned long id)
1796
-
{
1797
-
int ret;
1798
-
1799
-
ret = axg_audio_reset_assert(rcdev, id);
1800
-
if (ret)
1801
-
return ret;
1802
-
1803
-
return axg_audio_reset_deassert(rcdev, id);
1804
-
}
1805
-
1806
-
static const struct reset_control_ops axg_audio_rstc_ops = {
1807
-
.assert = axg_audio_reset_assert,
1808
-
.deassert = axg_audio_reset_deassert,
1809
-
.reset = axg_audio_reset_toggle,
1810
-
.status = axg_audio_reset_status,
1811
-
};
1812
-
1813
1260
static struct regmap_config axg_audio_regmap_cfg = {
1814
1261
.reg_bits = 32,
1815
1262
.val_bits = 32,
···
1318
1763
};
1319
1764
1320
1765
struct audioclk_data {
1321
-
struct clk_regmap *const *regmap_clks;
1322
-
unsigned int regmap_clk_num;
1323
1766
struct meson_clk_hw_data hw_clks;
1324
-
unsigned int reset_offset;
1325
-
unsigned int reset_num;
1767
+
const char *rst_drvname;
1326
1768
unsigned int max_register;
1327
1769
};
1328
1770
···
1327
1775
{
1328
1776
struct device *dev = &pdev->dev;
1329
1777
const struct audioclk_data *data;
1330
-
struct axg_audio_reset_data *rst;
1778
+
struct auxiliary_device *auxdev;
1331
1779
struct regmap *map;
1332
1780
void __iomem *regs;
1333
1781
struct clk_hw *hw;
···
1360
1808
return ret;
1361
1809
}
1362
1810
1363
-
/* Populate regmap for the regmap backed clocks */
1364
-
for (i = 0; i < data->regmap_clk_num; i++)
1365
-
data->regmap_clks[i]->map = map;
1366
-
1367
1811
/* Take care to skip the registered input clocks */
1368
1812
for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
1369
1813
const char *name;
···
1382
1834
if (ret)
1383
1835
return ret;
1384
1836
1385
-
/* Stop here if there is no reset */
1386
-
if (!data->reset_num)
1387
-
return 0;
1837
+
/* Register auxiliary reset driver when applicable */
1838
+
if (data->rst_drvname) {
1839
+
auxdev = __devm_auxiliary_device_create(dev, dev->driver->name,
1840
+
data->rst_drvname, NULL, 0);
1841
+
if (!auxdev)
1842
+
return -ENODEV;
1843
+
}
1388
1844
1389
-
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
1390
-
if (!rst)
1391
-
return -ENOMEM;
1392
-
1393
-
rst->map = map;
1394
-
rst->offset = data->reset_offset;
1395
-
rst->rstc.nr_resets = data->reset_num;
1396
-
rst->rstc.ops = &axg_audio_rstc_ops;
1397
-
rst->rstc.of_node = dev->of_node;
1398
-
rst->rstc.owner = THIS_MODULE;
1399
-
1400
-
return devm_reset_controller_register(dev, &rst->rstc);
1845
+
return 0;
1401
1846
}
1402
1847
1403
1848
static const struct audioclk_data axg_audioclk_data = {
1404
-
.regmap_clks = axg_clk_regmaps,
1405
-
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1406
1849
.hw_clks = {
1407
1850
.hws = axg_audio_hw_clks,
1408
1851
.num = ARRAY_SIZE(axg_audio_hw_clks),
···
1402
1863
};
1403
1864
1404
1865
static const struct audioclk_data g12a_audioclk_data = {
1405
-
.regmap_clks = g12a_clk_regmaps,
1406
-
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
1407
1866
.hw_clks = {
1408
1867
.hws = g12a_audio_hw_clks,
1409
1868
.num = ARRAY_SIZE(g12a_audio_hw_clks),
1410
1869
},
1411
-
.reset_offset = AUDIO_SW_RESET,
1412
-
.reset_num = 26,
1870
+
.rst_drvname = "rst-g12a",
1413
1871
.max_register = AUDIO_CLK_SPDIFOUT_B_CTRL,
1414
1872
};
1415
1873
1416
1874
static const struct audioclk_data sm1_audioclk_data = {
1417
-
.regmap_clks = sm1_clk_regmaps,
1418
-
.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
1419
1875
.hw_clks = {
1420
1876
.hws = sm1_audio_hw_clks,
1421
1877
.num = ARRAY_SIZE(sm1_audio_hw_clks),
1422
1878
},
1423
-
.reset_offset = AUDIO_SM1_SW_RESET0,
1424
-
.reset_num = 39,
1879
+
.rst_drvname = "rst-sm1",
1425
1880
.max_register = AUDIO_EARCRX_DMAC_CLK_CTRL,
1426
1881
};
1427
1882
-70
drivers/clk/meson/axg-audio.h
-70
drivers/clk/meson/axg-audio.h
···
1
-
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2
-
/*
3
-
* Copyright (c) 2018 BayLibre, SAS.
4
-
* Author: Jerome Brunet <jbrunet@baylibre.com>
5
-
*/
6
-
7
-
#ifndef __AXG_AUDIO_CLKC_H
8
-
#define __AXG_AUDIO_CLKC_H
9
-
10
-
/*
11
-
* Audio Clock register offsets
12
-
*
13
-
* Register offsets from the datasheet must be multiplied by 4 before
14
-
* to get the right offset
15
-
*/
16
-
#define AUDIO_CLK_GATE_EN 0x000
17
-
#define AUDIO_MCLK_A_CTRL 0x004
18
-
#define AUDIO_MCLK_B_CTRL 0x008
19
-
#define AUDIO_MCLK_C_CTRL 0x00C
20
-
#define AUDIO_MCLK_D_CTRL 0x010
21
-
#define AUDIO_MCLK_E_CTRL 0x014
22
-
#define AUDIO_MCLK_F_CTRL 0x018
23
-
#define AUDIO_MST_PAD_CTRL0 0x01c
24
-
#define AUDIO_MST_PAD_CTRL1 0x020
25
-
#define AUDIO_SW_RESET 0x024
26
-
#define AUDIO_MST_A_SCLK_CTRL0 0x040
27
-
#define AUDIO_MST_A_SCLK_CTRL1 0x044
28
-
#define AUDIO_MST_B_SCLK_CTRL0 0x048
29
-
#define AUDIO_MST_B_SCLK_CTRL1 0x04C
30
-
#define AUDIO_MST_C_SCLK_CTRL0 0x050
31
-
#define AUDIO_MST_C_SCLK_CTRL1 0x054
32
-
#define AUDIO_MST_D_SCLK_CTRL0 0x058
33
-
#define AUDIO_MST_D_SCLK_CTRL1 0x05C
34
-
#define AUDIO_MST_E_SCLK_CTRL0 0x060
35
-
#define AUDIO_MST_E_SCLK_CTRL1 0x064
36
-
#define AUDIO_MST_F_SCLK_CTRL0 0x068
37
-
#define AUDIO_MST_F_SCLK_CTRL1 0x06C
38
-
#define AUDIO_CLK_TDMIN_A_CTRL 0x080
39
-
#define AUDIO_CLK_TDMIN_B_CTRL 0x084
40
-
#define AUDIO_CLK_TDMIN_C_CTRL 0x088
41
-
#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C
42
-
#define AUDIO_CLK_TDMOUT_A_CTRL 0x090
43
-
#define AUDIO_CLK_TDMOUT_B_CTRL 0x094
44
-
#define AUDIO_CLK_TDMOUT_C_CTRL 0x098
45
-
#define AUDIO_CLK_SPDIFIN_CTRL 0x09C
46
-
#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0
47
-
#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4
48
-
#define AUDIO_CLK_LOCKER_CTRL 0x0A8
49
-
#define AUDIO_CLK_PDMIN_CTRL0 0x0AC
50
-
#define AUDIO_CLK_PDMIN_CTRL1 0x0B0
51
-
#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
52
-
53
-
/* SM1 introduce new register and some shifts :( */
54
-
#define AUDIO_CLK_GATE_EN1 0x004
55
-
#define AUDIO_SM1_MCLK_A_CTRL 0x008
56
-
#define AUDIO_SM1_MCLK_B_CTRL 0x00C
57
-
#define AUDIO_SM1_MCLK_C_CTRL 0x010
58
-
#define AUDIO_SM1_MCLK_D_CTRL 0x014
59
-
#define AUDIO_SM1_MCLK_E_CTRL 0x018
60
-
#define AUDIO_SM1_MCLK_F_CTRL 0x01C
61
-
#define AUDIO_SM1_MST_PAD_CTRL0 0x020
62
-
#define AUDIO_SM1_MST_PAD_CTRL1 0x024
63
-
#define AUDIO_SM1_SW_RESET0 0x028
64
-
#define AUDIO_SM1_SW_RESET1 0x02C
65
-
#define AUDIO_CLK81_CTRL 0x030
66
-
#define AUDIO_CLK81_EN 0x034
67
-
#define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0
68
-
#define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4
69
-
70
-
#endif /*__AXG_AUDIO_CLKC_H */
+86
-132
drivers/clk/meson/axg.c
+86
-132
drivers/clk/meson/axg.c
···
18
18
#include "clk-regmap.h"
19
19
#include "clk-pll.h"
20
20
#include "clk-mpll.h"
21
-
#include "axg.h"
22
21
#include "meson-eeclk.h"
23
22
24
23
#include <dt-bindings/clock/axg-clkc.h>
24
+
25
+
#define HHI_GP0_PLL_CNTL 0x40
26
+
#define HHI_GP0_PLL_CNTL2 0x44
27
+
#define HHI_GP0_PLL_CNTL3 0x48
28
+
#define HHI_GP0_PLL_CNTL4 0x4c
29
+
#define HHI_GP0_PLL_CNTL5 0x50
30
+
#define HHI_GP0_PLL_STS 0x54
31
+
#define HHI_GP0_PLL_CNTL1 0x58
32
+
#define HHI_HIFI_PLL_CNTL 0x80
33
+
#define HHI_HIFI_PLL_CNTL2 0x84
34
+
#define HHI_HIFI_PLL_CNTL3 0x88
35
+
#define HHI_HIFI_PLL_CNTL4 0x8C
36
+
#define HHI_HIFI_PLL_CNTL5 0x90
37
+
#define HHI_HIFI_PLL_STS 0x94
38
+
#define HHI_HIFI_PLL_CNTL1 0x98
39
+
40
+
#define HHI_XTAL_DIVN_CNTL 0xbc
41
+
#define HHI_GCLK2_MPEG0 0xc0
42
+
#define HHI_GCLK2_MPEG1 0xc4
43
+
#define HHI_GCLK2_MPEG2 0xc8
44
+
#define HHI_GCLK2_OTHER 0xd0
45
+
#define HHI_GCLK2_AO 0xd4
46
+
#define HHI_PCIE_PLL_CNTL 0xd8
47
+
#define HHI_PCIE_PLL_CNTL1 0xdC
48
+
#define HHI_PCIE_PLL_CNTL2 0xe0
49
+
#define HHI_PCIE_PLL_CNTL3 0xe4
50
+
#define HHI_PCIE_PLL_CNTL4 0xe8
51
+
#define HHI_PCIE_PLL_CNTL5 0xec
52
+
#define HHI_PCIE_PLL_CNTL6 0xf0
53
+
#define HHI_PCIE_PLL_STS 0xf4
54
+
55
+
#define HHI_MEM_PD_REG0 0x100
56
+
#define HHI_VPU_MEM_PD_REG0 0x104
57
+
#define HHI_VIID_CLK_DIV 0x128
58
+
#define HHI_VIID_CLK_CNTL 0x12c
59
+
60
+
#define HHI_GCLK_MPEG0 0x140
61
+
#define HHI_GCLK_MPEG1 0x144
62
+
#define HHI_GCLK_MPEG2 0x148
63
+
#define HHI_GCLK_OTHER 0x150
64
+
#define HHI_GCLK_AO 0x154
65
+
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
66
+
#define HHI_SYS_CPU_RESET_CNTL 0x160
67
+
#define HHI_VID_CLK_DIV 0x164
68
+
#define HHI_SPICC_HCLK_CNTL 0x168
69
+
70
+
#define HHI_MPEG_CLK_CNTL 0x174
71
+
#define HHI_VID_CLK_CNTL 0x17c
72
+
#define HHI_TS_CLK_CNTL 0x190
73
+
#define HHI_VID_CLK_CNTL2 0x194
74
+
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
75
+
#define HHI_VID_PLL_CLK_DIV 0x1a0
76
+
#define HHI_VPU_CLK_CNTL 0x1bC
77
+
78
+
#define HHI_VAPBCLK_CNTL 0x1F4
79
+
80
+
#define HHI_GEN_CLK_CNTL 0x228
81
+
82
+
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
83
+
#define HHI_NAND_CLK_CNTL 0x25C
84
+
#define HHI_SD_EMMC_CLK_CNTL 0x264
85
+
86
+
#define HHI_MPLL_CNTL 0x280
87
+
#define HHI_MPLL_CNTL2 0x284
88
+
#define HHI_MPLL_CNTL3 0x288
89
+
#define HHI_MPLL_CNTL4 0x28C
90
+
#define HHI_MPLL_CNTL5 0x290
91
+
#define HHI_MPLL_CNTL6 0x294
92
+
#define HHI_MPLL_CNTL7 0x298
93
+
#define HHI_MPLL_CNTL8 0x29C
94
+
#define HHI_MPLL_CNTL9 0x2A0
95
+
#define HHI_MPLL_CNTL10 0x2A4
96
+
97
+
#define HHI_MPLL3_CNTL0 0x2E0
98
+
#define HHI_MPLL3_CNTL1 0x2E4
99
+
#define HHI_PLL_TOP_MISC 0x2E8
100
+
101
+
#define HHI_SYS_PLL_CNTL1 0x2FC
102
+
#define HHI_SYS_PLL_CNTL 0x300
103
+
#define HHI_SYS_PLL_CNTL2 0x304
104
+
#define HHI_SYS_PLL_CNTL3 0x308
105
+
#define HHI_SYS_PLL_CNTL4 0x30c
106
+
#define HHI_SYS_PLL_CNTL5 0x310
107
+
#define HHI_SYS_PLL_STS 0x314
108
+
#define HHI_DPLL_TOP_I 0x318
109
+
#define HHI_DPLL_TOP2_I 0x31C
25
110
26
111
static struct clk_regmap axg_fixed_pll_dco = {
27
112
.data = &(struct meson_clk_pll_data){
···
2110
2025
[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
2111
2026
};
2112
2027
2113
-
/* Convenience table to populate regmap in .probe */
2114
-
static struct clk_regmap *const axg_clk_regmaps[] = {
2115
-
&axg_clk81,
2116
-
&axg_ddr,
2117
-
&axg_audio_locker,
2118
-
&axg_mipi_dsi_host,
2119
-
&axg_isa,
2120
-
&axg_pl301,
2121
-
&axg_periphs,
2122
-
&axg_spicc_0,
2123
-
&axg_i2c,
2124
-
&axg_rng0,
2125
-
&axg_uart0,
2126
-
&axg_mipi_dsi_phy,
2127
-
&axg_spicc_1,
2128
-
&axg_pcie_a,
2129
-
&axg_pcie_b,
2130
-
&axg_hiu_reg,
2131
-
&axg_assist_misc,
2132
-
&axg_emmc_b,
2133
-
&axg_emmc_c,
2134
-
&axg_dma,
2135
-
&axg_spi,
2136
-
&axg_audio,
2137
-
&axg_eth_core,
2138
-
&axg_uart1,
2139
-
&axg_g2d,
2140
-
&axg_usb0,
2141
-
&axg_usb1,
2142
-
&axg_reset,
2143
-
&axg_usb_general,
2144
-
&axg_ahb_arb0,
2145
-
&axg_efuse,
2146
-
&axg_boot_rom,
2147
-
&axg_ahb_data_bus,
2148
-
&axg_ahb_ctrl_bus,
2149
-
&axg_usb1_to_ddr,
2150
-
&axg_usb0_to_ddr,
2151
-
&axg_mmc_pclk,
2152
-
&axg_vpu_intr,
2153
-
&axg_sec_ahb_ahb3_bridge,
2154
-
&axg_gic,
2155
-
&axg_ao_media_cpu,
2156
-
&axg_ao_ahb_sram,
2157
-
&axg_ao_ahb_bus,
2158
-
&axg_ao_iface,
2159
-
&axg_ao_i2c,
2160
-
&axg_sd_emmc_b_clk0,
2161
-
&axg_sd_emmc_c_clk0,
2162
-
&axg_mpeg_clk_div,
2163
-
&axg_sd_emmc_b_clk0_div,
2164
-
&axg_sd_emmc_c_clk0_div,
2165
-
&axg_mpeg_clk_sel,
2166
-
&axg_sd_emmc_b_clk0_sel,
2167
-
&axg_sd_emmc_c_clk0_sel,
2168
-
&axg_mpll0,
2169
-
&axg_mpll1,
2170
-
&axg_mpll2,
2171
-
&axg_mpll3,
2172
-
&axg_mpll0_div,
2173
-
&axg_mpll1_div,
2174
-
&axg_mpll2_div,
2175
-
&axg_mpll3_div,
2176
-
&axg_fixed_pll,
2177
-
&axg_sys_pll,
2178
-
&axg_gp0_pll,
2179
-
&axg_hifi_pll,
2180
-
&axg_mpll_prediv,
2181
-
&axg_fclk_div2,
2182
-
&axg_fclk_div3,
2183
-
&axg_fclk_div4,
2184
-
&axg_fclk_div5,
2185
-
&axg_fclk_div7,
2186
-
&axg_pcie_pll_dco,
2187
-
&axg_pcie_pll_od,
2188
-
&axg_pcie_pll,
2189
-
&axg_pcie_mux,
2190
-
&axg_pcie_ref,
2191
-
&axg_pcie_cml_en0,
2192
-
&axg_pcie_cml_en1,
2193
-
&axg_gen_clk_sel,
2194
-
&axg_gen_clk_div,
2195
-
&axg_gen_clk,
2196
-
&axg_fixed_pll_dco,
2197
-
&axg_sys_pll_dco,
2198
-
&axg_gp0_pll_dco,
2199
-
&axg_hifi_pll_dco,
2200
-
&axg_pcie_pll_dco,
2201
-
&axg_pcie_pll_od,
2202
-
&axg_vpu_0_div,
2203
-
&axg_vpu_0_sel,
2204
-
&axg_vpu_0,
2205
-
&axg_vpu_1_div,
2206
-
&axg_vpu_1_sel,
2207
-
&axg_vpu_1,
2208
-
&axg_vpu,
2209
-
&axg_vapb_0_div,
2210
-
&axg_vapb_0_sel,
2211
-
&axg_vapb_0,
2212
-
&axg_vapb_1_div,
2213
-
&axg_vapb_1_sel,
2214
-
&axg_vapb_1,
2215
-
&axg_vapb_sel,
2216
-
&axg_vapb,
2217
-
&axg_vclk,
2218
-
&axg_vclk2,
2219
-
&axg_vclk_sel,
2220
-
&axg_vclk2_sel,
2221
-
&axg_vclk_input,
2222
-
&axg_vclk2_input,
2223
-
&axg_vclk_div,
2224
-
&axg_vclk_div1,
2225
-
&axg_vclk2_div,
2226
-
&axg_vclk2_div1,
2227
-
&axg_vclk_div2_en,
2228
-
&axg_vclk_div4_en,
2229
-
&axg_vclk_div6_en,
2230
-
&axg_vclk_div12_en,
2231
-
&axg_vclk2_div2_en,
2232
-
&axg_vclk2_div4_en,
2233
-
&axg_vclk2_div6_en,
2234
-
&axg_vclk2_div12_en,
2235
-
&axg_cts_encl_sel,
2236
-
&axg_cts_encl,
2237
-
&axg_vdin_meas_sel,
2238
-
&axg_vdin_meas_div,
2239
-
&axg_vdin_meas,
2240
-
};
2241
-
2242
2028
static const struct meson_eeclkc_data axg_clkc_data = {
2243
-
.regmap_clks = axg_clk_regmaps,
2244
-
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
2245
2029
.hw_clks = {
2246
2030
.hws = axg_hw_clks,
2247
2031
.num = ARRAY_SIZE(axg_hw_clks),
-105
drivers/clk/meson/axg.h
-105
drivers/clk/meson/axg.h
···
1
-
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2
-
/*
3
-
* Copyright (c) 2016 AmLogic, Inc.
4
-
* Author: Michael Turquette <mturquette@baylibre.com>
5
-
*
6
-
* Copyright (c) 2017 Amlogic, inc.
7
-
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
8
-
*
9
-
*/
10
-
#ifndef __AXG_H
11
-
#define __AXG_H
12
-
13
-
/*
14
-
* Clock controller register offsets
15
-
*
16
-
* Register offsets from the data sheet must be multiplied by 4 before
17
-
* adding them to the base address to get the right value.
18
-
*/
19
-
#define HHI_GP0_PLL_CNTL 0x40
20
-
#define HHI_GP0_PLL_CNTL2 0x44
21
-
#define HHI_GP0_PLL_CNTL3 0x48
22
-
#define HHI_GP0_PLL_CNTL4 0x4c
23
-
#define HHI_GP0_PLL_CNTL5 0x50
24
-
#define HHI_GP0_PLL_STS 0x54
25
-
#define HHI_GP0_PLL_CNTL1 0x58
26
-
#define HHI_HIFI_PLL_CNTL 0x80
27
-
#define HHI_HIFI_PLL_CNTL2 0x84
28
-
#define HHI_HIFI_PLL_CNTL3 0x88
29
-
#define HHI_HIFI_PLL_CNTL4 0x8C
30
-
#define HHI_HIFI_PLL_CNTL5 0x90
31
-
#define HHI_HIFI_PLL_STS 0x94
32
-
#define HHI_HIFI_PLL_CNTL1 0x98
33
-
34
-
#define HHI_XTAL_DIVN_CNTL 0xbc
35
-
#define HHI_GCLK2_MPEG0 0xc0
36
-
#define HHI_GCLK2_MPEG1 0xc4
37
-
#define HHI_GCLK2_MPEG2 0xc8
38
-
#define HHI_GCLK2_OTHER 0xd0
39
-
#define HHI_GCLK2_AO 0xd4
40
-
#define HHI_PCIE_PLL_CNTL 0xd8
41
-
#define HHI_PCIE_PLL_CNTL1 0xdC
42
-
#define HHI_PCIE_PLL_CNTL2 0xe0
43
-
#define HHI_PCIE_PLL_CNTL3 0xe4
44
-
#define HHI_PCIE_PLL_CNTL4 0xe8
45
-
#define HHI_PCIE_PLL_CNTL5 0xec
46
-
#define HHI_PCIE_PLL_CNTL6 0xf0
47
-
#define HHI_PCIE_PLL_STS 0xf4
48
-
49
-
#define HHI_MEM_PD_REG0 0x100
50
-
#define HHI_VPU_MEM_PD_REG0 0x104
51
-
#define HHI_VIID_CLK_DIV 0x128
52
-
#define HHI_VIID_CLK_CNTL 0x12c
53
-
54
-
#define HHI_GCLK_MPEG0 0x140
55
-
#define HHI_GCLK_MPEG1 0x144
56
-
#define HHI_GCLK_MPEG2 0x148
57
-
#define HHI_GCLK_OTHER 0x150
58
-
#define HHI_GCLK_AO 0x154
59
-
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
60
-
#define HHI_SYS_CPU_RESET_CNTL 0x160
61
-
#define HHI_VID_CLK_DIV 0x164
62
-
#define HHI_SPICC_HCLK_CNTL 0x168
63
-
64
-
#define HHI_MPEG_CLK_CNTL 0x174
65
-
#define HHI_VID_CLK_CNTL 0x17c
66
-
#define HHI_TS_CLK_CNTL 0x190
67
-
#define HHI_VID_CLK_CNTL2 0x194
68
-
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
69
-
#define HHI_VID_PLL_CLK_DIV 0x1a0
70
-
#define HHI_VPU_CLK_CNTL 0x1bC
71
-
72
-
#define HHI_VAPBCLK_CNTL 0x1F4
73
-
74
-
#define HHI_GEN_CLK_CNTL 0x228
75
-
76
-
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
77
-
#define HHI_NAND_CLK_CNTL 0x25C
78
-
#define HHI_SD_EMMC_CLK_CNTL 0x264
79
-
80
-
#define HHI_MPLL_CNTL 0x280
81
-
#define HHI_MPLL_CNTL2 0x284
82
-
#define HHI_MPLL_CNTL3 0x288
83
-
#define HHI_MPLL_CNTL4 0x28C
84
-
#define HHI_MPLL_CNTL5 0x290
85
-
#define HHI_MPLL_CNTL6 0x294
86
-
#define HHI_MPLL_CNTL7 0x298
87
-
#define HHI_MPLL_CNTL8 0x29C
88
-
#define HHI_MPLL_CNTL9 0x2A0
89
-
#define HHI_MPLL_CNTL10 0x2A4
90
-
91
-
#define HHI_MPLL3_CNTL0 0x2E0
92
-
#define HHI_MPLL3_CNTL1 0x2E4
93
-
#define HHI_PLL_TOP_MISC 0x2E8
94
-
95
-
#define HHI_SYS_PLL_CNTL1 0x2FC
96
-
#define HHI_SYS_PLL_CNTL 0x300
97
-
#define HHI_SYS_PLL_CNTL2 0x304
98
-
#define HHI_SYS_PLL_CNTL3 0x308
99
-
#define HHI_SYS_PLL_CNTL4 0x30c
100
-
#define HHI_SYS_PLL_CNTL5 0x310
101
-
#define HHI_SYS_PLL_STS 0x314
102
-
#define HHI_DPLL_TOP_I 0x318
103
-
#define HHI_DPLL_TOP2_I 0x31C
104
-
105
-
#endif /* __AXG_H */
+1
-209
drivers/clk/meson/c3-peripherals.c
+1
-209
drivers/clk/meson/c3-peripherals.c
···
2092
2092
[CLKID_VAPB] = &vapb.hw,
2093
2093
};
2094
2094
2095
-
/* Convenience table to populate regmap in .probe */
2096
-
static struct clk_regmap *const c3_periphs_clk_regmaps[] = {
2097
-
&rtc_xtal_clkin,
2098
-
&rtc_32k_div,
2099
-
&rtc_32k_mux,
2100
-
&rtc_32k,
2101
-
&rtc_clk,
2102
-
&sys_reset_ctrl,
2103
-
&sys_pwr_ctrl,
2104
-
&sys_pad_ctrl,
2105
-
&sys_ctrl,
2106
-
&sys_ts_pll,
2107
-
&sys_dev_arb,
2108
-
&sys_mmc_pclk,
2109
-
&sys_cpu_ctrl,
2110
-
&sys_jtag_ctrl,
2111
-
&sys_ir_ctrl,
2112
-
&sys_irq_ctrl,
2113
-
&sys_msr_clk,
2114
-
&sys_rom,
2115
-
&sys_uart_f,
2116
-
&sys_cpu_apb,
2117
-
&sys_rsa,
2118
-
&sys_sar_adc,
2119
-
&sys_startup,
2120
-
&sys_secure,
2121
-
&sys_spifc,
2122
-
&sys_nna,
2123
-
&sys_eth_mac,
2124
-
&sys_gic,
2125
-
&sys_rama,
2126
-
&sys_big_nic,
2127
-
&sys_ramb,
2128
-
&sys_audio_pclk,
2129
-
&sys_pwm_kl,
2130
-
&sys_pwm_ij,
2131
-
&sys_usb,
2132
-
&sys_sd_emmc_a,
2133
-
&sys_sd_emmc_c,
2134
-
&sys_pwm_ab,
2135
-
&sys_pwm_cd,
2136
-
&sys_pwm_ef,
2137
-
&sys_pwm_gh,
2138
-
&sys_spicc_1,
2139
-
&sys_spicc_0,
2140
-
&sys_uart_a,
2141
-
&sys_uart_b,
2142
-
&sys_uart_c,
2143
-
&sys_uart_d,
2144
-
&sys_uart_e,
2145
-
&sys_i2c_m_a,
2146
-
&sys_i2c_m_b,
2147
-
&sys_i2c_m_c,
2148
-
&sys_i2c_m_d,
2149
-
&sys_i2c_s_a,
2150
-
&sys_rtc,
2151
-
&sys_ge2d,
2152
-
&sys_isp,
2153
-
&sys_gpv_isp_nic,
2154
-
&sys_gpv_cve_nic,
2155
-
&sys_mipi_dsi_host,
2156
-
&sys_mipi_dsi_phy,
2157
-
&sys_eth_phy,
2158
-
&sys_acodec,
2159
-
&sys_dwap,
2160
-
&sys_dos,
2161
-
&sys_cve,
2162
-
&sys_vout,
2163
-
&sys_vc9000e,
2164
-
&sys_pwm_mn,
2165
-
&sys_sd_emmc_b,
2166
-
&axi_sys_nic,
2167
-
&axi_isp_nic,
2168
-
&axi_cve_nic,
2169
-
&axi_ramb,
2170
-
&axi_rama,
2171
-
&axi_cpu_dmc,
2172
-
&axi_nic,
2173
-
&axi_dma,
2174
-
&axi_mux_nic,
2175
-
&axi_cve,
2176
-
&axi_dev1_dmc,
2177
-
&axi_dev0_dmc,
2178
-
&axi_dsp_dmc,
2179
-
&clk_12_24m_in,
2180
-
&clk_12_24m,
2181
-
&fclk_25m_div,
2182
-
&fclk_25m,
2183
-
&gen_sel,
2184
-
&gen_div,
2185
-
&gen,
2186
-
&saradc_sel,
2187
-
&saradc_div,
2188
-
&saradc,
2189
-
&pwm_a_sel,
2190
-
&pwm_a_div,
2191
-
&pwm_a,
2192
-
&pwm_b_sel,
2193
-
&pwm_b_div,
2194
-
&pwm_b,
2195
-
&pwm_c_sel,
2196
-
&pwm_c_div,
2197
-
&pwm_c,
2198
-
&pwm_d_sel,
2199
-
&pwm_d_div,
2200
-
&pwm_d,
2201
-
&pwm_e_sel,
2202
-
&pwm_e_div,
2203
-
&pwm_e,
2204
-
&pwm_f_sel,
2205
-
&pwm_f_div,
2206
-
&pwm_f,
2207
-
&pwm_g_sel,
2208
-
&pwm_g_div,
2209
-
&pwm_g,
2210
-
&pwm_h_sel,
2211
-
&pwm_h_div,
2212
-
&pwm_h,
2213
-
&pwm_i_sel,
2214
-
&pwm_i_div,
2215
-
&pwm_i,
2216
-
&pwm_j_sel,
2217
-
&pwm_j_div,
2218
-
&pwm_j,
2219
-
&pwm_k_sel,
2220
-
&pwm_k_div,
2221
-
&pwm_k,
2222
-
&pwm_l_sel,
2223
-
&pwm_l_div,
2224
-
&pwm_l,
2225
-
&pwm_m_sel,
2226
-
&pwm_m_div,
2227
-
&pwm_m,
2228
-
&pwm_n_sel,
2229
-
&pwm_n_div,
2230
-
&pwm_n,
2231
-
&spicc_a_sel,
2232
-
&spicc_a_div,
2233
-
&spicc_a,
2234
-
&spicc_b_sel,
2235
-
&spicc_b_div,
2236
-
&spicc_b,
2237
-
&spifc_sel,
2238
-
&spifc_div,
2239
-
&spifc,
2240
-
&sd_emmc_a_sel,
2241
-
&sd_emmc_a_div,
2242
-
&sd_emmc_a,
2243
-
&sd_emmc_b_sel,
2244
-
&sd_emmc_b_div,
2245
-
&sd_emmc_b,
2246
-
&sd_emmc_c_sel,
2247
-
&sd_emmc_c_div,
2248
-
&sd_emmc_c,
2249
-
&ts_div,
2250
-
&ts,
2251
-
ð_125m,
2252
-
ð_rmii_div,
2253
-
ð_rmii,
2254
-
&mipi_dsi_meas_sel,
2255
-
&mipi_dsi_meas_div,
2256
-
&mipi_dsi_meas,
2257
-
&dsi_phy_sel,
2258
-
&dsi_phy_div,
2259
-
&dsi_phy,
2260
-
&vout_mclk_sel,
2261
-
&vout_mclk_div,
2262
-
&vout_mclk,
2263
-
&vout_enc_sel,
2264
-
&vout_enc_div,
2265
-
&vout_enc,
2266
-
&hcodec_0_sel,
2267
-
&hcodec_0_div,
2268
-
&hcodec_0,
2269
-
&hcodec_1_sel,
2270
-
&hcodec_1_div,
2271
-
&hcodec_1,
2272
-
&hcodec,
2273
-
&vc9000e_aclk_sel,
2274
-
&vc9000e_aclk_div,
2275
-
&vc9000e_aclk,
2276
-
&vc9000e_core_sel,
2277
-
&vc9000e_core_div,
2278
-
&vc9000e_core,
2279
-
&csi_phy0_sel,
2280
-
&csi_phy0_div,
2281
-
&csi_phy0,
2282
-
&dewarpa_sel,
2283
-
&dewarpa_div,
2284
-
&dewarpa,
2285
-
&isp0_sel,
2286
-
&isp0_div,
2287
-
&isp0,
2288
-
&nna_core_sel,
2289
-
&nna_core_div,
2290
-
&nna_core,
2291
-
&ge2d_sel,
2292
-
&ge2d_div,
2293
-
&ge2d,
2294
-
&vapb_sel,
2295
-
&vapb_div,
2296
-
&vapb,
2297
-
};
2298
-
2299
2095
static const struct regmap_config clkc_regmap_config = {
2300
2096
.reg_bits = 32,
2301
2097
.val_bits = 32,
···
2109
2313
struct device *dev = &pdev->dev;
2110
2314
struct regmap *regmap;
2111
2315
void __iomem *base;
2112
-
int clkid, ret, i;
2316
+
int clkid, ret;
2113
2317
2114
2318
base = devm_platform_ioremap_resource(pdev, 0);
2115
2319
if (IS_ERR(base))
···
2118
2322
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
2119
2323
if (IS_ERR(regmap))
2120
2324
return PTR_ERR(regmap);
2121
-
2122
-
/* Populate regmap for the regmap backed clocks */
2123
-
for (i = 0; i < ARRAY_SIZE(c3_periphs_clk_regmaps); i++)
2124
-
c3_periphs_clk_regmaps[i]->map = regmap;
2125
2325
2126
2326
for (clkid = 0; clkid < c3_periphs_clks.num; clkid++) {
2127
2327
/* array might be sparse */
+1
-31
drivers/clk/meson/c3-pll.c
+1
-31
drivers/clk/meson/c3-pll.c
···
653
653
[CLKID_MCLK1] = &mclk1.hw
654
654
};
655
655
656
-
/* Convenience table to populate regmap in .probe */
657
-
static struct clk_regmap *const c3_pll_clk_regmaps[] = {
658
-
&fclk_50m_en,
659
-
&fclk_div2,
660
-
&fclk_div2p5,
661
-
&fclk_div3,
662
-
&fclk_div4,
663
-
&fclk_div5,
664
-
&fclk_div7,
665
-
&gp0_pll_dco,
666
-
&gp0_pll,
667
-
&hifi_pll_dco,
668
-
&hifi_pll,
669
-
&mclk_pll_dco,
670
-
&mclk_pll_od,
671
-
&mclk_pll,
672
-
&mclk0_sel,
673
-
&mclk0_div_en,
674
-
&mclk0_div,
675
-
&mclk0,
676
-
&mclk1_sel,
677
-
&mclk1_div_en,
678
-
&mclk1_div,
679
-
&mclk1,
680
-
};
681
-
682
656
static const struct regmap_config clkc_regmap_config = {
683
657
.reg_bits = 32,
684
658
.val_bits = 32,
···
670
696
struct device *dev = &pdev->dev;
671
697
struct regmap *regmap;
672
698
void __iomem *base;
673
-
int clkid, ret, i;
699
+
int clkid, ret;
674
700
675
701
base = devm_platform_ioremap_resource(pdev, 0);
676
702
if (IS_ERR(base))
···
679
705
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
680
706
if (IS_ERR(regmap))
681
707
return PTR_ERR(regmap);
682
-
683
-
/* Populate regmap for the regmap backed clocks */
684
-
for (i = 0; i < ARRAY_SIZE(c3_pll_clk_regmaps); i++)
685
-
c3_pll_clk_regmaps[i]->map = regmap;
686
708
687
709
for (clkid = 0; clkid < c3_pll_clks.num; clkid++) {
688
710
/* array might be sparse */
+1
drivers/clk/meson/clk-cpu-dyndiv.c
+1
drivers/clk/meson/clk-cpu-dyndiv.c
+2
drivers/clk/meson/clk-dualdiv.c
+2
drivers/clk/meson/clk-dualdiv.c
···
126
126
}
127
127
128
128
const struct clk_ops meson_clk_dualdiv_ops = {
129
+
.init = clk_regmap_init,
129
130
.recalc_rate = meson_clk_dualdiv_recalc_rate,
130
131
.determine_rate = meson_clk_dualdiv_determine_rate,
131
132
.set_rate = meson_clk_dualdiv_set_rate,
···
134
133
EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ops, "CLK_MESON");
135
134
136
135
const struct clk_ops meson_clk_dualdiv_ro_ops = {
136
+
.init = clk_regmap_init,
137
137
.recalc_rate = meson_clk_dualdiv_recalc_rate,
138
138
};
139
139
EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ro_ops, "CLK_MESON");
+6
drivers/clk/meson/clk-mpll.c
+6
drivers/clk/meson/clk-mpll.c
···
128
128
{
129
129
struct clk_regmap *clk = to_clk_regmap(hw);
130
130
struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
131
+
int ret;
132
+
133
+
ret = clk_regmap_init(hw);
134
+
if (ret)
135
+
return ret;
131
136
132
137
if (mpll->init_count)
133
138
regmap_multi_reg_write(clk->map, mpll->init_regs,
···
156
151
}
157
152
158
153
const struct clk_ops meson_clk_mpll_ro_ops = {
154
+
.init = clk_regmap_init,
159
155
.recalc_rate = mpll_recalc_rate,
160
156
.determine_rate = mpll_determine_rate,
161
157
};
+11
drivers/clk/meson/clk-phase.c
+11
drivers/clk/meson/clk-phase.c
···
58
58
}
59
59
60
60
const struct clk_ops meson_clk_phase_ops = {
61
+
.init = clk_regmap_init,
61
62
.get_phase = meson_clk_phase_get_phase,
62
63
.set_phase = meson_clk_phase_set_phase,
63
64
};
···
84
83
struct clk_regmap *clk = to_clk_regmap(hw);
85
84
struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
86
85
unsigned int val;
86
+
int ret;
87
+
88
+
ret = clk_regmap_init(hw);
89
+
if (ret)
90
+
return ret;
87
91
88
92
/* Get phase 0 and sync it to phase 1 and 2 */
89
93
val = meson_parm_read(clk->map, &tph->ph0);
···
148
142
struct clk_regmap *clk = to_clk_regmap(hw);
149
143
struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
150
144
unsigned int val;
145
+
int ret;
146
+
147
+
ret = clk_regmap_init(hw);
148
+
if (ret)
149
+
return ret;
151
150
152
151
/* Get phase and sync the inverted value to ws */
153
152
val = meson_parm_read(clk->map, &tph->ph);
+7
drivers/clk/meson/clk-pll.c
+7
drivers/clk/meson/clk-pll.c
···
311
311
{
312
312
struct clk_regmap *clk = to_clk_regmap(hw);
313
313
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
314
+
int ret;
315
+
316
+
ret = clk_regmap_init(hw);
317
+
if (ret)
318
+
return ret;
314
319
315
320
/*
316
321
* Keep the clock running, which was already initialized and enabled
···
473
468
* the other ops except set_rate since the rate is fixed.
474
469
*/
475
470
const struct clk_ops meson_clk_pcie_pll_ops = {
471
+
.init = clk_regmap_init,
476
472
.recalc_rate = meson_clk_pll_recalc_rate,
477
473
.determine_rate = meson_clk_pll_determine_rate,
478
474
.is_enabled = meson_clk_pll_is_enabled,
···
494
488
EXPORT_SYMBOL_NS_GPL(meson_clk_pll_ops, "CLK_MESON");
495
489
496
490
const struct clk_ops meson_clk_pll_ro_ops = {
491
+
.init = clk_regmap_init,
497
492
.recalc_rate = meson_clk_pll_recalc_rate,
498
493
.is_enabled = meson_clk_pll_is_enabled,
499
494
};
+49
drivers/clk/meson/clk-regmap.c
+49
drivers/clk/meson/clk-regmap.c
···
4
4
* Author: Jerome Brunet <jbrunet@baylibre.com>
5
5
*/
6
6
7
+
#include <linux/device.h>
7
8
#include <linux/module.h>
9
+
#include <linux/mfd/syscon.h>
8
10
#include "clk-regmap.h"
11
+
12
+
int clk_regmap_init(struct clk_hw *hw)
13
+
{
14
+
struct clk_regmap *clk = to_clk_regmap(hw);
15
+
struct device_node *np, *parent_np;
16
+
struct device *dev;
17
+
18
+
/* Allow regmap to be preset as it was historically done */
19
+
if (clk->map)
20
+
return 0;
21
+
22
+
/*
23
+
* FIXME: what follows couples the controller implementation
24
+
* and clk_regmap clock type. This situation is not desirable
25
+
* but temporary, until the controller is able to register
26
+
* a hook to initialize a clock type
27
+
*/
28
+
29
+
/* Check the usual dev enabled controller with an basic IO regmap */
30
+
dev = clk_hw_get_dev(hw);
31
+
if (dev) {
32
+
clk->map = dev_get_regmap(dev, NULL);
33
+
if (clk->map)
34
+
return 0;
35
+
}
36
+
37
+
/* Move on to early and syscon based controllers */
38
+
np = clk_hw_get_of_node(hw);
39
+
if (np) {
40
+
parent_np = of_get_parent(np);
41
+
clk->map = syscon_node_to_regmap(parent_np);
42
+
of_node_put(parent_np);
43
+
44
+
if (!IS_ERR_OR_NULL(clk->map))
45
+
return 0;
46
+
}
47
+
48
+
/* Bail out if regmap can't be found */
49
+
return -EINVAL;
50
+
}
51
+
EXPORT_SYMBOL_NS_GPL(clk_regmap_init, "CLK_MESON");
9
52
10
53
static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable)
11
54
{
···
88
45
}
89
46
90
47
const struct clk_ops clk_regmap_gate_ops = {
48
+
.init = clk_regmap_init,
91
49
.enable = clk_regmap_gate_enable,
92
50
.disable = clk_regmap_gate_disable,
93
51
.is_enabled = clk_regmap_gate_is_enabled,
···
96
52
EXPORT_SYMBOL_NS_GPL(clk_regmap_gate_ops, "CLK_MESON");
97
53
98
54
const struct clk_ops clk_regmap_gate_ro_ops = {
55
+
.init = clk_regmap_init,
99
56
.is_enabled = clk_regmap_gate_is_enabled,
100
57
};
101
58
EXPORT_SYMBOL_NS_GPL(clk_regmap_gate_ro_ops, "CLK_MESON");
···
166
121
/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */
167
122
168
123
const struct clk_ops clk_regmap_divider_ops = {
124
+
.init = clk_regmap_init,
169
125
.recalc_rate = clk_regmap_div_recalc_rate,
170
126
.determine_rate = clk_regmap_div_determine_rate,
171
127
.set_rate = clk_regmap_div_set_rate,
···
174
128
EXPORT_SYMBOL_NS_GPL(clk_regmap_divider_ops, "CLK_MESON");
175
129
176
130
const struct clk_ops clk_regmap_divider_ro_ops = {
131
+
.init = clk_regmap_init,
177
132
.recalc_rate = clk_regmap_div_recalc_rate,
178
133
.determine_rate = clk_regmap_div_determine_rate,
179
134
};
···
217
170
}
218
171
219
172
const struct clk_ops clk_regmap_mux_ops = {
173
+
.init = clk_regmap_init,
220
174
.get_parent = clk_regmap_mux_get_parent,
221
175
.set_parent = clk_regmap_mux_set_parent,
222
176
.determine_rate = clk_regmap_mux_determine_rate,
···
225
177
EXPORT_SYMBOL_NS_GPL(clk_regmap_mux_ops, "CLK_MESON");
226
178
227
179
const struct clk_ops clk_regmap_mux_ro_ops = {
180
+
.init = clk_regmap_init,
228
181
.get_parent = clk_regmap_mux_get_parent,
229
182
};
230
183
EXPORT_SYMBOL_NS_GPL(clk_regmap_mux_ro_ops, "CLK_MESON");
+4
drivers/clk/meson/clk-regmap.h
+4
drivers/clk/meson/clk-regmap.h
···
7
7
#ifndef __CLK_REGMAP_H
8
8
#define __CLK_REGMAP_H
9
9
10
+
#include <linux/device.h>
10
11
#include <linux/clk-provider.h>
11
12
#include <linux/regmap.h>
12
13
···
31
30
{
32
31
return container_of(hw, struct clk_regmap, hw);
33
32
}
33
+
34
+
/* clk_regmap init op to get and cache regmap from the controllers */
35
+
int clk_regmap_init(struct clk_hw *hw);
34
36
35
37
/**
36
38
* struct clk_regmap_gate_data - regmap backed gate specific data
-34
drivers/clk/meson/g12a-aoclk.c
-34
drivers/clk/meson/g12a-aoclk.c
···
381
381
[RESET_AO_IR_OUT] = 23,
382
382
};
383
383
384
-
static struct clk_regmap *g12a_aoclk_regmap[] = {
385
-
&g12a_aoclk_ahb,
386
-
&g12a_aoclk_ir_in,
387
-
&g12a_aoclk_i2c_m0,
388
-
&g12a_aoclk_i2c_s0,
389
-
&g12a_aoclk_uart,
390
-
&g12a_aoclk_prod_i2c,
391
-
&g12a_aoclk_uart2,
392
-
&g12a_aoclk_ir_out,
393
-
&g12a_aoclk_saradc,
394
-
&g12a_aoclk_mailbox,
395
-
&g12a_aoclk_m3,
396
-
&g12a_aoclk_ahb_sram,
397
-
&g12a_aoclk_rti,
398
-
&g12a_aoclk_m4_fclk,
399
-
&g12a_aoclk_m4_hclk,
400
-
&g12a_aoclk_cts_oscin,
401
-
&g12a_aoclk_32k_by_oscin_pre,
402
-
&g12a_aoclk_32k_by_oscin_div,
403
-
&g12a_aoclk_32k_by_oscin_sel,
404
-
&g12a_aoclk_32k_by_oscin,
405
-
&g12a_aoclk_cec_pre,
406
-
&g12a_aoclk_cec_div,
407
-
&g12a_aoclk_cec_sel,
408
-
&g12a_aoclk_cec,
409
-
&g12a_aoclk_cts_rtc_oscin,
410
-
&g12a_aoclk_clk81,
411
-
&g12a_aoclk_saradc_mux,
412
-
&g12a_aoclk_saradc_div,
413
-
&g12a_aoclk_saradc_gate,
414
-
};
415
-
416
384
static struct clk_hw *g12a_aoclk_hw_clks[] = {
417
385
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
418
386
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
···
417
449
.reset_reg = AO_RTI_GEN_CNTL_REG0,
418
450
.num_reset = ARRAY_SIZE(g12a_aoclk_reset),
419
451
.reset = g12a_aoclk_reset,
420
-
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
421
-
.clks = g12a_aoclk_regmap,
422
452
.hw_clks = {
423
453
.hws = g12a_aoclk_hw_clks,
424
454
.num = ARRAY_SIZE(g12a_aoclk_hw_clks),
+110
-262
drivers/clk/meson/g12a.c
+110
-262
drivers/clk/meson/g12a.c
···
24
24
#include "vid-pll-div.h"
25
25
#include "vclk.h"
26
26
#include "meson-eeclk.h"
27
-
#include "g12a.h"
28
27
29
28
#include <dt-bindings/clock/g12a-clkc.h>
29
+
30
+
#define HHI_MIPI_CNTL0 0x000
31
+
#define HHI_MIPI_CNTL1 0x004
32
+
#define HHI_MIPI_CNTL2 0x008
33
+
#define HHI_MIPI_STS 0x00c
34
+
#define HHI_GP0_PLL_CNTL0 0x040
35
+
#define HHI_GP0_PLL_CNTL1 0x044
36
+
#define HHI_GP0_PLL_CNTL2 0x048
37
+
#define HHI_GP0_PLL_CNTL3 0x04c
38
+
#define HHI_GP0_PLL_CNTL4 0x050
39
+
#define HHI_GP0_PLL_CNTL5 0x054
40
+
#define HHI_GP0_PLL_CNTL6 0x058
41
+
#define HHI_GP0_PLL_STS 0x05c
42
+
#define HHI_GP1_PLL_CNTL0 0x060
43
+
#define HHI_GP1_PLL_CNTL1 0x064
44
+
#define HHI_GP1_PLL_CNTL2 0x068
45
+
#define HHI_GP1_PLL_CNTL3 0x06c
46
+
#define HHI_GP1_PLL_CNTL4 0x070
47
+
#define HHI_GP1_PLL_CNTL5 0x074
48
+
#define HHI_GP1_PLL_CNTL6 0x078
49
+
#define HHI_GP1_PLL_STS 0x07c
50
+
#define HHI_PCIE_PLL_CNTL0 0x098
51
+
#define HHI_PCIE_PLL_CNTL1 0x09c
52
+
#define HHI_PCIE_PLL_CNTL2 0x0a0
53
+
#define HHI_PCIE_PLL_CNTL3 0x0a4
54
+
#define HHI_PCIE_PLL_CNTL4 0x0a8
55
+
#define HHI_PCIE_PLL_CNTL5 0x0ac
56
+
#define HHI_PCIE_PLL_STS 0x0b8
57
+
#define HHI_HIFI_PLL_CNTL0 0x0d8
58
+
#define HHI_HIFI_PLL_CNTL1 0x0dc
59
+
#define HHI_HIFI_PLL_CNTL2 0x0e0
60
+
#define HHI_HIFI_PLL_CNTL3 0x0e4
61
+
#define HHI_HIFI_PLL_CNTL4 0x0e8
62
+
#define HHI_HIFI_PLL_CNTL5 0x0ec
63
+
#define HHI_HIFI_PLL_CNTL6 0x0f0
64
+
#define HHI_VIID_CLK_DIV 0x128
65
+
#define HHI_VIID_CLK_CNTL 0x12c
66
+
#define HHI_GCLK_MPEG0 0x140
67
+
#define HHI_GCLK_MPEG1 0x144
68
+
#define HHI_GCLK_MPEG2 0x148
69
+
#define HHI_GCLK_OTHER 0x150
70
+
#define HHI_GCLK_OTHER2 0x154
71
+
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
72
+
#define HHI_VID_CLK_DIV 0x164
73
+
#define HHI_MPEG_CLK_CNTL 0x174
74
+
#define HHI_AUD_CLK_CNTL 0x178
75
+
#define HHI_VID_CLK_CNTL 0x17c
76
+
#define HHI_TS_CLK_CNTL 0x190
77
+
#define HHI_VID_CLK_CNTL2 0x194
78
+
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
79
+
#define HHI_VID_PLL_CLK_DIV 0x1a0
80
+
#define HHI_MALI_CLK_CNTL 0x1b0
81
+
#define HHI_VPU_CLKC_CNTL 0x1b4
82
+
#define HHI_VPU_CLK_CNTL 0x1bc
83
+
#define HHI_ISP_CLK_CNTL 0x1c0
84
+
#define HHI_NNA_CLK_CNTL 0x1c8
85
+
#define HHI_HDMI_CLK_CNTL 0x1cc
86
+
#define HHI_VDEC_CLK_CNTL 0x1e0
87
+
#define HHI_VDEC2_CLK_CNTL 0x1e4
88
+
#define HHI_VDEC3_CLK_CNTL 0x1e8
89
+
#define HHI_VDEC4_CLK_CNTL 0x1ec
90
+
#define HHI_HDCP22_CLK_CNTL 0x1f0
91
+
#define HHI_VAPBCLK_CNTL 0x1f4
92
+
#define HHI_SYS_CPUB_CLK_CNTL1 0x200
93
+
#define HHI_SYS_CPUB_CLK_CNTL 0x208
94
+
#define HHI_VPU_CLKB_CNTL 0x20c
95
+
#define HHI_SYS_CPU_CLK_CNTL2 0x210
96
+
#define HHI_SYS_CPU_CLK_CNTL3 0x214
97
+
#define HHI_SYS_CPU_CLK_CNTL4 0x218
98
+
#define HHI_SYS_CPU_CLK_CNTL5 0x21c
99
+
#define HHI_SYS_CPU_CLK_CNTL6 0x220
100
+
#define HHI_GEN_CLK_CNTL 0x228
101
+
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
102
+
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
103
+
#define HHI_NAND_CLK_CNTL 0x25c
104
+
#define HHI_SD_EMMC_CLK_CNTL 0x264
105
+
#define HHI_MPLL_CNTL0 0x278
106
+
#define HHI_MPLL_CNTL1 0x27c
107
+
#define HHI_MPLL_CNTL2 0x280
108
+
#define HHI_MPLL_CNTL3 0x284
109
+
#define HHI_MPLL_CNTL4 0x288
110
+
#define HHI_MPLL_CNTL5 0x28c
111
+
#define HHI_MPLL_CNTL6 0x290
112
+
#define HHI_MPLL_CNTL7 0x294
113
+
#define HHI_MPLL_CNTL8 0x298
114
+
#define HHI_FIX_PLL_CNTL0 0x2a0
115
+
#define HHI_FIX_PLL_CNTL1 0x2a4
116
+
#define HHI_FIX_PLL_CNTL3 0x2ac
117
+
#define HHI_SYS_PLL_CNTL0 0x2f4
118
+
#define HHI_SYS_PLL_CNTL1 0x2f8
119
+
#define HHI_SYS_PLL_CNTL2 0x2fc
120
+
#define HHI_SYS_PLL_CNTL3 0x300
121
+
#define HHI_SYS_PLL_CNTL4 0x304
122
+
#define HHI_SYS_PLL_CNTL5 0x308
123
+
#define HHI_SYS_PLL_CNTL6 0x30c
124
+
#define HHI_HDMI_PLL_CNTL0 0x320
125
+
#define HHI_HDMI_PLL_CNTL1 0x324
126
+
#define HHI_HDMI_PLL_CNTL2 0x328
127
+
#define HHI_HDMI_PLL_CNTL3 0x32c
128
+
#define HHI_HDMI_PLL_CNTL4 0x330
129
+
#define HHI_HDMI_PLL_CNTL5 0x334
130
+
#define HHI_HDMI_PLL_CNTL6 0x338
131
+
#define HHI_SPICC_CLK_CNTL 0x3dc
132
+
#define HHI_SYS1_PLL_CNTL0 0x380
133
+
#define HHI_SYS1_PLL_CNTL1 0x384
134
+
#define HHI_SYS1_PLL_CNTL2 0x388
135
+
#define HHI_SYS1_PLL_CNTL3 0x38c
136
+
#define HHI_SYS1_PLL_CNTL4 0x390
137
+
#define HHI_SYS1_PLL_CNTL5 0x394
138
+
#define HHI_SYS1_PLL_CNTL6 0x398
30
139
31
140
static struct clk_regmap g12a_fixed_pll_dco = {
32
141
.data = &(struct meson_clk_pll_data){
···
5235
5126
[CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
5236
5127
};
5237
5128
5238
-
/* Convenience table to populate regmap in .probe */
5239
-
static struct clk_regmap *const g12a_clk_regmaps[] = {
5240
-
&g12a_clk81,
5241
-
&g12a_dos,
5242
-
&g12a_ddr,
5243
-
&g12a_audio_locker,
5244
-
&g12a_mipi_dsi_host,
5245
-
&g12a_eth_phy,
5246
-
&g12a_isa,
5247
-
&g12a_pl301,
5248
-
&g12a_periphs,
5249
-
&g12a_spicc_0,
5250
-
&g12a_i2c,
5251
-
&g12a_sana,
5252
-
&g12a_sd,
5253
-
&g12a_rng0,
5254
-
&g12a_uart0,
5255
-
&g12a_spicc_1,
5256
-
&g12a_hiu_reg,
5257
-
&g12a_mipi_dsi_phy,
5258
-
&g12a_assist_misc,
5259
-
&g12a_emmc_a,
5260
-
&g12a_emmc_b,
5261
-
&g12a_emmc_c,
5262
-
&g12a_audio_codec,
5263
-
&g12a_audio,
5264
-
&g12a_eth_core,
5265
-
&g12a_demux,
5266
-
&g12a_audio_ififo,
5267
-
&g12a_adc,
5268
-
&g12a_uart1,
5269
-
&g12a_g2d,
5270
-
&g12a_reset,
5271
-
&g12a_pcie_comb,
5272
-
&g12a_parser,
5273
-
&g12a_usb_general,
5274
-
&g12a_pcie_phy,
5275
-
&g12a_ahb_arb0,
5276
-
&g12a_ahb_data_bus,
5277
-
&g12a_ahb_ctrl_bus,
5278
-
&g12a_htx_hdcp22,
5279
-
&g12a_htx_pclk,
5280
-
&g12a_bt656,
5281
-
&g12a_usb1_to_ddr,
5282
-
&g12a_mmc_pclk,
5283
-
&g12a_uart2,
5284
-
&g12a_vpu_intr,
5285
-
&g12a_gic,
5286
-
&g12a_sd_emmc_a_clk0,
5287
-
&g12a_sd_emmc_b_clk0,
5288
-
&g12a_sd_emmc_c_clk0,
5289
-
&g12a_mpeg_clk_div,
5290
-
&g12a_sd_emmc_a_clk0_div,
5291
-
&g12a_sd_emmc_b_clk0_div,
5292
-
&g12a_sd_emmc_c_clk0_div,
5293
-
&g12a_mpeg_clk_sel,
5294
-
&g12a_sd_emmc_a_clk0_sel,
5295
-
&g12a_sd_emmc_b_clk0_sel,
5296
-
&g12a_sd_emmc_c_clk0_sel,
5297
-
&g12a_mpll0,
5298
-
&g12a_mpll1,
5299
-
&g12a_mpll2,
5300
-
&g12a_mpll3,
5301
-
&g12a_mpll0_div,
5302
-
&g12a_mpll1_div,
5303
-
&g12a_mpll2_div,
5304
-
&g12a_mpll3_div,
5305
-
&g12a_fixed_pll,
5306
-
&g12a_sys_pll,
5307
-
&g12a_gp0_pll,
5308
-
&g12a_hifi_pll,
5309
-
&g12a_vclk2_venci0,
5310
-
&g12a_vclk2_venci1,
5311
-
&g12a_vclk2_vencp0,
5312
-
&g12a_vclk2_vencp1,
5313
-
&g12a_vclk2_venct0,
5314
-
&g12a_vclk2_venct1,
5315
-
&g12a_vclk2_other,
5316
-
&g12a_vclk2_enci,
5317
-
&g12a_vclk2_encp,
5318
-
&g12a_dac_clk,
5319
-
&g12a_aoclk_gate,
5320
-
&g12a_iec958_gate,
5321
-
&g12a_enc480p,
5322
-
&g12a_rng1,
5323
-
&g12a_vclk2_enct,
5324
-
&g12a_vclk2_encl,
5325
-
&g12a_vclk2_venclmmc,
5326
-
&g12a_vclk2_vencl,
5327
-
&g12a_vclk2_other1,
5328
-
&g12a_fixed_pll_dco,
5329
-
&g12a_sys_pll_dco,
5330
-
&g12a_gp0_pll_dco,
5331
-
&g12a_hifi_pll_dco,
5332
-
&g12a_fclk_div2,
5333
-
&g12a_fclk_div3,
5334
-
&g12a_fclk_div4,
5335
-
&g12a_fclk_div5,
5336
-
&g12a_fclk_div7,
5337
-
&g12a_fclk_div2p5,
5338
-
&g12a_dma,
5339
-
&g12a_efuse,
5340
-
&g12a_rom_boot,
5341
-
&g12a_reset_sec,
5342
-
&g12a_sec_ahb_apb3,
5343
-
&g12a_vpu_0_sel,
5344
-
&g12a_vpu_0_div,
5345
-
&g12a_vpu_0,
5346
-
&g12a_vpu_1_sel,
5347
-
&g12a_vpu_1_div,
5348
-
&g12a_vpu_1,
5349
-
&g12a_vpu,
5350
-
&g12a_vapb_0_sel,
5351
-
&g12a_vapb_0_div,
5352
-
&g12a_vapb_0,
5353
-
&g12a_vapb_1_sel,
5354
-
&g12a_vapb_1_div,
5355
-
&g12a_vapb_1,
5356
-
&g12a_vapb_sel,
5357
-
&g12a_vapb,
5358
-
&g12a_hdmi_pll_dco,
5359
-
&g12a_hdmi_pll_od,
5360
-
&g12a_hdmi_pll_od2,
5361
-
&g12a_hdmi_pll,
5362
-
&g12a_vid_pll_div,
5363
-
&g12a_vid_pll_sel,
5364
-
&g12a_vid_pll,
5365
-
&g12a_vclk_sel,
5366
-
&g12a_vclk2_sel,
5367
-
&g12a_vclk_input,
5368
-
&g12a_vclk2_input,
5369
-
&g12a_vclk_div,
5370
-
&g12a_vclk2_div,
5371
-
&g12a_vclk,
5372
-
&g12a_vclk2,
5373
-
&g12a_vclk_div1,
5374
-
&g12a_vclk_div2_en,
5375
-
&g12a_vclk_div4_en,
5376
-
&g12a_vclk_div6_en,
5377
-
&g12a_vclk_div12_en,
5378
-
&g12a_vclk2_div1,
5379
-
&g12a_vclk2_div2_en,
5380
-
&g12a_vclk2_div4_en,
5381
-
&g12a_vclk2_div6_en,
5382
-
&g12a_vclk2_div12_en,
5383
-
&g12a_cts_enci_sel,
5384
-
&g12a_cts_encp_sel,
5385
-
&g12a_cts_encl_sel,
5386
-
&g12a_cts_vdac_sel,
5387
-
&g12a_hdmi_tx_sel,
5388
-
&g12a_cts_enci,
5389
-
&g12a_cts_encp,
5390
-
&g12a_cts_encl,
5391
-
&g12a_cts_vdac,
5392
-
&g12a_hdmi_tx,
5393
-
&g12a_hdmi_sel,
5394
-
&g12a_hdmi_div,
5395
-
&g12a_hdmi,
5396
-
&g12a_mali_0_sel,
5397
-
&g12a_mali_0_div,
5398
-
&g12a_mali_0,
5399
-
&g12a_mali_1_sel,
5400
-
&g12a_mali_1_div,
5401
-
&g12a_mali_1,
5402
-
&g12a_mali,
5403
-
&g12a_mpll_50m,
5404
-
&g12a_sys_pll_div16_en,
5405
-
&g12a_cpu_clk_premux0,
5406
-
&g12a_cpu_clk_mux0_div,
5407
-
&g12a_cpu_clk_postmux0,
5408
-
&g12a_cpu_clk_premux1,
5409
-
&g12a_cpu_clk_mux1_div,
5410
-
&g12a_cpu_clk_postmux1,
5411
-
&g12a_cpu_clk_dyn,
5412
-
&g12a_cpu_clk,
5413
-
&g12a_cpu_clk_div16_en,
5414
-
&g12a_cpu_clk_apb_div,
5415
-
&g12a_cpu_clk_apb,
5416
-
&g12a_cpu_clk_atb_div,
5417
-
&g12a_cpu_clk_atb,
5418
-
&g12a_cpu_clk_axi_div,
5419
-
&g12a_cpu_clk_axi,
5420
-
&g12a_cpu_clk_trace_div,
5421
-
&g12a_cpu_clk_trace,
5422
-
&g12a_pcie_pll_od,
5423
-
&g12a_pcie_pll_dco,
5424
-
&g12a_vdec_1_sel,
5425
-
&g12a_vdec_1_div,
5426
-
&g12a_vdec_1,
5427
-
&g12a_vdec_hevc_sel,
5428
-
&g12a_vdec_hevc_div,
5429
-
&g12a_vdec_hevc,
5430
-
&g12a_vdec_hevcf_sel,
5431
-
&g12a_vdec_hevcf_div,
5432
-
&g12a_vdec_hevcf,
5433
-
&g12a_ts_div,
5434
-
&g12a_ts,
5435
-
&g12b_cpu_clk,
5436
-
&g12b_sys1_pll_dco,
5437
-
&g12b_sys1_pll,
5438
-
&g12b_sys1_pll_div16_en,
5439
-
&g12b_cpub_clk_premux0,
5440
-
&g12b_cpub_clk_mux0_div,
5441
-
&g12b_cpub_clk_postmux0,
5442
-
&g12b_cpub_clk_premux1,
5443
-
&g12b_cpub_clk_mux1_div,
5444
-
&g12b_cpub_clk_postmux1,
5445
-
&g12b_cpub_clk_dyn,
5446
-
&g12b_cpub_clk,
5447
-
&g12b_cpub_clk_div16_en,
5448
-
&g12b_cpub_clk_apb_sel,
5449
-
&g12b_cpub_clk_apb,
5450
-
&g12b_cpub_clk_atb_sel,
5451
-
&g12b_cpub_clk_atb,
5452
-
&g12b_cpub_clk_axi_sel,
5453
-
&g12b_cpub_clk_axi,
5454
-
&g12b_cpub_clk_trace_sel,
5455
-
&g12b_cpub_clk_trace,
5456
-
&sm1_gp1_pll_dco,
5457
-
&sm1_gp1_pll,
5458
-
&sm1_dsu_clk_premux0,
5459
-
&sm1_dsu_clk_premux1,
5460
-
&sm1_dsu_clk_mux0_div,
5461
-
&sm1_dsu_clk_postmux0,
5462
-
&sm1_dsu_clk_mux1_div,
5463
-
&sm1_dsu_clk_postmux1,
5464
-
&sm1_dsu_clk_dyn,
5465
-
&sm1_dsu_final_clk,
5466
-
&sm1_dsu_clk,
5467
-
&sm1_cpu1_clk,
5468
-
&sm1_cpu2_clk,
5469
-
&sm1_cpu3_clk,
5470
-
&g12a_spicc0_sclk_sel,
5471
-
&g12a_spicc0_sclk_div,
5472
-
&g12a_spicc0_sclk,
5473
-
&g12a_spicc1_sclk_sel,
5474
-
&g12a_spicc1_sclk_div,
5475
-
&g12a_spicc1_sclk,
5476
-
&sm1_nna_axi_clk_sel,
5477
-
&sm1_nna_axi_clk_div,
5478
-
&sm1_nna_axi_clk,
5479
-
&sm1_nna_core_clk_sel,
5480
-
&sm1_nna_core_clk_div,
5481
-
&sm1_nna_core_clk,
5482
-
&g12a_mipi_dsi_pxclk_sel,
5483
-
&g12a_mipi_dsi_pxclk_div,
5484
-
&g12a_mipi_dsi_pxclk,
5485
-
&g12b_mipi_isp_sel,
5486
-
&g12b_mipi_isp_div,
5487
-
&g12b_mipi_isp,
5488
-
&g12b_mipi_isp_gate,
5489
-
&g12b_csi_phy1,
5490
-
&g12b_csi_phy0,
5491
-
};
5492
-
5493
5129
static const struct reg_sequence g12a_init_regs[] = {
5494
5130
{ .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
5495
5131
};
···
5413
5559
5414
5560
static const struct meson_g12a_data g12a_clkc_data = {
5415
5561
.eeclkc_data = {
5416
-
.regmap_clks = g12a_clk_regmaps,
5417
-
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5418
5562
.hw_clks = {
5419
5563
.hws = g12a_hw_clks,
5420
5564
.num = ARRAY_SIZE(g12a_hw_clks),
···
5425
5573
5426
5574
static const struct meson_g12a_data g12b_clkc_data = {
5427
5575
.eeclkc_data = {
5428
-
.regmap_clks = g12a_clk_regmaps,
5429
-
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5430
5576
.hw_clks = {
5431
5577
.hws = g12b_hw_clks,
5432
5578
.num = ARRAY_SIZE(g12b_hw_clks),
···
5435
5585
5436
5586
static const struct meson_g12a_data sm1_clkc_data = {
5437
5587
.eeclkc_data = {
5438
-
.regmap_clks = g12a_clk_regmaps,
5439
-
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5440
5588
.hw_clks = {
5441
5589
.hws = sm1_hw_clks,
5442
5590
.num = ARRAY_SIZE(sm1_hw_clks),
-130
drivers/clk/meson/g12a.h
-130
drivers/clk/meson/g12a.h
···
1
-
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2
-
/*
3
-
* Copyright (c) 2016 Amlogic, Inc.
4
-
* Author: Michael Turquette <mturquette@baylibre.com>
5
-
*
6
-
* Copyright (c) 2018 Amlogic, inc.
7
-
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
8
-
* Author: Jian Hu <jian.hu@amlogic.com>
9
-
*
10
-
*/
11
-
#ifndef __G12A_H
12
-
#define __G12A_H
13
-
14
-
/*
15
-
* Clock controller register offsets
16
-
*
17
-
* Register offsets from the data sheet must be multiplied by 4 before
18
-
* adding them to the base address to get the right value.
19
-
*/
20
-
#define HHI_MIPI_CNTL0 0x000
21
-
#define HHI_MIPI_CNTL1 0x004
22
-
#define HHI_MIPI_CNTL2 0x008
23
-
#define HHI_MIPI_STS 0x00C
24
-
#define HHI_GP0_PLL_CNTL0 0x040
25
-
#define HHI_GP0_PLL_CNTL1 0x044
26
-
#define HHI_GP0_PLL_CNTL2 0x048
27
-
#define HHI_GP0_PLL_CNTL3 0x04C
28
-
#define HHI_GP0_PLL_CNTL4 0x050
29
-
#define HHI_GP0_PLL_CNTL5 0x054
30
-
#define HHI_GP0_PLL_CNTL6 0x058
31
-
#define HHI_GP0_PLL_STS 0x05C
32
-
#define HHI_GP1_PLL_CNTL0 0x060
33
-
#define HHI_GP1_PLL_CNTL1 0x064
34
-
#define HHI_GP1_PLL_CNTL2 0x068
35
-
#define HHI_GP1_PLL_CNTL3 0x06C
36
-
#define HHI_GP1_PLL_CNTL4 0x070
37
-
#define HHI_GP1_PLL_CNTL5 0x074
38
-
#define HHI_GP1_PLL_CNTL6 0x078
39
-
#define HHI_GP1_PLL_STS 0x07C
40
-
#define HHI_PCIE_PLL_CNTL0 0x098
41
-
#define HHI_PCIE_PLL_CNTL1 0x09C
42
-
#define HHI_PCIE_PLL_CNTL2 0x0A0
43
-
#define HHI_PCIE_PLL_CNTL3 0x0A4
44
-
#define HHI_PCIE_PLL_CNTL4 0x0A8
45
-
#define HHI_PCIE_PLL_CNTL5 0x0AC
46
-
#define HHI_PCIE_PLL_STS 0x0B8
47
-
#define HHI_HIFI_PLL_CNTL0 0x0D8
48
-
#define HHI_HIFI_PLL_CNTL1 0x0DC
49
-
#define HHI_HIFI_PLL_CNTL2 0x0E0
50
-
#define HHI_HIFI_PLL_CNTL3 0x0E4
51
-
#define HHI_HIFI_PLL_CNTL4 0x0E8
52
-
#define HHI_HIFI_PLL_CNTL5 0x0EC
53
-
#define HHI_HIFI_PLL_CNTL6 0x0F0
54
-
#define HHI_VIID_CLK_DIV 0x128
55
-
#define HHI_VIID_CLK_CNTL 0x12C
56
-
#define HHI_GCLK_MPEG0 0x140
57
-
#define HHI_GCLK_MPEG1 0x144
58
-
#define HHI_GCLK_MPEG2 0x148
59
-
#define HHI_GCLK_OTHER 0x150
60
-
#define HHI_GCLK_OTHER2 0x154
61
-
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
62
-
#define HHI_VID_CLK_DIV 0x164
63
-
#define HHI_MPEG_CLK_CNTL 0x174
64
-
#define HHI_AUD_CLK_CNTL 0x178
65
-
#define HHI_VID_CLK_CNTL 0x17c
66
-
#define HHI_TS_CLK_CNTL 0x190
67
-
#define HHI_VID_CLK_CNTL2 0x194
68
-
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
69
-
#define HHI_VID_PLL_CLK_DIV 0x1A0
70
-
#define HHI_MALI_CLK_CNTL 0x1b0
71
-
#define HHI_VPU_CLKC_CNTL 0x1b4
72
-
#define HHI_VPU_CLK_CNTL 0x1bC
73
-
#define HHI_ISP_CLK_CNTL 0x1C0
74
-
#define HHI_NNA_CLK_CNTL 0x1C8
75
-
#define HHI_HDMI_CLK_CNTL 0x1CC
76
-
#define HHI_VDEC_CLK_CNTL 0x1E0
77
-
#define HHI_VDEC2_CLK_CNTL 0x1E4
78
-
#define HHI_VDEC3_CLK_CNTL 0x1E8
79
-
#define HHI_VDEC4_CLK_CNTL 0x1EC
80
-
#define HHI_HDCP22_CLK_CNTL 0x1F0
81
-
#define HHI_VAPBCLK_CNTL 0x1F4
82
-
#define HHI_SYS_CPUB_CLK_CNTL1 0x200
83
-
#define HHI_SYS_CPUB_CLK_CNTL 0x208
84
-
#define HHI_VPU_CLKB_CNTL 0x20C
85
-
#define HHI_SYS_CPU_CLK_CNTL2 0x210
86
-
#define HHI_SYS_CPU_CLK_CNTL3 0x214
87
-
#define HHI_SYS_CPU_CLK_CNTL4 0x218
88
-
#define HHI_SYS_CPU_CLK_CNTL5 0x21c
89
-
#define HHI_SYS_CPU_CLK_CNTL6 0x220
90
-
#define HHI_GEN_CLK_CNTL 0x228
91
-
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
92
-
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
93
-
#define HHI_NAND_CLK_CNTL 0x25C
94
-
#define HHI_SD_EMMC_CLK_CNTL 0x264
95
-
#define HHI_MPLL_CNTL0 0x278
96
-
#define HHI_MPLL_CNTL1 0x27C
97
-
#define HHI_MPLL_CNTL2 0x280
98
-
#define HHI_MPLL_CNTL3 0x284
99
-
#define HHI_MPLL_CNTL4 0x288
100
-
#define HHI_MPLL_CNTL5 0x28c
101
-
#define HHI_MPLL_CNTL6 0x290
102
-
#define HHI_MPLL_CNTL7 0x294
103
-
#define HHI_MPLL_CNTL8 0x298
104
-
#define HHI_FIX_PLL_CNTL0 0x2A0
105
-
#define HHI_FIX_PLL_CNTL1 0x2A4
106
-
#define HHI_FIX_PLL_CNTL3 0x2AC
107
-
#define HHI_SYS_PLL_CNTL0 0x2f4
108
-
#define HHI_SYS_PLL_CNTL1 0x2f8
109
-
#define HHI_SYS_PLL_CNTL2 0x2fc
110
-
#define HHI_SYS_PLL_CNTL3 0x300
111
-
#define HHI_SYS_PLL_CNTL4 0x304
112
-
#define HHI_SYS_PLL_CNTL5 0x308
113
-
#define HHI_SYS_PLL_CNTL6 0x30c
114
-
#define HHI_HDMI_PLL_CNTL0 0x320
115
-
#define HHI_HDMI_PLL_CNTL1 0x324
116
-
#define HHI_HDMI_PLL_CNTL2 0x328
117
-
#define HHI_HDMI_PLL_CNTL3 0x32c
118
-
#define HHI_HDMI_PLL_CNTL4 0x330
119
-
#define HHI_HDMI_PLL_CNTL5 0x334
120
-
#define HHI_HDMI_PLL_CNTL6 0x338
121
-
#define HHI_SPICC_CLK_CNTL 0x3dc
122
-
#define HHI_SYS1_PLL_CNTL0 0x380
123
-
#define HHI_SYS1_PLL_CNTL1 0x384
124
-
#define HHI_SYS1_PLL_CNTL2 0x388
125
-
#define HHI_SYS1_PLL_CNTL3 0x38c
126
-
#define HHI_SYS1_PLL_CNTL4 0x390
127
-
#define HHI_SYS1_PLL_CNTL5 0x394
128
-
#define HHI_SYS1_PLL_CNTL6 0x398
129
-
130
-
#endif /* __G12A_H */
-19
drivers/clk/meson/gxbb-aoclk.c
-19
drivers/clk/meson/gxbb-aoclk.c
···
237
237
[RESET_AO_IR_BLASTER] = 23,
238
238
};
239
239
240
-
static struct clk_regmap *gxbb_aoclk[] = {
241
-
&remote_ao,
242
-
&i2c_master_ao,
243
-
&i2c_slave_ao,
244
-
&uart1_ao,
245
-
&uart2_ao,
246
-
&ir_blaster_ao,
247
-
&ao_cts_oscin,
248
-
&ao_32k_pre,
249
-
&ao_32k_div,
250
-
&ao_32k_sel,
251
-
&ao_32k,
252
-
&ao_cts_rtc_oscin,
253
-
&ao_clk81,
254
-
&ao_cts_cec,
255
-
};
256
-
257
240
static struct clk_hw *gxbb_aoclk_hw_clks[] = {
258
241
[CLKID_AO_REMOTE] = &remote_ao.hw,
259
242
[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
···
258
275
.reset_reg = AO_RTI_GEN_CNTL_REG0,
259
276
.num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
260
277
.reset = gxbb_aoclk_reset,
261
-
.num_clks = ARRAY_SIZE(gxbb_aoclk),
262
-
.clks = gxbb_aoclk,
263
278
.hw_clks = {
264
279
.hws = gxbb_aoclk_hw_clks,
265
280
.num = ARRAY_SIZE(gxbb_aoclk_hw_clks),
+98
-394
drivers/clk/meson/gxbb.c
+98
-394
drivers/clk/meson/gxbb.c
···
10
10
#include <linux/platform_device.h>
11
11
#include <linux/module.h>
12
12
13
-
#include "gxbb.h"
14
13
#include "clk-regmap.h"
15
14
#include "clk-pll.h"
16
15
#include "clk-mpll.h"
···
17
18
#include "vid-pll-div.h"
18
19
19
20
#include <dt-bindings/clock/gxbb-clkc.h>
21
+
22
+
#define SCR 0x2c
23
+
#define TIMEOUT_VALUE 0x3c
24
+
25
+
#define HHI_GP0_PLL_CNTL 0x40
26
+
#define HHI_GP0_PLL_CNTL2 0x44
27
+
#define HHI_GP0_PLL_CNTL3 0x48
28
+
#define HHI_GP0_PLL_CNTL4 0x4c
29
+
#define HHI_GP0_PLL_CNTL5 0x50
30
+
#define HHI_GP0_PLL_CNTL1 0x58
31
+
32
+
#define HHI_XTAL_DIVN_CNTL 0xbc
33
+
#define HHI_TIMER90K 0xec
34
+
35
+
#define HHI_MEM_PD_REG0 0x100
36
+
#define HHI_MEM_PD_REG1 0x104
37
+
#define HHI_VPU_MEM_PD_REG1 0x108
38
+
#define HHI_VIID_CLK_DIV 0x128
39
+
#define HHI_VIID_CLK_CNTL 0x12c
40
+
41
+
#define HHI_GCLK_MPEG0 0x140
42
+
#define HHI_GCLK_MPEG1 0x144
43
+
#define HHI_GCLK_MPEG2 0x148
44
+
#define HHI_GCLK_OTHER 0x150
45
+
#define HHI_GCLK_AO 0x154
46
+
#define HHI_SYS_OSCIN_CNTL 0x158
47
+
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
48
+
#define HHI_SYS_CPU_RESET_CNTL 0x160
49
+
#define HHI_VID_CLK_DIV 0x164
50
+
51
+
#define HHI_MPEG_CLK_CNTL 0x174
52
+
#define HHI_AUD_CLK_CNTL 0x178
53
+
#define HHI_VID_CLK_CNTL 0x17c
54
+
#define HHI_AUD_CLK_CNTL2 0x190
55
+
#define HHI_VID_CLK_CNTL2 0x194
56
+
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
57
+
#define HHI_VID_PLL_CLK_DIV 0x1a0
58
+
#define HHI_AUD_CLK_CNTL3 0x1a4
59
+
#define HHI_MALI_CLK_CNTL 0x1b0
60
+
#define HHI_VPU_CLK_CNTL 0x1bc
61
+
62
+
#define HHI_HDMI_CLK_CNTL 0x1cc
63
+
#define HHI_VDEC_CLK_CNTL 0x1e0
64
+
#define HHI_VDEC2_CLK_CNTL 0x1e4
65
+
#define HHI_VDEC3_CLK_CNTL 0x1e8
66
+
#define HHI_VDEC4_CLK_CNTL 0x1ec
67
+
#define HHI_HDCP22_CLK_CNTL 0x1f0
68
+
#define HHI_VAPBCLK_CNTL 0x1f4
69
+
70
+
#define HHI_VPU_CLKB_CNTL 0x20c
71
+
#define HHI_USB_CLK_CNTL 0x220
72
+
#define HHI_32K_CLK_CNTL 0x224
73
+
#define HHI_GEN_CLK_CNTL 0x228
74
+
75
+
#define HHI_PCM_CLK_CNTL 0x258
76
+
#define HHI_NAND_CLK_CNTL 0x25c
77
+
#define HHI_SD_EMMC_CLK_CNTL 0x264
78
+
79
+
#define HHI_MPLL_CNTL 0x280
80
+
#define HHI_MPLL_CNTL2 0x284
81
+
#define HHI_MPLL_CNTL3 0x288
82
+
#define HHI_MPLL_CNTL4 0x28c
83
+
#define HHI_MPLL_CNTL5 0x290
84
+
#define HHI_MPLL_CNTL6 0x294
85
+
#define HHI_MPLL_CNTL7 0x298
86
+
#define HHI_MPLL_CNTL8 0x29c
87
+
#define HHI_MPLL_CNTL9 0x2a0
88
+
#define HHI_MPLL_CNTL10 0x2a4
89
+
90
+
#define HHI_MPLL3_CNTL0 0x2e0
91
+
#define HHI_MPLL3_CNTL1 0x2e4
92
+
#define HHI_VDAC_CNTL0 0x2f4
93
+
#define HHI_VDAC_CNTL1 0x2f8
94
+
95
+
#define HHI_SYS_PLL_CNTL 0x300
96
+
#define HHI_SYS_PLL_CNTL2 0x304
97
+
#define HHI_SYS_PLL_CNTL3 0x308
98
+
#define HHI_SYS_PLL_CNTL4 0x30c
99
+
#define HHI_SYS_PLL_CNTL5 0x310
100
+
#define HHI_DPLL_TOP_I 0x318
101
+
#define HHI_DPLL_TOP2_I 0x31c
102
+
#define HHI_HDMI_PLL_CNTL 0x320
103
+
#define HHI_HDMI_PLL_CNTL2 0x324
104
+
#define HHI_HDMI_PLL_CNTL3 0x328
105
+
#define HHI_HDMI_PLL_CNTL4 0x32c
106
+
#define HHI_HDMI_PLL_CNTL5 0x330
107
+
#define HHI_HDMI_PLL_CNTL6 0x334
108
+
#define HHI_HDMI_PLL_CNTL_I 0x338
109
+
#define HHI_HDMI_PLL_CNTL7 0x33c
110
+
111
+
#define HHI_HDMI_PHY_CNTL0 0x3a0
112
+
#define HHI_HDMI_PHY_CNTL1 0x3a4
113
+
#define HHI_HDMI_PHY_CNTL2 0x3a8
114
+
#define HHI_HDMI_PHY_CNTL3 0x3ac
115
+
116
+
#define HHI_VID_LOCK_CLK_CNTL 0x3c8
117
+
#define HHI_BT656_CLK_CNTL 0x3d4
118
+
#define HHI_SAR_CLK_CNTL 0x3d8
20
119
21
120
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
22
121
PLL_PARAMS(32, 1),
···
3237
3140
[CLKID_ACODEC] = &gxl_acodec.hw,
3238
3141
};
3239
3142
3240
-
static struct clk_regmap *const gxbb_clk_regmaps[] = {
3241
-
&gxbb_clk81,
3242
-
&gxbb_ddr,
3243
-
&gxbb_dos,
3244
-
&gxbb_isa,
3245
-
&gxbb_pl301,
3246
-
&gxbb_periphs,
3247
-
&gxbb_spicc,
3248
-
&gxbb_i2c,
3249
-
&gxbb_sar_adc,
3250
-
&gxbb_smart_card,
3251
-
&gxbb_rng0,
3252
-
&gxbb_uart0,
3253
-
&gxbb_sdhc,
3254
-
&gxbb_stream,
3255
-
&gxbb_async_fifo,
3256
-
&gxbb_sdio,
3257
-
&gxbb_abuf,
3258
-
&gxbb_hiu_iface,
3259
-
&gxbb_assist_misc,
3260
-
&gxbb_spi,
3261
-
&gxbb_i2s_spdif,
3262
-
&gxbb_eth,
3263
-
&gxbb_demux,
3264
-
&gxbb_aiu_glue,
3265
-
&gxbb_iec958,
3266
-
&gxbb_i2s_out,
3267
-
&gxbb_amclk,
3268
-
&gxbb_aififo2,
3269
-
&gxbb_mixer,
3270
-
&gxbb_mixer_iface,
3271
-
&gxbb_adc,
3272
-
&gxbb_blkmv,
3273
-
&gxbb_aiu,
3274
-
&gxbb_uart1,
3275
-
&gxbb_g2d,
3276
-
&gxbb_usb0,
3277
-
&gxbb_usb1,
3278
-
&gxbb_reset,
3279
-
&gxbb_nand,
3280
-
&gxbb_dos_parser,
3281
-
&gxbb_usb,
3282
-
&gxbb_vdin1,
3283
-
&gxbb_ahb_arb0,
3284
-
&gxbb_efuse,
3285
-
&gxbb_boot_rom,
3286
-
&gxbb_ahb_data_bus,
3287
-
&gxbb_ahb_ctrl_bus,
3288
-
&gxbb_hdmi_intr_sync,
3289
-
&gxbb_hdmi_pclk,
3290
-
&gxbb_usb1_ddr_bridge,
3291
-
&gxbb_usb0_ddr_bridge,
3292
-
&gxbb_mmc_pclk,
3293
-
&gxbb_dvin,
3294
-
&gxbb_uart2,
3295
-
&gxbb_sana,
3296
-
&gxbb_vpu_intr,
3297
-
&gxbb_sec_ahb_ahb3_bridge,
3298
-
&gxbb_clk81_a53,
3299
-
&gxbb_vclk2_venci0,
3300
-
&gxbb_vclk2_venci1,
3301
-
&gxbb_vclk2_vencp0,
3302
-
&gxbb_vclk2_vencp1,
3303
-
&gxbb_gclk_venci_int0,
3304
-
&gxbb_gclk_vencp_int,
3305
-
&gxbb_dac_clk,
3306
-
&gxbb_aoclk_gate,
3307
-
&gxbb_iec958_gate,
3308
-
&gxbb_enc480p,
3309
-
&gxbb_rng1,
3310
-
&gxbb_gclk_venci_int1,
3311
-
&gxbb_vclk2_venclmcc,
3312
-
&gxbb_vclk2_vencl,
3313
-
&gxbb_vclk_other,
3314
-
&gxbb_edp,
3315
-
&gxbb_ao_media_cpu,
3316
-
&gxbb_ao_ahb_sram,
3317
-
&gxbb_ao_ahb_bus,
3318
-
&gxbb_ao_iface,
3319
-
&gxbb_ao_i2c,
3320
-
&gxbb_emmc_a,
3321
-
&gxbb_emmc_b,
3322
-
&gxbb_emmc_c,
3323
-
&gxbb_sar_adc_clk,
3324
-
&gxbb_mali_0,
3325
-
&gxbb_mali_1,
3326
-
&gxbb_cts_amclk,
3327
-
&gxbb_cts_mclk_i958,
3328
-
&gxbb_32k_clk,
3329
-
&gxbb_sd_emmc_a_clk0,
3330
-
&gxbb_sd_emmc_b_clk0,
3331
-
&gxbb_sd_emmc_c_clk0,
3332
-
&gxbb_vpu_0,
3333
-
&gxbb_vpu_1,
3334
-
&gxbb_vapb_0,
3335
-
&gxbb_vapb_1,
3336
-
&gxbb_vapb,
3337
-
&gxbb_mpeg_clk_div,
3338
-
&gxbb_sar_adc_clk_div,
3339
-
&gxbb_mali_0_div,
3340
-
&gxbb_mali_1_div,
3341
-
&gxbb_cts_mclk_i958_div,
3342
-
&gxbb_32k_clk_div,
3343
-
&gxbb_sd_emmc_a_clk0_div,
3344
-
&gxbb_sd_emmc_b_clk0_div,
3345
-
&gxbb_sd_emmc_c_clk0_div,
3346
-
&gxbb_vpu_0_div,
3347
-
&gxbb_vpu_1_div,
3348
-
&gxbb_vapb_0_div,
3349
-
&gxbb_vapb_1_div,
3350
-
&gxbb_mpeg_clk_sel,
3351
-
&gxbb_sar_adc_clk_sel,
3352
-
&gxbb_mali_0_sel,
3353
-
&gxbb_mali_1_sel,
3354
-
&gxbb_mali,
3355
-
&gxbb_cts_amclk_sel,
3356
-
&gxbb_cts_mclk_i958_sel,
3357
-
&gxbb_cts_i958,
3358
-
&gxbb_32k_clk_sel,
3359
-
&gxbb_sd_emmc_a_clk0_sel,
3360
-
&gxbb_sd_emmc_b_clk0_sel,
3361
-
&gxbb_sd_emmc_c_clk0_sel,
3362
-
&gxbb_vpu_0_sel,
3363
-
&gxbb_vpu_1_sel,
3364
-
&gxbb_vpu,
3365
-
&gxbb_vapb_0_sel,
3366
-
&gxbb_vapb_1_sel,
3367
-
&gxbb_vapb_sel,
3368
-
&gxbb_mpll0,
3369
-
&gxbb_mpll1,
3370
-
&gxbb_mpll2,
3371
-
&gxbb_mpll0_div,
3372
-
&gxbb_mpll1_div,
3373
-
&gxbb_mpll2_div,
3374
-
&gxbb_cts_amclk_div,
3375
-
&gxbb_fixed_pll,
3376
-
&gxbb_sys_pll,
3377
-
&gxbb_mpll_prediv,
3378
-
&gxbb_fclk_div2,
3379
-
&gxbb_fclk_div3,
3380
-
&gxbb_fclk_div4,
3381
-
&gxbb_fclk_div5,
3382
-
&gxbb_fclk_div7,
3383
-
&gxbb_vdec_1_sel,
3384
-
&gxbb_vdec_1_div,
3385
-
&gxbb_vdec_1,
3386
-
&gxbb_vdec_hevc_sel,
3387
-
&gxbb_vdec_hevc_div,
3388
-
&gxbb_vdec_hevc,
3389
-
&gxbb_gen_clk_sel,
3390
-
&gxbb_gen_clk_div,
3391
-
&gxbb_gen_clk,
3392
-
&gxbb_fixed_pll_dco,
3393
-
&gxbb_sys_pll_dco,
3394
-
&gxbb_gp0_pll,
3395
-
&gxbb_vid_pll,
3396
-
&gxbb_vid_pll_sel,
3397
-
&gxbb_vid_pll_div,
3398
-
&gxbb_vclk,
3399
-
&gxbb_vclk_sel,
3400
-
&gxbb_vclk_div,
3401
-
&gxbb_vclk_input,
3402
-
&gxbb_vclk_div1,
3403
-
&gxbb_vclk_div2_en,
3404
-
&gxbb_vclk_div4_en,
3405
-
&gxbb_vclk_div6_en,
3406
-
&gxbb_vclk_div12_en,
3407
-
&gxbb_vclk2,
3408
-
&gxbb_vclk2_sel,
3409
-
&gxbb_vclk2_div,
3410
-
&gxbb_vclk2_input,
3411
-
&gxbb_vclk2_div1,
3412
-
&gxbb_vclk2_div2_en,
3413
-
&gxbb_vclk2_div4_en,
3414
-
&gxbb_vclk2_div6_en,
3415
-
&gxbb_vclk2_div12_en,
3416
-
&gxbb_cts_enci,
3417
-
&gxbb_cts_enci_sel,
3418
-
&gxbb_cts_encp,
3419
-
&gxbb_cts_encp_sel,
3420
-
&gxbb_cts_vdac,
3421
-
&gxbb_cts_vdac_sel,
3422
-
&gxbb_hdmi_tx,
3423
-
&gxbb_hdmi_tx_sel,
3424
-
&gxbb_hdmi_sel,
3425
-
&gxbb_hdmi_div,
3426
-
&gxbb_hdmi,
3427
-
&gxbb_gp0_pll_dco,
3428
-
&gxbb_hdmi_pll,
3429
-
&gxbb_hdmi_pll_od,
3430
-
&gxbb_hdmi_pll_od2,
3431
-
&gxbb_hdmi_pll_dco,
3432
-
};
3433
-
3434
-
static struct clk_regmap *const gxl_clk_regmaps[] = {
3435
-
&gxbb_clk81,
3436
-
&gxbb_ddr,
3437
-
&gxbb_dos,
3438
-
&gxbb_isa,
3439
-
&gxbb_pl301,
3440
-
&gxbb_periphs,
3441
-
&gxbb_spicc,
3442
-
&gxbb_i2c,
3443
-
&gxbb_sar_adc,
3444
-
&gxbb_smart_card,
3445
-
&gxbb_rng0,
3446
-
&gxbb_uart0,
3447
-
&gxbb_sdhc,
3448
-
&gxbb_stream,
3449
-
&gxbb_async_fifo,
3450
-
&gxbb_sdio,
3451
-
&gxbb_abuf,
3452
-
&gxbb_hiu_iface,
3453
-
&gxbb_assist_misc,
3454
-
&gxbb_spi,
3455
-
&gxbb_i2s_spdif,
3456
-
&gxbb_eth,
3457
-
&gxbb_demux,
3458
-
&gxbb_aiu_glue,
3459
-
&gxbb_iec958,
3460
-
&gxbb_i2s_out,
3461
-
&gxbb_amclk,
3462
-
&gxbb_aififo2,
3463
-
&gxbb_mixer,
3464
-
&gxbb_mixer_iface,
3465
-
&gxbb_adc,
3466
-
&gxbb_blkmv,
3467
-
&gxbb_aiu,
3468
-
&gxbb_uart1,
3469
-
&gxbb_g2d,
3470
-
&gxbb_usb0,
3471
-
&gxbb_usb1,
3472
-
&gxbb_reset,
3473
-
&gxbb_nand,
3474
-
&gxbb_dos_parser,
3475
-
&gxbb_usb,
3476
-
&gxbb_vdin1,
3477
-
&gxbb_ahb_arb0,
3478
-
&gxbb_efuse,
3479
-
&gxbb_boot_rom,
3480
-
&gxbb_ahb_data_bus,
3481
-
&gxbb_ahb_ctrl_bus,
3482
-
&gxbb_hdmi_intr_sync,
3483
-
&gxbb_hdmi_pclk,
3484
-
&gxbb_usb1_ddr_bridge,
3485
-
&gxbb_usb0_ddr_bridge,
3486
-
&gxbb_mmc_pclk,
3487
-
&gxbb_dvin,
3488
-
&gxbb_uart2,
3489
-
&gxbb_sana,
3490
-
&gxbb_vpu_intr,
3491
-
&gxbb_sec_ahb_ahb3_bridge,
3492
-
&gxbb_clk81_a53,
3493
-
&gxbb_vclk2_venci0,
3494
-
&gxbb_vclk2_venci1,
3495
-
&gxbb_vclk2_vencp0,
3496
-
&gxbb_vclk2_vencp1,
3497
-
&gxbb_gclk_venci_int0,
3498
-
&gxbb_gclk_vencp_int,
3499
-
&gxbb_dac_clk,
3500
-
&gxbb_aoclk_gate,
3501
-
&gxbb_iec958_gate,
3502
-
&gxbb_enc480p,
3503
-
&gxbb_rng1,
3504
-
&gxbb_gclk_venci_int1,
3505
-
&gxbb_vclk2_venclmcc,
3506
-
&gxbb_vclk2_vencl,
3507
-
&gxbb_vclk_other,
3508
-
&gxbb_edp,
3509
-
&gxbb_ao_media_cpu,
3510
-
&gxbb_ao_ahb_sram,
3511
-
&gxbb_ao_ahb_bus,
3512
-
&gxbb_ao_iface,
3513
-
&gxbb_ao_i2c,
3514
-
&gxbb_emmc_a,
3515
-
&gxbb_emmc_b,
3516
-
&gxbb_emmc_c,
3517
-
&gxbb_sar_adc_clk,
3518
-
&gxbb_mali_0,
3519
-
&gxbb_mali_1,
3520
-
&gxbb_cts_amclk,
3521
-
&gxbb_cts_mclk_i958,
3522
-
&gxbb_32k_clk,
3523
-
&gxbb_sd_emmc_a_clk0,
3524
-
&gxbb_sd_emmc_b_clk0,
3525
-
&gxbb_sd_emmc_c_clk0,
3526
-
&gxbb_vpu_0,
3527
-
&gxbb_vpu_1,
3528
-
&gxbb_vapb_0,
3529
-
&gxbb_vapb_1,
3530
-
&gxbb_vapb,
3531
-
&gxbb_mpeg_clk_div,
3532
-
&gxbb_sar_adc_clk_div,
3533
-
&gxbb_mali_0_div,
3534
-
&gxbb_mali_1_div,
3535
-
&gxbb_cts_mclk_i958_div,
3536
-
&gxbb_32k_clk_div,
3537
-
&gxbb_sd_emmc_a_clk0_div,
3538
-
&gxbb_sd_emmc_b_clk0_div,
3539
-
&gxbb_sd_emmc_c_clk0_div,
3540
-
&gxbb_vpu_0_div,
3541
-
&gxbb_vpu_1_div,
3542
-
&gxbb_vapb_0_div,
3543
-
&gxbb_vapb_1_div,
3544
-
&gxbb_mpeg_clk_sel,
3545
-
&gxbb_sar_adc_clk_sel,
3546
-
&gxbb_mali_0_sel,
3547
-
&gxbb_mali_1_sel,
3548
-
&gxbb_mali,
3549
-
&gxbb_cts_amclk_sel,
3550
-
&gxbb_cts_mclk_i958_sel,
3551
-
&gxbb_cts_i958,
3552
-
&gxbb_32k_clk_sel,
3553
-
&gxbb_sd_emmc_a_clk0_sel,
3554
-
&gxbb_sd_emmc_b_clk0_sel,
3555
-
&gxbb_sd_emmc_c_clk0_sel,
3556
-
&gxbb_vpu_0_sel,
3557
-
&gxbb_vpu_1_sel,
3558
-
&gxbb_vpu,
3559
-
&gxbb_vapb_0_sel,
3560
-
&gxbb_vapb_1_sel,
3561
-
&gxbb_vapb_sel,
3562
-
&gxbb_mpll0,
3563
-
&gxbb_mpll1,
3564
-
&gxbb_mpll2,
3565
-
&gxl_mpll0_div,
3566
-
&gxbb_mpll1_div,
3567
-
&gxbb_mpll2_div,
3568
-
&gxbb_cts_amclk_div,
3569
-
&gxbb_fixed_pll,
3570
-
&gxbb_sys_pll,
3571
-
&gxbb_mpll_prediv,
3572
-
&gxbb_fclk_div2,
3573
-
&gxbb_fclk_div3,
3574
-
&gxbb_fclk_div4,
3575
-
&gxbb_fclk_div5,
3576
-
&gxbb_fclk_div7,
3577
-
&gxbb_vdec_1_sel,
3578
-
&gxbb_vdec_1_div,
3579
-
&gxbb_vdec_1,
3580
-
&gxbb_vdec_hevc_sel,
3581
-
&gxbb_vdec_hevc_div,
3582
-
&gxbb_vdec_hevc,
3583
-
&gxbb_gen_clk_sel,
3584
-
&gxbb_gen_clk_div,
3585
-
&gxbb_gen_clk,
3586
-
&gxbb_fixed_pll_dco,
3587
-
&gxbb_sys_pll_dco,
3588
-
&gxbb_gp0_pll,
3589
-
&gxbb_vid_pll,
3590
-
&gxbb_vid_pll_sel,
3591
-
&gxbb_vid_pll_div,
3592
-
&gxbb_vclk,
3593
-
&gxbb_vclk_sel,
3594
-
&gxbb_vclk_div,
3595
-
&gxbb_vclk_input,
3596
-
&gxbb_vclk_div1,
3597
-
&gxbb_vclk_div2_en,
3598
-
&gxbb_vclk_div4_en,
3599
-
&gxbb_vclk_div6_en,
3600
-
&gxbb_vclk_div12_en,
3601
-
&gxbb_vclk2,
3602
-
&gxbb_vclk2_sel,
3603
-
&gxbb_vclk2_div,
3604
-
&gxbb_vclk2_input,
3605
-
&gxbb_vclk2_div1,
3606
-
&gxbb_vclk2_div2_en,
3607
-
&gxbb_vclk2_div4_en,
3608
-
&gxbb_vclk2_div6_en,
3609
-
&gxbb_vclk2_div12_en,
3610
-
&gxbb_cts_enci,
3611
-
&gxbb_cts_enci_sel,
3612
-
&gxbb_cts_encp,
3613
-
&gxbb_cts_encp_sel,
3614
-
&gxbb_cts_vdac,
3615
-
&gxbb_cts_vdac_sel,
3616
-
&gxbb_hdmi_tx,
3617
-
&gxbb_hdmi_tx_sel,
3618
-
&gxbb_hdmi_sel,
3619
-
&gxbb_hdmi_div,
3620
-
&gxbb_hdmi,
3621
-
&gxl_gp0_pll_dco,
3622
-
&gxl_hdmi_pll,
3623
-
&gxl_hdmi_pll_od,
3624
-
&gxl_hdmi_pll_od2,
3625
-
&gxl_hdmi_pll_dco,
3626
-
&gxl_acodec,
3627
-
};
3628
-
3629
3143
static const struct meson_eeclkc_data gxbb_clkc_data = {
3630
-
.regmap_clks = gxbb_clk_regmaps,
3631
-
.regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3632
3144
.hw_clks = {
3633
3145
.hws = gxbb_hw_clks,
3634
3146
.num = ARRAY_SIZE(gxbb_hw_clks),
···
3245
3539
};
3246
3540
3247
3541
static const struct meson_eeclkc_data gxl_clkc_data = {
3248
-
.regmap_clks = gxl_clk_regmaps,
3249
-
.regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3250
3542
.hw_clks = {
3251
3543
.hws = gxl_hw_clks,
3252
3544
.num = ARRAY_SIZE(gxl_hw_clks),
-115
drivers/clk/meson/gxbb.h
-115
drivers/clk/meson/gxbb.h
···
1
-
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2
-
/*
3
-
* Copyright (c) 2016 AmLogic, Inc.
4
-
* Author: Michael Turquette <mturquette@baylibre.com>
5
-
*/
6
-
7
-
#ifndef __GXBB_H
8
-
#define __GXBB_H
9
-
10
-
/*
11
-
* Clock controller register offsets
12
-
*
13
-
* Register offsets from the data sheet are listed in comment blocks below.
14
-
* Those offsets must be multiplied by 4 before adding them to the base address
15
-
* to get the right value
16
-
*/
17
-
#define SCR 0x2C /* 0x0b offset in data sheet */
18
-
#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
19
-
20
-
#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
21
-
#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
22
-
#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
23
-
#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
24
-
#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
25
-
#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
26
-
27
-
#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
28
-
#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
29
-
30
-
#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */
31
-
#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */
32
-
#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */
33
-
#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
34
-
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
35
-
36
-
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
37
-
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
38
-
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
39
-
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
40
-
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
41
-
#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */
42
-
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
43
-
#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */
44
-
#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
45
-
46
-
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
47
-
#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
48
-
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
49
-
#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
50
-
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
51
-
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
52
-
#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
53
-
#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */
54
-
#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
55
-
#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */
56
-
57
-
#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */
58
-
#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */
59
-
#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */
60
-
#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */
61
-
#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */
62
-
#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */
63
-
#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */
64
-
65
-
#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */
66
-
#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
67
-
#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
68
-
#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
69
-
70
-
#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
71
-
#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
72
-
#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */
73
-
74
-
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
75
-
#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
76
-
#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
77
-
#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
78
-
#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
79
-
#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
80
-
#define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */
81
-
#define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */
82
-
#define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */
83
-
#define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */
84
-
85
-
#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */
86
-
#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */
87
-
#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
88
-
#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
89
-
90
-
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
91
-
#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */
92
-
#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */
93
-
#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */
94
-
#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */
95
-
#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */
96
-
#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */
97
-
#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
98
-
#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
99
-
#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
100
-
#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
101
-
#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
102
-
#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
103
-
#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */
104
-
#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */
105
-
106
-
#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */
107
-
#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */
108
-
#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */
109
-
#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */
110
-
111
-
#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */
112
-
#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
113
-
#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
114
-
115
-
#endif /* __GXBB_H */
+1
-4
drivers/clk/meson/meson-aoclk.c
+1
-4
drivers/clk/meson/meson-aoclk.c
···
18
18
19
19
#include <linux/slab.h>
20
20
#include "meson-aoclk.h"
21
+
#include "clk-regmap.h"
21
22
22
23
static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
23
24
unsigned long id)
···
70
69
dev_err(dev, "failed to register reset controller\n");
71
70
return ret;
72
71
}
73
-
74
-
/* Populate regmap */
75
-
for (clkid = 0; clkid < data->num_clks; clkid++)
76
-
data->clks[clkid]->map = regmap;
77
72
78
73
/* Register all clks */
79
74
for (clkid = 0; clkid < data->hw_clks.num; clkid++) {
-2
drivers/clk/meson/meson-aoclk.h
-2
drivers/clk/meson/meson-aoclk.h
-4
drivers/clk/meson/meson-eeclk.c
-4
drivers/clk/meson/meson-eeclk.c
···
39
39
if (data->init_count)
40
40
regmap_multi_reg_write(map, data->init_regs, data->init_count);
41
41
42
-
/* Populate regmap for the regmap backed clocks */
43
-
for (i = 0; i < data->regmap_clk_num; i++)
44
-
data->regmap_clks[i]->map = map;
45
-
46
42
for (i = 0; i < data->hw_clks.num; i++) {
47
43
/* array might be sparse */
48
44
if (!data->hw_clks.hws[i])
-2
drivers/clk/meson/meson-eeclk.h
-2
drivers/clk/meson/meson-eeclk.h
-9
drivers/clk/meson/meson8-ddr.c
-9
drivers/clk/meson/meson8-ddr.c
···
85
85
.num = 2,
86
86
};
87
87
88
-
static struct clk_regmap *const meson8_ddr_clk_regmaps[] = {
89
-
&meson8_ddr_pll_dco,
90
-
&meson8_ddr_pll,
91
-
};
92
-
93
88
static const struct regmap_config meson8_ddr_clkc_regmap_config = {
94
89
.reg_bits = 8,
95
90
.val_bits = 32,
···
107
112
&meson8_ddr_clkc_regmap_config);
108
113
if (IS_ERR(regmap))
109
114
return PTR_ERR(regmap);
110
-
111
-
/* Populate regmap */
112
-
for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++)
113
-
meson8_ddr_clk_regmaps[i]->map = regmap;
114
115
115
116
/* Register all clks */
116
117
for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) {
+66
-201
drivers/clk/meson/meson8b.c
+66
-201
drivers/clk/meson/meson8b.c
···
16
16
#include <linux/slab.h>
17
17
#include <linux/regmap.h>
18
18
19
-
#include "meson8b.h"
20
19
#include "clk-regmap.h"
21
20
#include "meson-clkc-utils.h"
22
21
#include "clk-pll.h"
···
23
24
24
25
#include <dt-bindings/clock/meson8b-clkc.h>
25
26
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
27
+
28
+
/*
29
+
* Clock controller register offsets
30
+
*
31
+
* Register offsets from the HardKernel[0] data sheet must be multiplied
32
+
* by 4 before adding them to the base address to get the right value
33
+
*
34
+
* [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
35
+
*/
36
+
#define HHI_GP_PLL_CNTL 0x40
37
+
#define HHI_GP_PLL_CNTL2 0x44
38
+
#define HHI_GP_PLL_CNTL3 0x48
39
+
#define HHI_GP_PLL_CNTL4 0x4C
40
+
#define HHI_GP_PLL_CNTL5 0x50
41
+
#define HHI_VIID_CLK_DIV 0x128
42
+
#define HHI_VIID_CLK_CNTL 0x12c
43
+
#define HHI_GCLK_MPEG0 0x140
44
+
#define HHI_GCLK_MPEG1 0x144
45
+
#define HHI_GCLK_MPEG2 0x148
46
+
#define HHI_GCLK_OTHER 0x150
47
+
#define HHI_GCLK_AO 0x154
48
+
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
49
+
#define HHI_VID_CLK_DIV 0x164
50
+
#define HHI_MPEG_CLK_CNTL 0x174
51
+
#define HHI_AUD_CLK_CNTL 0x178
52
+
#define HHI_VID_CLK_CNTL 0x17c
53
+
#define HHI_AUD_CLK_CNTL2 0x190
54
+
#define HHI_VID_CLK_CNTL2 0x194
55
+
#define HHI_VID_DIVIDER_CNTL 0x198
56
+
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
57
+
#define HHI_MALI_CLK_CNTL 0x1b0
58
+
#define HHI_VPU_CLK_CNTL 0x1bc
59
+
#define HHI_HDMI_CLK_CNTL 0x1cc
60
+
#define HHI_VDEC_CLK_CNTL 0x1e0
61
+
#define HHI_VDEC2_CLK_CNTL 0x1e4
62
+
#define HHI_VDEC3_CLK_CNTL 0x1e8
63
+
#define HHI_NAND_CLK_CNTL 0x25c
64
+
#define HHI_MPLL_CNTL 0x280
65
+
#define HHI_SYS_PLL_CNTL 0x300
66
+
#define HHI_VID_PLL_CNTL 0x320
67
+
#define HHI_VID_PLL_CNTL2 0x324
68
+
#define HHI_VID_PLL_CNTL3 0x328
69
+
#define HHI_VID_PLL_CNTL4 0x32c
70
+
#define HHI_VID_PLL_CNTL5 0x330
71
+
#define HHI_VID_PLL_CNTL6 0x334
72
+
#define HHI_VID2_PLL_CNTL 0x380
73
+
#define HHI_VID2_PLL_CNTL2 0x384
74
+
#define HHI_VID2_PLL_CNTL3 0x388
75
+
#define HHI_VID2_PLL_CNTL4 0x38c
76
+
#define HHI_VID2_PLL_CNTL5 0x390
77
+
#define HHI_VID2_PLL_CNTL6 0x394
78
+
79
+
/*
80
+
* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
81
+
* confirm these are the same for the S805.
82
+
*/
83
+
#define HHI_MPLL_CNTL 0x280
84
+
#define HHI_MPLL_CNTL2 0x284
85
+
#define HHI_MPLL_CNTL3 0x288
86
+
#define HHI_MPLL_CNTL4 0x28c
87
+
#define HHI_MPLL_CNTL5 0x290
88
+
#define HHI_MPLL_CNTL6 0x294
89
+
#define HHI_MPLL_CNTL7 0x298
90
+
#define HHI_MPLL_CNTL8 0x29c
91
+
#define HHI_MPLL_CNTL9 0x2a0
92
+
#define HHI_MPLL_CNTL10 0x2a4
26
93
27
94
struct meson8b_clk_reset {
28
95
struct reset_controller_dev reset;
···
3472
3407
[CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
3473
3408
};
3474
3409
3475
-
static struct clk_regmap *const meson8b_clk_regmaps[] = {
3476
-
&meson8b_clk81,
3477
-
&meson8b_ddr,
3478
-
&meson8b_dos,
3479
-
&meson8b_isa,
3480
-
&meson8b_pl301,
3481
-
&meson8b_periphs,
3482
-
&meson8b_spicc,
3483
-
&meson8b_i2c,
3484
-
&meson8b_sar_adc,
3485
-
&meson8b_smart_card,
3486
-
&meson8b_rng0,
3487
-
&meson8b_uart0,
3488
-
&meson8b_sdhc,
3489
-
&meson8b_stream,
3490
-
&meson8b_async_fifo,
3491
-
&meson8b_sdio,
3492
-
&meson8b_abuf,
3493
-
&meson8b_hiu_iface,
3494
-
&meson8b_assist_misc,
3495
-
&meson8b_spi,
3496
-
&meson8b_i2s_spdif,
3497
-
&meson8b_eth,
3498
-
&meson8b_demux,
3499
-
&meson8b_aiu_glue,
3500
-
&meson8b_iec958,
3501
-
&meson8b_i2s_out,
3502
-
&meson8b_amclk,
3503
-
&meson8b_aififo2,
3504
-
&meson8b_mixer,
3505
-
&meson8b_mixer_iface,
3506
-
&meson8b_adc,
3507
-
&meson8b_blkmv,
3508
-
&meson8b_aiu,
3509
-
&meson8b_uart1,
3510
-
&meson8b_g2d,
3511
-
&meson8b_usb0,
3512
-
&meson8b_usb1,
3513
-
&meson8b_reset,
3514
-
&meson8b_nand,
3515
-
&meson8b_dos_parser,
3516
-
&meson8b_usb,
3517
-
&meson8b_vdin1,
3518
-
&meson8b_ahb_arb0,
3519
-
&meson8b_efuse,
3520
-
&meson8b_boot_rom,
3521
-
&meson8b_ahb_data_bus,
3522
-
&meson8b_ahb_ctrl_bus,
3523
-
&meson8b_hdmi_intr_sync,
3524
-
&meson8b_hdmi_pclk,
3525
-
&meson8b_usb1_ddr_bridge,
3526
-
&meson8b_usb0_ddr_bridge,
3527
-
&meson8b_mmc_pclk,
3528
-
&meson8b_dvin,
3529
-
&meson8b_uart2,
3530
-
&meson8b_sana,
3531
-
&meson8b_vpu_intr,
3532
-
&meson8b_sec_ahb_ahb3_bridge,
3533
-
&meson8b_clk81_a9,
3534
-
&meson8b_vclk2_venci0,
3535
-
&meson8b_vclk2_venci1,
3536
-
&meson8b_vclk2_vencp0,
3537
-
&meson8b_vclk2_vencp1,
3538
-
&meson8b_gclk_venci_int,
3539
-
&meson8b_gclk_vencp_int,
3540
-
&meson8b_dac_clk,
3541
-
&meson8b_aoclk_gate,
3542
-
&meson8b_iec958_gate,
3543
-
&meson8b_enc480p,
3544
-
&meson8b_rng1,
3545
-
&meson8b_gclk_vencl_int,
3546
-
&meson8b_vclk2_venclmcc,
3547
-
&meson8b_vclk2_vencl,
3548
-
&meson8b_vclk2_other,
3549
-
&meson8b_edp,
3550
-
&meson8b_ao_media_cpu,
3551
-
&meson8b_ao_ahb_sram,
3552
-
&meson8b_ao_ahb_bus,
3553
-
&meson8b_ao_iface,
3554
-
&meson8b_mpeg_clk_div,
3555
-
&meson8b_mpeg_clk_sel,
3556
-
&meson8b_mpll0,
3557
-
&meson8b_mpll1,
3558
-
&meson8b_mpll2,
3559
-
&meson8b_mpll0_div,
3560
-
&meson8b_mpll1_div,
3561
-
&meson8b_mpll2_div,
3562
-
&meson8b_fixed_pll,
3563
-
&meson8b_sys_pll,
3564
-
&meson8b_cpu_in_sel,
3565
-
&meson8b_cpu_scale_div,
3566
-
&meson8b_cpu_scale_out_sel,
3567
-
&meson8b_cpu_clk,
3568
-
&meson8b_mpll_prediv,
3569
-
&meson8b_fclk_div2,
3570
-
&meson8b_fclk_div3,
3571
-
&meson8b_fclk_div4,
3572
-
&meson8b_fclk_div5,
3573
-
&meson8b_fclk_div7,
3574
-
&meson8b_nand_clk_sel,
3575
-
&meson8b_nand_clk_div,
3576
-
&meson8b_nand_clk_gate,
3577
-
&meson8b_fixed_pll_dco,
3578
-
&meson8b_hdmi_pll_dco,
3579
-
&meson8b_sys_pll_dco,
3580
-
&meson8b_apb_clk_sel,
3581
-
&meson8b_apb_clk_gate,
3582
-
&meson8b_periph_clk_sel,
3583
-
&meson8b_periph_clk_gate,
3584
-
&meson8b_axi_clk_sel,
3585
-
&meson8b_axi_clk_gate,
3586
-
&meson8b_l2_dram_clk_sel,
3587
-
&meson8b_l2_dram_clk_gate,
3588
-
&meson8b_hdmi_pll_lvds_out,
3589
-
&meson8b_hdmi_pll_hdmi_out,
3590
-
&meson8b_vid_pll_in_sel,
3591
-
&meson8b_vid_pll_in_en,
3592
-
&meson8b_vid_pll_pre_div,
3593
-
&meson8b_vid_pll_post_div,
3594
-
&meson8b_vid_pll,
3595
-
&meson8b_vid_pll_final_div,
3596
-
&meson8b_vclk_in_sel,
3597
-
&meson8b_vclk_in_en,
3598
-
&meson8b_vclk_en,
3599
-
&meson8b_vclk_div1_gate,
3600
-
&meson8b_vclk_div2_div_gate,
3601
-
&meson8b_vclk_div4_div_gate,
3602
-
&meson8b_vclk_div6_div_gate,
3603
-
&meson8b_vclk_div12_div_gate,
3604
-
&meson8b_vclk2_in_sel,
3605
-
&meson8b_vclk2_clk_in_en,
3606
-
&meson8b_vclk2_clk_en,
3607
-
&meson8b_vclk2_div1_gate,
3608
-
&meson8b_vclk2_div2_div_gate,
3609
-
&meson8b_vclk2_div4_div_gate,
3610
-
&meson8b_vclk2_div6_div_gate,
3611
-
&meson8b_vclk2_div12_div_gate,
3612
-
&meson8b_cts_enct_sel,
3613
-
&meson8b_cts_enct,
3614
-
&meson8b_cts_encp_sel,
3615
-
&meson8b_cts_encp,
3616
-
&meson8b_cts_enci_sel,
3617
-
&meson8b_cts_enci,
3618
-
&meson8b_hdmi_tx_pixel_sel,
3619
-
&meson8b_hdmi_tx_pixel,
3620
-
&meson8b_cts_encl_sel,
3621
-
&meson8b_cts_encl,
3622
-
&meson8b_cts_vdac0_sel,
3623
-
&meson8b_cts_vdac0,
3624
-
&meson8b_hdmi_sys_sel,
3625
-
&meson8b_hdmi_sys_div,
3626
-
&meson8b_hdmi_sys,
3627
-
&meson8b_mali_0_sel,
3628
-
&meson8b_mali_0_div,
3629
-
&meson8b_mali_0,
3630
-
&meson8b_mali_1_sel,
3631
-
&meson8b_mali_1_div,
3632
-
&meson8b_mali_1,
3633
-
&meson8b_mali,
3634
-
&meson8m2_gp_pll_dco,
3635
-
&meson8m2_gp_pll,
3636
-
&meson8b_vpu_0_sel,
3637
-
&meson8m2_vpu_0_sel,
3638
-
&meson8b_vpu_0_div,
3639
-
&meson8b_vpu_0,
3640
-
&meson8b_vpu_1_sel,
3641
-
&meson8m2_vpu_1_sel,
3642
-
&meson8b_vpu_1_div,
3643
-
&meson8b_vpu_1,
3644
-
&meson8b_vpu,
3645
-
&meson8b_vdec_1_sel,
3646
-
&meson8b_vdec_1_1_div,
3647
-
&meson8b_vdec_1_1,
3648
-
&meson8b_vdec_1_2_div,
3649
-
&meson8b_vdec_1_2,
3650
-
&meson8b_vdec_1,
3651
-
&meson8b_vdec_hcodec_sel,
3652
-
&meson8b_vdec_hcodec_div,
3653
-
&meson8b_vdec_hcodec,
3654
-
&meson8b_vdec_2_sel,
3655
-
&meson8b_vdec_2_div,
3656
-
&meson8b_vdec_2,
3657
-
&meson8b_vdec_hevc_sel,
3658
-
&meson8b_vdec_hevc_div,
3659
-
&meson8b_vdec_hevc_en,
3660
-
&meson8b_vdec_hevc,
3661
-
&meson8b_cts_amclk,
3662
-
&meson8b_cts_amclk_sel,
3663
-
&meson8b_cts_amclk_div,
3664
-
&meson8b_cts_mclk_i958_sel,
3665
-
&meson8b_cts_mclk_i958_div,
3666
-
&meson8b_cts_mclk_i958,
3667
-
&meson8b_cts_i958,
3668
-
&meson8b_vid_pll_lvds_en,
3669
-
};
3670
-
3671
3410
static const struct meson8b_clk_reset_line {
3672
3411
u32 reg;
3673
3412
u8 bit_idx;
···
3687
3818
__func__, ret);
3688
3819
return;
3689
3820
}
3690
-
3691
-
/* Populate regmap for the regmap backed clocks */
3692
-
for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
3693
-
meson8b_clk_regmaps[i]->map = map;
3694
3821
3695
3822
/*
3696
3823
* register all clks and start with the first used ID (which is
-80
drivers/clk/meson/meson8b.h
-80
drivers/clk/meson/meson8b.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* Copyright (c) 2015 Endless Mobile, Inc.
4
-
* Author: Carlo Caione <carlo@endlessm.com>
5
-
*
6
-
* Copyright (c) 2016 BayLibre, Inc.
7
-
* Michael Turquette <mturquette@baylibre.com>
8
-
*/
9
-
10
-
#ifndef __MESON8B_H
11
-
#define __MESON8B_H
12
-
13
-
/*
14
-
* Clock controller register offsets
15
-
*
16
-
* Register offsets from the HardKernel[0] data sheet are listed in comment
17
-
* blocks below. Those offsets must be multiplied by 4 before adding them to
18
-
* the base address to get the right value
19
-
*
20
-
* [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
21
-
*/
22
-
#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
23
-
#define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
24
-
#define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
25
-
#define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */
26
-
#define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
27
-
#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
28
-
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
29
-
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
30
-
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
31
-
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
32
-
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
33
-
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
34
-
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
35
-
#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
36
-
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
37
-
#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
38
-
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
39
-
#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
40
-
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
41
-
#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
42
-
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
43
-
#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
44
-
#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */
45
-
#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
46
-
#define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */
47
-
#define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */
48
-
#define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */
49
-
#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
50
-
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
51
-
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
52
-
#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
53
-
#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
54
-
#define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
55
-
#define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */
56
-
#define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
57
-
#define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
58
-
#define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */
59
-
#define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */
60
-
#define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */
61
-
#define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */
62
-
#define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */
63
-
#define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */
64
-
65
-
/*
66
-
* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
67
-
* confirm these are the same for the S805.
68
-
*/
69
-
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
70
-
#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
71
-
#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
72
-
#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
73
-
#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
74
-
#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
75
-
#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */
76
-
#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */
77
-
#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
78
-
#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
79
-
80
-
#endif /* __MESON8B_H */
+46
-342
drivers/clk/meson/s4-peripherals.c
+46
-342
drivers/clk/meson/s4-peripherals.c
···
13
13
#include "clk-regmap.h"
14
14
#include "vid-pll-div.h"
15
15
#include "clk-dualdiv.h"
16
-
#include "s4-peripherals.h"
17
16
#include "meson-clkc-utils.h"
18
17
#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
18
+
19
+
#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008
20
+
#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c
21
+
#define CLKCTRL_RTC_CTRL 0x010
22
+
#define CLKCTRL_SYS_CLK_CTRL0 0x040
23
+
#define CLKCTRL_SYS_CLK_EN0_REG0 0x044
24
+
#define CLKCTRL_SYS_CLK_EN0_REG1 0x048
25
+
#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c
26
+
#define CLKCTRL_SYS_CLK_EN0_REG3 0x050
27
+
#define CLKCTRL_CECA_CTRL0 0x088
28
+
#define CLKCTRL_CECA_CTRL1 0x08c
29
+
#define CLKCTRL_CECB_CTRL0 0x090
30
+
#define CLKCTRL_CECB_CTRL1 0x094
31
+
#define CLKCTRL_SC_CLK_CTRL 0x098
32
+
#define CLKCTRL_CLK12_24_CTRL 0x0a8
33
+
#define CLKCTRL_VID_CLK_CTRL 0x0c0
34
+
#define CLKCTRL_VID_CLK_CTRL2 0x0c4
35
+
#define CLKCTRL_VID_CLK_DIV 0x0c8
36
+
#define CLKCTRL_VIID_CLK_DIV 0x0cc
37
+
#define CLKCTRL_VIID_CLK_CTRL 0x0d0
38
+
#define CLKCTRL_HDMI_CLK_CTRL 0x0e0
39
+
#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4
40
+
#define CLKCTRL_VPU_CLK_CTRL 0x0e8
41
+
#define CLKCTRL_VPU_CLKB_CTRL 0x0ec
42
+
#define CLKCTRL_VPU_CLKC_CTRL 0x0f0
43
+
#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4
44
+
#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8
45
+
#define CLKCTRL_VAPBCLK_CTRL 0x0fc
46
+
#define CLKCTRL_HDCP22_CTRL 0x100
47
+
#define CLKCTRL_VDEC_CLK_CTRL 0x140
48
+
#define CLKCTRL_VDEC2_CLK_CTRL 0x144
49
+
#define CLKCTRL_VDEC3_CLK_CTRL 0x148
50
+
#define CLKCTRL_VDEC4_CLK_CTRL 0x14c
51
+
#define CLKCTRL_TS_CLK_CTRL 0x158
52
+
#define CLKCTRL_MALI_CLK_CTRL 0x15c
53
+
#define CLKCTRL_NAND_CLK_CTRL 0x168
54
+
#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c
55
+
#define CLKCTRL_SPICC_CLK_CTRL 0x174
56
+
#define CLKCTRL_GEN_CLK_CTRL 0x178
57
+
#define CLKCTRL_SAR_CLK_CTRL 0x17c
58
+
#define CLKCTRL_PWM_CLK_AB_CTRL 0x180
59
+
#define CLKCTRL_PWM_CLK_CD_CTRL 0x184
60
+
#define CLKCTRL_PWM_CLK_EF_CTRL 0x188
61
+
#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c
62
+
#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190
63
+
#define CLKCTRL_DEMOD_CLK_CTRL 0x200
19
64
20
65
static struct clk_regmap s4_rtc_32k_by_oscin_clkin = {
21
66
.data = &(struct clk_regmap_gate_data){
···
3174
3129
},
3175
3130
};
3176
3131
3177
-
static const struct clk_parent_data s4_adc_extclk_in_parent_data[] = {
3178
-
{ .fw_name = "xtal", },
3179
-
{ .fw_name = "fclk_div4", },
3180
-
{ .fw_name = "fclk_div3", },
3181
-
{ .fw_name = "fclk_div5", },
3182
-
{ .fw_name = "fclk_div7", },
3183
-
{ .fw_name = "mpll2", },
3184
-
{ .fw_name = "gp0_pll", },
3185
-
{ .fw_name = "hifi_pll", },
3186
-
};
3187
-
3188
-
static struct clk_regmap s4_adc_extclk_in_mux = {
3189
-
.data = &(struct clk_regmap_mux_data) {
3190
-
.offset = CLKCTRL_DEMOD_CLK_CTRL,
3191
-
.mask = 0x7,
3192
-
.shift = 25,
3193
-
},
3194
-
.hw.init = &(struct clk_init_data){
3195
-
.name = "adc_extclk_in_mux",
3196
-
.ops = &clk_regmap_mux_ops,
3197
-
.parent_data = s4_adc_extclk_in_parent_data,
3198
-
.num_parents = ARRAY_SIZE(s4_adc_extclk_in_parent_data),
3199
-
.flags = 0,
3200
-
},
3201
-
};
3202
-
3203
-
static struct clk_regmap s4_adc_extclk_in_div = {
3204
-
.data = &(struct clk_regmap_div_data) {
3205
-
.offset = CLKCTRL_DEMOD_CLK_CTRL,
3206
-
.shift = 16,
3207
-
.width = 7,
3208
-
},
3209
-
.hw.init = &(struct clk_init_data){
3210
-
.name = "adc_extclk_in_div",
3211
-
.ops = &clk_regmap_divider_ops,
3212
-
.parent_hws = (const struct clk_hw *[]) {
3213
-
&s4_adc_extclk_in_mux.hw
3214
-
},
3215
-
.num_parents = 1,
3216
-
.flags = CLK_SET_RATE_PARENT,
3217
-
},
3218
-
};
3219
-
3220
-
static struct clk_regmap s4_adc_extclk_in_gate = {
3221
-
.data = &(struct clk_regmap_gate_data) {
3222
-
.offset = CLKCTRL_DEMOD_CLK_CTRL,
3223
-
.bit_idx = 24,
3224
-
},
3225
-
.hw.init = &(struct clk_init_data){
3226
-
.name = "adc_extclk_in",
3227
-
.ops = &clk_regmap_gate_ops,
3228
-
.parent_hws = (const struct clk_hw *[]) {
3229
-
&s4_adc_extclk_in_div.hw
3230
-
},
3231
-
.num_parents = 1,
3232
-
.flags = CLK_SET_RATE_PARENT,
3233
-
},
3234
-
};
3235
-
3236
-
static struct clk_regmap s4_demod_core_clk_mux = {
3237
-
.data = &(struct clk_regmap_mux_data) {
3238
-
.offset = CLKCTRL_DEMOD_CLK_CTRL,
3239
-
.mask = 0x3,
3240
-
.shift = 9,
3241
-
},
3242
-
.hw.init = &(struct clk_init_data){
3243
-
.name = "demod_core_clk_mux",
3244
-
.ops = &clk_regmap_mux_ops,
3245
-
.parent_data = (const struct clk_parent_data []) {
3246
-
{ .fw_name = "xtal", },
3247
-
{ .fw_name = "fclk_div7", },
3248
-
{ .fw_name = "fclk_div4", },
3249
-
{ .hw = &s4_adc_extclk_in_gate.hw }
3250
-
},
3251
-
.num_parents = 4,
3252
-
.flags = CLK_SET_RATE_PARENT,
3253
-
},
3254
-
};
3255
-
3256
-
static struct clk_regmap s4_demod_core_clk_div = {
3257
-
.data = &(struct clk_regmap_div_data) {
3258
-
.offset = CLKCTRL_DEMOD_CLK_CTRL,
3259
-
.shift = 0,
3260
-
.width = 7,
3261
-
},
3262
-
.hw.init = &(struct clk_init_data){
3263
-
.name = "demod_core_clk_div",
3264
-
.ops = &clk_regmap_divider_ops,
3265
-
.parent_hws = (const struct clk_hw *[]) {
3266
-
&s4_demod_core_clk_mux.hw
3267
-
},
3268
-
.num_parents = 1,
3269
-
.flags = CLK_SET_RATE_PARENT,
3270
-
},
3271
-
};
3272
-
3273
-
static struct clk_regmap s4_demod_core_clk_gate = {
3274
-
.data = &(struct clk_regmap_gate_data) {
3275
-
.offset = CLKCTRL_DEMOD_CLK_CTRL,
3276
-
.bit_idx = 8,
3277
-
},
3278
-
.hw.init = &(struct clk_init_data){
3279
-
.name = "demod_core_clk",
3280
-
.ops = &clk_regmap_gate_ops,
3281
-
.parent_hws = (const struct clk_hw *[]) {
3282
-
&s4_demod_core_clk_div.hw
3283
-
},
3284
-
.num_parents = 1,
3285
-
.flags = CLK_SET_RATE_PARENT,
3286
-
},
3287
-
};
3288
-
3289
3132
#define MESON_GATE(_name, _reg, _bit) \
3290
3133
MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw)
3291
3134
···
3455
3522
[CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk_gate.hw,
3456
3523
};
3457
3524
3458
-
/* Convenience table to populate regmap in .probe */
3459
-
static struct clk_regmap *const s4_periphs_clk_regmaps[] = {
3460
-
&s4_rtc_32k_by_oscin_clkin,
3461
-
&s4_rtc_32k_by_oscin_div,
3462
-
&s4_rtc_32k_by_oscin_sel,
3463
-
&s4_rtc_32k_by_oscin,
3464
-
&s4_rtc_clk,
3465
-
&s4_sysclk_b_sel,
3466
-
&s4_sysclk_b_div,
3467
-
&s4_sysclk_b,
3468
-
&s4_sysclk_a_sel,
3469
-
&s4_sysclk_a_div,
3470
-
&s4_sysclk_a,
3471
-
&s4_sys_clk,
3472
-
&s4_ceca_32k_clkin,
3473
-
&s4_ceca_32k_div,
3474
-
&s4_ceca_32k_sel_pre,
3475
-
&s4_ceca_32k_sel,
3476
-
&s4_ceca_32k_clkout,
3477
-
&s4_cecb_32k_clkin,
3478
-
&s4_cecb_32k_div,
3479
-
&s4_cecb_32k_sel_pre,
3480
-
&s4_cecb_32k_sel,
3481
-
&s4_cecb_32k_clkout,
3482
-
&s4_sc_clk_mux,
3483
-
&s4_sc_clk_div,
3484
-
&s4_sc_clk_gate,
3485
-
&s4_12_24M_clk_gate,
3486
-
&s4_12_24M_clk,
3487
-
&s4_vid_pll_div,
3488
-
&s4_vid_pll_sel,
3489
-
&s4_vid_pll,
3490
-
&s4_vclk_sel,
3491
-
&s4_vclk2_sel,
3492
-
&s4_vclk_input,
3493
-
&s4_vclk2_input,
3494
-
&s4_vclk_div,
3495
-
&s4_vclk2_div,
3496
-
&s4_vclk,
3497
-
&s4_vclk2,
3498
-
&s4_vclk_div1,
3499
-
&s4_vclk_div2_en,
3500
-
&s4_vclk_div4_en,
3501
-
&s4_vclk_div6_en,
3502
-
&s4_vclk_div12_en,
3503
-
&s4_vclk2_div1,
3504
-
&s4_vclk2_div2_en,
3505
-
&s4_vclk2_div4_en,
3506
-
&s4_vclk2_div6_en,
3507
-
&s4_vclk2_div12_en,
3508
-
&s4_cts_enci_sel,
3509
-
&s4_cts_encp_sel,
3510
-
&s4_cts_vdac_sel,
3511
-
&s4_hdmi_tx_sel,
3512
-
&s4_cts_enci,
3513
-
&s4_cts_encp,
3514
-
&s4_cts_vdac,
3515
-
&s4_hdmi_tx,
3516
-
&s4_hdmi_sel,
3517
-
&s4_hdmi_div,
3518
-
&s4_hdmi,
3519
-
&s4_ts_clk_div,
3520
-
&s4_ts_clk_gate,
3521
-
&s4_mali_0_sel,
3522
-
&s4_mali_0_div,
3523
-
&s4_mali_0,
3524
-
&s4_mali_1_sel,
3525
-
&s4_mali_1_div,
3526
-
&s4_mali_1,
3527
-
&s4_mali_mux,
3528
-
&s4_vdec_p0_mux,
3529
-
&s4_vdec_p0_div,
3530
-
&s4_vdec_p0,
3531
-
&s4_vdec_p1_mux,
3532
-
&s4_vdec_p1_div,
3533
-
&s4_vdec_p1,
3534
-
&s4_vdec_mux,
3535
-
&s4_hevcf_p0_mux,
3536
-
&s4_hevcf_p0_div,
3537
-
&s4_hevcf_p0,
3538
-
&s4_hevcf_p1_mux,
3539
-
&s4_hevcf_p1_div,
3540
-
&s4_hevcf_p1,
3541
-
&s4_hevcf_mux,
3542
-
&s4_vpu_0_sel,
3543
-
&s4_vpu_0_div,
3544
-
&s4_vpu_0,
3545
-
&s4_vpu_1_sel,
3546
-
&s4_vpu_1_div,
3547
-
&s4_vpu_1,
3548
-
&s4_vpu,
3549
-
&s4_vpu_clkb_tmp_mux,
3550
-
&s4_vpu_clkb_tmp_div,
3551
-
&s4_vpu_clkb_tmp,
3552
-
&s4_vpu_clkb_div,
3553
-
&s4_vpu_clkb,
3554
-
&s4_vpu_clkc_p0_mux,
3555
-
&s4_vpu_clkc_p0_div,
3556
-
&s4_vpu_clkc_p0,
3557
-
&s4_vpu_clkc_p1_mux,
3558
-
&s4_vpu_clkc_p1_div,
3559
-
&s4_vpu_clkc_p1,
3560
-
&s4_vpu_clkc_mux,
3561
-
&s4_vapb_0_sel,
3562
-
&s4_vapb_0_div,
3563
-
&s4_vapb_0,
3564
-
&s4_vapb_1_sel,
3565
-
&s4_vapb_1_div,
3566
-
&s4_vapb_1,
3567
-
&s4_vapb,
3568
-
&s4_ge2d_gate,
3569
-
&s4_hdcp22_esmclk_mux,
3570
-
&s4_hdcp22_esmclk_div,
3571
-
&s4_hdcp22_esmclk_gate,
3572
-
&s4_hdcp22_skpclk_mux,
3573
-
&s4_hdcp22_skpclk_div,
3574
-
&s4_hdcp22_skpclk_gate,
3575
-
&s4_vdin_meas_mux,
3576
-
&s4_vdin_meas_div,
3577
-
&s4_vdin_meas_gate,
3578
-
&s4_sd_emmc_c_clk0_sel,
3579
-
&s4_sd_emmc_c_clk0_div,
3580
-
&s4_sd_emmc_c_clk0,
3581
-
&s4_sd_emmc_a_clk0_sel,
3582
-
&s4_sd_emmc_a_clk0_div,
3583
-
&s4_sd_emmc_a_clk0,
3584
-
&s4_sd_emmc_b_clk0_sel,
3585
-
&s4_sd_emmc_b_clk0_div,
3586
-
&s4_sd_emmc_b_clk0,
3587
-
&s4_spicc0_mux,
3588
-
&s4_spicc0_div,
3589
-
&s4_spicc0_gate,
3590
-
&s4_pwm_a_mux,
3591
-
&s4_pwm_a_div,
3592
-
&s4_pwm_a_gate,
3593
-
&s4_pwm_b_mux,
3594
-
&s4_pwm_b_div,
3595
-
&s4_pwm_b_gate,
3596
-
&s4_pwm_c_mux,
3597
-
&s4_pwm_c_div,
3598
-
&s4_pwm_c_gate,
3599
-
&s4_pwm_d_mux,
3600
-
&s4_pwm_d_div,
3601
-
&s4_pwm_d_gate,
3602
-
&s4_pwm_e_mux,
3603
-
&s4_pwm_e_div,
3604
-
&s4_pwm_e_gate,
3605
-
&s4_pwm_f_mux,
3606
-
&s4_pwm_f_div,
3607
-
&s4_pwm_f_gate,
3608
-
&s4_pwm_g_mux,
3609
-
&s4_pwm_g_div,
3610
-
&s4_pwm_g_gate,
3611
-
&s4_pwm_h_mux,
3612
-
&s4_pwm_h_div,
3613
-
&s4_pwm_h_gate,
3614
-
&s4_pwm_i_mux,
3615
-
&s4_pwm_i_div,
3616
-
&s4_pwm_i_gate,
3617
-
&s4_pwm_j_mux,
3618
-
&s4_pwm_j_div,
3619
-
&s4_pwm_j_gate,
3620
-
&s4_saradc_mux,
3621
-
&s4_saradc_div,
3622
-
&s4_saradc_gate,
3623
-
&s4_gen_clk_sel,
3624
-
&s4_gen_clk_div,
3625
-
&s4_gen_clk,
3626
-
&s4_ddr,
3627
-
&s4_dos,
3628
-
&s4_ethphy,
3629
-
&s4_mali,
3630
-
&s4_aocpu,
3631
-
&s4_aucpu,
3632
-
&s4_cec,
3633
-
&s4_sdemmca,
3634
-
&s4_sdemmcb,
3635
-
&s4_nand,
3636
-
&s4_smartcard,
3637
-
&s4_acodec,
3638
-
&s4_spifc,
3639
-
&s4_msr_clk,
3640
-
&s4_ir_ctrl,
3641
-
&s4_audio,
3642
-
&s4_eth,
3643
-
&s4_uart_a,
3644
-
&s4_uart_b,
3645
-
&s4_uart_c,
3646
-
&s4_uart_d,
3647
-
&s4_uart_e,
3648
-
&s4_aififo,
3649
-
&s4_ts_ddr,
3650
-
&s4_ts_pll,
3651
-
&s4_g2d,
3652
-
&s4_spicc0,
3653
-
&s4_usb,
3654
-
&s4_i2c_m_a,
3655
-
&s4_i2c_m_b,
3656
-
&s4_i2c_m_c,
3657
-
&s4_i2c_m_d,
3658
-
&s4_i2c_m_e,
3659
-
&s4_hdmitx_apb,
3660
-
&s4_i2c_s_a,
3661
-
&s4_usb1_to_ddr,
3662
-
&s4_hdcp22,
3663
-
&s4_mmc_apb,
3664
-
&s4_rsa,
3665
-
&s4_cpu_debug,
3666
-
&s4_vpu_intr,
3667
-
&s4_demod,
3668
-
&s4_sar_adc,
3669
-
&s4_gic,
3670
-
&s4_pwm_ab,
3671
-
&s4_pwm_cd,
3672
-
&s4_pwm_ef,
3673
-
&s4_pwm_gh,
3674
-
&s4_pwm_ij,
3675
-
&s4_demod_core_clk_mux,
3676
-
&s4_demod_core_clk_div,
3677
-
&s4_demod_core_clk_gate,
3678
-
&s4_adc_extclk_in_mux,
3679
-
&s4_adc_extclk_in_div,
3680
-
&s4_adc_extclk_in_gate,
3681
-
};
3682
-
3683
3525
static const struct regmap_config clkc_regmap_config = {
3684
3526
.reg_bits = 32,
3685
3527
.val_bits = 32,
···
3483
3775
if (IS_ERR(regmap))
3484
3776
return dev_err_probe(dev, PTR_ERR(regmap),
3485
3777
"can't init regmap mmio region\n");
3486
-
3487
-
/* Populate regmap for the regmap backed clocks */
3488
-
for (i = 0; i < ARRAY_SIZE(s4_periphs_clk_regmaps); i++)
3489
-
s4_periphs_clk_regmaps[i]->map = regmap;
3490
3778
3491
3779
for (i = 0; i < s4_periphs_clks.num; i++) {
3492
3780
/* array might be sparse */
-56
drivers/clk/meson/s4-peripherals.h
-56
drivers/clk/meson/s4-peripherals.h
···
1
-
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2
-
/*
3
-
* Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
4
-
* Author: Yu Tu <yu.tu@amlogic.com>
5
-
*/
6
-
7
-
#ifndef __MESON_S4_PERIPHERALS_H__
8
-
#define __MESON_S4_PERIPHERALS_H__
9
-
10
-
#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008
11
-
#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c
12
-
#define CLKCTRL_RTC_CTRL 0x010
13
-
#define CLKCTRL_SYS_CLK_CTRL0 0x040
14
-
#define CLKCTRL_SYS_CLK_EN0_REG0 0x044
15
-
#define CLKCTRL_SYS_CLK_EN0_REG1 0x048
16
-
#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c
17
-
#define CLKCTRL_SYS_CLK_EN0_REG3 0x050
18
-
#define CLKCTRL_CECA_CTRL0 0x088
19
-
#define CLKCTRL_CECA_CTRL1 0x08c
20
-
#define CLKCTRL_CECB_CTRL0 0x090
21
-
#define CLKCTRL_CECB_CTRL1 0x094
22
-
#define CLKCTRL_SC_CLK_CTRL 0x098
23
-
#define CLKCTRL_CLK12_24_CTRL 0x0a8
24
-
#define CLKCTRL_VID_CLK_CTRL 0x0c0
25
-
#define CLKCTRL_VID_CLK_CTRL2 0x0c4
26
-
#define CLKCTRL_VID_CLK_DIV 0x0c8
27
-
#define CLKCTRL_VIID_CLK_DIV 0x0cc
28
-
#define CLKCTRL_VIID_CLK_CTRL 0x0d0
29
-
#define CLKCTRL_HDMI_CLK_CTRL 0x0e0
30
-
#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4
31
-
#define CLKCTRL_VPU_CLK_CTRL 0x0e8
32
-
#define CLKCTRL_VPU_CLKB_CTRL 0x0ec
33
-
#define CLKCTRL_VPU_CLKC_CTRL 0x0f0
34
-
#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4
35
-
#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8
36
-
#define CLKCTRL_VAPBCLK_CTRL 0x0fc
37
-
#define CLKCTRL_HDCP22_CTRL 0x100
38
-
#define CLKCTRL_VDEC_CLK_CTRL 0x140
39
-
#define CLKCTRL_VDEC2_CLK_CTRL 0x144
40
-
#define CLKCTRL_VDEC3_CLK_CTRL 0x148
41
-
#define CLKCTRL_VDEC4_CLK_CTRL 0x14c
42
-
#define CLKCTRL_TS_CLK_CTRL 0x158
43
-
#define CLKCTRL_MALI_CLK_CTRL 0x15c
44
-
#define CLKCTRL_NAND_CLK_CTRL 0x168
45
-
#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c
46
-
#define CLKCTRL_SPICC_CLK_CTRL 0x174
47
-
#define CLKCTRL_GEN_CLK_CTRL 0x178
48
-
#define CLKCTRL_SAR_CLK_CTRL 0x17c
49
-
#define CLKCTRL_PWM_CLK_AB_CTRL 0x180
50
-
#define CLKCTRL_PWM_CLK_CD_CTRL 0x184
51
-
#define CLKCTRL_PWM_CLK_EF_CTRL 0x188
52
-
#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c
53
-
#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190
54
-
#define CLKCTRL_DEMOD_CLK_CTRL 0x200
55
-
56
-
#endif /* __MESON_S4_PERIPHERALS_H__ */
+28
-32
drivers/clk/meson/s4-pll.c
+28
-32
drivers/clk/meson/s4-pll.c
···
13
13
#include "clk-mpll.h"
14
14
#include "clk-pll.h"
15
15
#include "clk-regmap.h"
16
-
#include "s4-pll.h"
17
16
#include "meson-clkc-utils.h"
18
17
#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
18
+
19
+
#define ANACTRL_FIXPLL_CTRL0 0x040
20
+
#define ANACTRL_FIXPLL_CTRL1 0x044
21
+
#define ANACTRL_FIXPLL_CTRL3 0x04c
22
+
#define ANACTRL_GP0PLL_CTRL0 0x080
23
+
#define ANACTRL_GP0PLL_CTRL1 0x084
24
+
#define ANACTRL_GP0PLL_CTRL2 0x088
25
+
#define ANACTRL_GP0PLL_CTRL3 0x08c
26
+
#define ANACTRL_GP0PLL_CTRL4 0x090
27
+
#define ANACTRL_GP0PLL_CTRL5 0x094
28
+
#define ANACTRL_GP0PLL_CTRL6 0x098
29
+
#define ANACTRL_HIFIPLL_CTRL0 0x100
30
+
#define ANACTRL_HIFIPLL_CTRL1 0x104
31
+
#define ANACTRL_HIFIPLL_CTRL2 0x108
32
+
#define ANACTRL_HIFIPLL_CTRL3 0x10c
33
+
#define ANACTRL_HIFIPLL_CTRL4 0x110
34
+
#define ANACTRL_HIFIPLL_CTRL5 0x114
35
+
#define ANACTRL_HIFIPLL_CTRL6 0x118
36
+
#define ANACTRL_MPLL_CTRL0 0x180
37
+
#define ANACTRL_MPLL_CTRL1 0x184
38
+
#define ANACTRL_MPLL_CTRL2 0x188
39
+
#define ANACTRL_MPLL_CTRL3 0x18c
40
+
#define ANACTRL_MPLL_CTRL4 0x190
41
+
#define ANACTRL_MPLL_CTRL5 0x194
42
+
#define ANACTRL_MPLL_CTRL6 0x198
43
+
#define ANACTRL_MPLL_CTRL7 0x19c
44
+
#define ANACTRL_MPLL_CTRL8 0x1a0
45
+
#define ANACTRL_HDMIPLL_CTRL0 0x1c0
19
46
20
47
/*
21
48
* These clock are a fixed value (fixed_pll is 2GHz) that is initialized by ROMcode.
···
794
767
[CLKID_MPLL3] = &s4_mpll3.hw,
795
768
};
796
769
797
-
static struct clk_regmap *const s4_pll_clk_regmaps[] = {
798
-
&s4_fixed_pll_dco,
799
-
&s4_fixed_pll,
800
-
&s4_fclk_div2,
801
-
&s4_fclk_div3,
802
-
&s4_fclk_div4,
803
-
&s4_fclk_div5,
804
-
&s4_fclk_div7,
805
-
&s4_fclk_div2p5,
806
-
&s4_gp0_pll_dco,
807
-
&s4_gp0_pll,
808
-
&s4_hifi_pll_dco,
809
-
&s4_hifi_pll,
810
-
&s4_hdmi_pll_dco,
811
-
&s4_hdmi_pll_od,
812
-
&s4_hdmi_pll,
813
-
&s4_mpll_50m,
814
-
&s4_mpll0_div,
815
-
&s4_mpll0,
816
-
&s4_mpll1_div,
817
-
&s4_mpll1,
818
-
&s4_mpll2_div,
819
-
&s4_mpll2,
820
-
&s4_mpll3_div,
821
-
&s4_mpll3,
822
-
};
823
-
824
770
static const struct reg_sequence s4_init_regs[] = {
825
771
{ .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
826
772
};
···
831
831
if (ret)
832
832
return dev_err_probe(dev, ret,
833
833
"Failed to init registers\n");
834
-
835
-
/* Populate regmap for the regmap backed clocks */
836
-
for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++)
837
-
s4_pll_clk_regmaps[i]->map = regmap;
838
834
839
835
/* Register clocks */
840
836
for (i = 0; i < s4_pll_clks.num; i++) {
-38
drivers/clk/meson/s4-pll.h
-38
drivers/clk/meson/s4-pll.h
···
1
-
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2
-
/*
3
-
* Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
4
-
* Author: Yu Tu <yu.tu@amlogic.com>
5
-
*/
6
-
7
-
#ifndef __MESON_S4_PLL_H__
8
-
#define __MESON_S4_PLL_H__
9
-
10
-
#define ANACTRL_FIXPLL_CTRL0 0x040
11
-
#define ANACTRL_FIXPLL_CTRL1 0x044
12
-
#define ANACTRL_FIXPLL_CTRL3 0x04c
13
-
#define ANACTRL_GP0PLL_CTRL0 0x080
14
-
#define ANACTRL_GP0PLL_CTRL1 0x084
15
-
#define ANACTRL_GP0PLL_CTRL2 0x088
16
-
#define ANACTRL_GP0PLL_CTRL3 0x08c
17
-
#define ANACTRL_GP0PLL_CTRL4 0x090
18
-
#define ANACTRL_GP0PLL_CTRL5 0x094
19
-
#define ANACTRL_GP0PLL_CTRL6 0x098
20
-
#define ANACTRL_HIFIPLL_CTRL0 0x100
21
-
#define ANACTRL_HIFIPLL_CTRL1 0x104
22
-
#define ANACTRL_HIFIPLL_CTRL2 0x108
23
-
#define ANACTRL_HIFIPLL_CTRL3 0x10c
24
-
#define ANACTRL_HIFIPLL_CTRL4 0x110
25
-
#define ANACTRL_HIFIPLL_CTRL5 0x114
26
-
#define ANACTRL_HIFIPLL_CTRL6 0x118
27
-
#define ANACTRL_MPLL_CTRL0 0x180
28
-
#define ANACTRL_MPLL_CTRL1 0x184
29
-
#define ANACTRL_MPLL_CTRL2 0x188
30
-
#define ANACTRL_MPLL_CTRL3 0x18c
31
-
#define ANACTRL_MPLL_CTRL4 0x190
32
-
#define ANACTRL_MPLL_CTRL5 0x194
33
-
#define ANACTRL_MPLL_CTRL6 0x198
34
-
#define ANACTRL_MPLL_CTRL7 0x19c
35
-
#define ANACTRL_MPLL_CTRL8 0x1a0
36
-
#define ANACTRL_HDMIPLL_CTRL0 0x1c0
37
-
38
-
#endif /* __MESON_S4_PLL_H__ */
+5
drivers/clk/meson/sclk-div.c
+5
drivers/clk/meson/sclk-div.c
···
222
222
struct clk_regmap *clk = to_clk_regmap(hw);
223
223
struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
224
224
unsigned int val;
225
+
int ret;
226
+
227
+
ret = clk_regmap_init(hw);
228
+
if (ret)
229
+
return ret;
225
230
226
231
val = meson_parm_read(clk->map, &sclk->div);
227
232
+2
drivers/clk/meson/vclk.c
+2
drivers/clk/meson/vclk.c
···
45
45
}
46
46
47
47
const struct clk_ops meson_vclk_gate_ops = {
48
+
.init = clk_regmap_init,
48
49
.enable = meson_vclk_gate_enable,
49
50
.disable = meson_vclk_gate_disable,
50
51
.is_enabled = meson_vclk_gate_is_enabled,
···
128
127
}
129
128
130
129
const struct clk_ops meson_vclk_div_ops = {
130
+
.init = clk_regmap_init,
131
131
.recalc_rate = meson_vclk_div_recalc_rate,
132
132
.determine_rate = meson_vclk_div_determine_rate,
133
133
.set_rate = meson_vclk_div_set_rate,
+1
drivers/clk/meson/vid-pll-div.c
+1
drivers/clk/meson/vid-pll-div.c
+10
drivers/clk/renesas/Kconfig
+10
drivers/clk/renesas/Kconfig
···
43
43
select CLK_R9A09G047 if ARCH_R9A09G047
44
44
select CLK_R9A09G056 if ARCH_R9A09G056
45
45
select CLK_R9A09G057 if ARCH_R9A09G057
46
+
select CLK_R9A09G077 if ARCH_R9A09G077
47
+
select CLK_R9A09G087 if ARCH_R9A09G087
46
48
select CLK_SH73A0 if ARCH_SH73A0
47
49
48
50
if CLK_RENESAS
···
209
207
config CLK_R9A09G057
210
208
bool "RZ/V2H(P) clock support" if COMPILE_TEST
211
209
select CLK_RZV2H
210
+
211
+
config CLK_R9A09G077
212
+
bool "RZ/T2H clock support" if COMPILE_TEST
213
+
select CLK_RENESAS_CPG_MSSR
214
+
215
+
config CLK_R9A09G087
216
+
bool "RZ/N2H clock support" if COMPILE_TEST
217
+
select CLK_RENESAS_CPG_MSSR
212
218
213
219
config CLK_SH73A0
214
220
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
+2
drivers/clk/renesas/Makefile
+2
drivers/clk/renesas/Makefile
···
40
40
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
41
41
obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
42
42
obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
43
+
obj-$(CONFIG_CLK_R9A09G077) += r9a09g077-cpg.o
44
+
obj-$(CONFIG_CLK_R9A09G087) += r9a09g077-cpg.o
43
45
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
44
46
45
47
# Family
+4
-3
drivers/clk/renesas/r7s9210-cpg-mssr.c
+4
-3
drivers/clk/renesas/r7s9210-cpg-mssr.c
···
159
159
160
160
static struct clk * __init rza2_cpg_clk_register(struct device *dev,
161
161
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
162
-
struct clk **clks, void __iomem *base,
163
-
struct raw_notifier_head *notifiers)
162
+
struct cpg_mssr_pub *pub)
164
163
{
165
-
struct clk *parent;
164
+
void __iomem *base = pub->base0;
165
+
struct clk **clks = pub->clks;
166
166
unsigned int mult = 1;
167
167
unsigned int div = 1;
168
+
struct clk *parent;
168
169
169
170
parent = clks[core->parent];
170
171
if (IS_ERR(parent))
+4
-4
drivers/clk/renesas/r8a77970-cpg-mssr.c
+4
-4
drivers/clk/renesas/r8a77970-cpg-mssr.c
···
219
219
220
220
static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
221
221
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
222
-
struct clk **clks, void __iomem *base,
223
-
struct raw_notifier_head *notifiers)
222
+
struct cpg_mssr_pub *pub)
224
223
{
225
224
const struct clk_div_table *table;
225
+
void __iomem *base = pub->base0;
226
+
struct clk **clks = pub->clks;
226
227
const struct clk *parent;
227
228
unsigned int shift;
228
229
···
237
236
shift = 4;
238
237
break;
239
238
default:
240
-
return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
241
-
notifiers);
239
+
return rcar_gen3_cpg_clk_register(dev, core, info, pub);
242
240
}
243
241
244
242
parent = clks[core->parent];
+66
-66
drivers/clk/renesas/r9a07g043-cpg.c
+66
-66
drivers/clk/renesas/r9a07g043-cpg.c
···
164
164
static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
165
165
#ifdef CONFIG_ARM64
166
166
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
167
-
0x514, 0),
167
+
0x514, 0, 0),
168
168
DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
169
-
0x518, 0),
169
+
0x518, 0, 0),
170
170
DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
171
-
0x518, 1),
171
+
0x518, 1, 0),
172
172
#endif
173
173
#ifdef CONFIG_RISCV
174
174
DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
175
-
0x518, 0),
175
+
0x518, 0, 0),
176
176
DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
177
-
0x518, 1),
177
+
0x518, 1, 0),
178
178
#endif
179
179
DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
180
-
0x52c, 0),
180
+
0x52c, 0, 0),
181
181
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
182
-
0x52c, 1),
182
+
0x52c, 1, 0),
183
183
DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
184
-
0x534, 0),
184
+
0x534, 0, 0),
185
185
DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
186
-
0x534, 1),
186
+
0x534, 1, 0),
187
187
DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
188
-
0x534, 2),
188
+
0x534, 2, 0),
189
189
DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0,
190
-
0x538, 0),
190
+
0x538, 0, 0),
191
191
DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
192
-
0x548, 0),
192
+
0x548, 0, 0),
193
193
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
194
-
0x548, 1),
194
+
0x548, 1, 0),
195
195
DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
196
-
0x550, 0),
196
+
0x550, 0, 0),
197
197
DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
198
-
0x550, 1),
198
+
0x550, 1, 0),
199
199
DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
200
-
0x554, 0),
200
+
0x554, 0, 0),
201
201
DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
202
-
0x554, 1),
202
+
0x554, 1, 0),
203
203
DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0,
204
-
0x554, 2),
204
+
0x554, 2, 0),
205
205
DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1,
206
-
0x554, 3),
206
+
0x554, 3, 0),
207
207
DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4,
208
-
0x554, 4),
208
+
0x554, 4, 0),
209
209
DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4,
210
-
0x554, 5),
210
+
0x554, 5, 0),
211
211
DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1,
212
-
0x554, 6),
212
+
0x554, 6, 0),
213
213
DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
214
-
0x554, 7),
214
+
0x554, 7, 0),
215
215
#ifdef CONFIG_ARM64
216
216
DEF_MOD("cru_sysclk", R9A07G043_CRU_SYSCLK, CLK_M2_DIV2,
217
-
0x564, 0),
217
+
0x564, 0, 0),
218
218
DEF_MOD("cru_vclk", R9A07G043_CRU_VCLK, R9A07G043_CLK_M2,
219
-
0x564, 1),
219
+
0x564, 1, 0),
220
220
DEF_MOD("cru_pclk", R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT,
221
-
0x564, 2),
221
+
0x564, 2, 0),
222
222
DEF_MOD("cru_aclk", R9A07G043_CRU_ACLK, R9A07G043_CLK_M0,
223
-
0x564, 3),
223
+
0x564, 3, 0),
224
224
DEF_COUPLED("lcdc_clk_a", R9A07G043_LCDC_CLK_A, R9A07G043_CLK_M0,
225
-
0x56c, 0),
225
+
0x56c, 0, 0),
226
226
DEF_COUPLED("lcdc_clk_p", R9A07G043_LCDC_CLK_P, R9A07G043_CLK_ZT,
227
-
0x56c, 0),
227
+
0x56c, 0, 0),
228
228
DEF_MOD("lcdc_clk_d", R9A07G043_LCDC_CLK_D, R9A07G043_CLK_M3,
229
-
0x56c, 1),
229
+
0x56c, 1, 0),
230
230
#endif
231
231
DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0,
232
-
0x570, 0),
232
+
0x570, 0, 0),
233
233
DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0,
234
-
0x570, 1),
234
+
0x570, 1, 0),
235
235
DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0,
236
-
0x570, 2),
236
+
0x570, 2, 0),
237
237
DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0,
238
-
0x570, 3),
238
+
0x570, 3, 0),
239
239
DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0,
240
-
0x570, 4),
240
+
0x570, 4, 0),
241
241
DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0,
242
-
0x570, 5),
242
+
0x570, 5, 0),
243
243
DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0,
244
-
0x570, 6),
244
+
0x570, 6, 0),
245
245
DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
246
-
0x570, 7),
246
+
0x570, 7, 0),
247
247
DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,
248
-
0x578, 0),
248
+
0x578, 0, 0),
249
249
DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,
250
-
0x578, 1),
250
+
0x578, 1, 0),
251
251
DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,
252
-
0x578, 2),
252
+
0x578, 2, 0),
253
253
DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1,
254
-
0x578, 3),
254
+
0x578, 3, 0),
255
255
DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
256
-
0x57c, 0),
256
+
0x57c, 0, 0),
257
257
DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
258
-
0x57c, 0),
258
+
0x57c, 0, 0),
259
259
DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,
260
-
0x57c, 1),
260
+
0x57c, 1, 0),
261
261
DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
262
-
0x57c, 1),
262
+
0x57c, 1, 0),
263
263
DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0,
264
-
0x580, 0),
264
+
0x580, 0, 0),
265
265
DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0,
266
-
0x580, 1),
266
+
0x580, 1, 0),
267
267
DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0,
268
-
0x580, 2),
268
+
0x580, 2, 0),
269
269
DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0,
270
-
0x580, 3),
270
+
0x580, 3, 0),
271
271
DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
272
-
0x584, 0),
272
+
0x584, 0, 0),
273
273
DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
274
-
0x584, 1),
274
+
0x584, 1, 0),
275
275
DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,
276
-
0x584, 2),
276
+
0x584, 2, 0),
277
277
DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,
278
-
0x584, 3),
278
+
0x584, 3, 0),
279
279
DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,
280
-
0x584, 4),
280
+
0x584, 4, 0),
281
281
DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,
282
-
0x588, 0),
282
+
0x588, 0, 0),
283
283
DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
284
-
0x588, 1),
284
+
0x588, 1, 0),
285
285
DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0,
286
-
0x590, 0),
286
+
0x590, 0, 0),
287
287
DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0,
288
-
0x590, 1),
288
+
0x590, 1, 0),
289
289
DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0,
290
-
0x590, 2),
290
+
0x590, 2, 0),
291
291
DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
292
-
0x594, 0),
292
+
0x594, 0, 0),
293
293
DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
294
-
0x598, 0),
294
+
0x598, 0, 0),
295
295
DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU,
296
-
0x5a8, 0),
296
+
0x5a8, 0, 0),
297
297
DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0,
298
-
0x5a8, 1),
298
+
0x5a8, 1, 0),
299
299
DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
300
-
0x5ac, 0),
300
+
0x5ac, 0, 0),
301
301
#ifdef CONFIG_RISCV
302
302
DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,
303
-
0x608, 0),
303
+
0x608, 0, 0),
304
304
#endif
305
305
};
306
306
+84
-84
drivers/clk/renesas/r9a07g044-cpg.c
+84
-84
drivers/clk/renesas/r9a07g044-cpg.c
···
242
242
} mod_clks = {
243
243
.common = {
244
244
DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
245
-
0x514, 0),
245
+
0x514, 0, 0),
246
246
DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
247
-
0x518, 0),
247
+
0x518, 0, 0),
248
248
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
249
-
0x518, 1),
249
+
0x518, 1, 0),
250
250
DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
251
-
0x52c, 0),
251
+
0x52c, 0, 0),
252
252
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
253
-
0x52c, 1),
253
+
0x52c, 1, 0),
254
254
DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
255
-
0x534, 0),
255
+
0x534, 0, 0),
256
256
DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
257
-
0x534, 1),
257
+
0x534, 1, 0),
258
258
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
259
-
0x534, 2),
259
+
0x534, 2, 0),
260
260
DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
261
-
0x538, 0),
261
+
0x538, 0, 0),
262
262
DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
263
-
0x540, 0),
263
+
0x540, 0, 0),
264
264
DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
265
-
0x544, 0),
265
+
0x544, 0, 0),
266
266
DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
267
-
0x544, 1),
267
+
0x544, 1, 0),
268
268
DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
269
-
0x544, 2),
269
+
0x544, 2, 0),
270
270
DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
271
-
0x544, 3),
271
+
0x544, 3, 0),
272
272
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
273
-
0x548, 0),
273
+
0x548, 0, 0),
274
274
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
275
-
0x548, 1),
275
+
0x548, 1, 0),
276
276
DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
277
-
0x548, 2),
277
+
0x548, 2, 0),
278
278
DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
279
-
0x548, 3),
279
+
0x548, 3, 0),
280
280
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
281
-
0x550, 0),
281
+
0x550, 0, 0),
282
282
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
283
-
0x550, 1),
283
+
0x550, 1, 0),
284
284
DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
285
-
0x554, 0),
285
+
0x554, 0, 0),
286
286
DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
287
-
0x554, 1),
287
+
0x554, 1, 0),
288
288
DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
289
-
0x554, 2),
289
+
0x554, 2, 0),
290
290
DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
291
-
0x554, 3),
291
+
0x554, 3, 0),
292
292
DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
293
-
0x554, 4),
293
+
0x554, 4, 0),
294
294
DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
295
-
0x554, 5),
295
+
0x554, 5, 0),
296
296
DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
297
-
0x554, 6),
297
+
0x554, 6, 0),
298
298
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
299
-
0x554, 7),
299
+
0x554, 7, 0),
300
300
DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
301
-
0x558, 0),
301
+
0x558, 0, 0),
302
302
DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
303
-
0x558, 1),
303
+
0x558, 1, 0),
304
304
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
305
-
0x558, 2),
305
+
0x558, 2, 0),
306
306
DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
307
-
0x564, 0),
307
+
0x564, 0, 0),
308
308
DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
309
-
0x564, 1),
309
+
0x564, 1, 0),
310
310
DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
311
-
0x564, 2),
311
+
0x564, 2, 0),
312
312
DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
313
-
0x564, 3),
313
+
0x564, 3, 0),
314
314
DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
315
-
0x568, 0),
315
+
0x568, 0, 0),
316
316
DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
317
-
0x568, 1),
317
+
0x568, 1, 0),
318
318
DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
319
-
0x568, 2),
319
+
0x568, 2, 0),
320
320
DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
321
-
0x568, 3),
321
+
0x568, 3, 0),
322
322
DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
323
-
0x568, 4),
323
+
0x568, 4, 0),
324
324
DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
325
-
0x568, 5),
325
+
0x568, 5, 0),
326
326
DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
327
-
0x56c, 0),
327
+
0x56c, 0, 0),
328
328
DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
329
-
0x56c, 0),
329
+
0x56c, 0, 0),
330
330
DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3,
331
-
0x56c, 1),
331
+
0x56c, 1, 0),
332
332
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
333
-
0x570, 0),
333
+
0x570, 0, 0),
334
334
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
335
-
0x570, 1),
335
+
0x570, 1, 0),
336
336
DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
337
-
0x570, 2),
337
+
0x570, 2, 0),
338
338
DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
339
-
0x570, 3),
339
+
0x570, 3, 0),
340
340
DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
341
-
0x570, 4),
341
+
0x570, 4, 0),
342
342
DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
343
-
0x570, 5),
343
+
0x570, 5, 0),
344
344
DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
345
-
0x570, 6),
345
+
0x570, 6, 0),
346
346
DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
347
-
0x570, 7),
347
+
0x570, 7, 0),
348
348
DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
349
-
0x578, 0),
349
+
0x578, 0, 0),
350
350
DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
351
-
0x578, 1),
351
+
0x578, 1, 0),
352
352
DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
353
-
0x578, 2),
353
+
0x578, 2, 0),
354
354
DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
355
-
0x578, 3),
355
+
0x578, 3, 0),
356
356
DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
357
-
0x57c, 0),
357
+
0x57c, 0, 0),
358
358
DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
359
-
0x57c, 0),
359
+
0x57c, 0, 0),
360
360
DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
361
-
0x57c, 1),
361
+
0x57c, 1, 0),
362
362
DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
363
-
0x57c, 1),
363
+
0x57c, 1, 0),
364
364
DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
365
-
0x580, 0),
365
+
0x580, 0, 0),
366
366
DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
367
-
0x580, 1),
367
+
0x580, 1, 0),
368
368
DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
369
-
0x580, 2),
369
+
0x580, 2, 0),
370
370
DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
371
-
0x580, 3),
371
+
0x580, 3, 0),
372
372
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
373
-
0x584, 0),
373
+
0x584, 0, 0),
374
374
DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
375
-
0x584, 1),
375
+
0x584, 1, 0),
376
376
DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
377
-
0x584, 2),
377
+
0x584, 2, 0),
378
378
DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
379
-
0x584, 3),
379
+
0x584, 3, 0),
380
380
DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
381
-
0x584, 4),
381
+
0x584, 4, 0),
382
382
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
383
-
0x588, 0),
383
+
0x588, 0, 0),
384
384
DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
385
-
0x588, 1),
385
+
0x588, 1, 0),
386
386
DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
387
-
0x590, 0),
387
+
0x590, 0, 0),
388
388
DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
389
-
0x590, 1),
389
+
0x590, 1, 0),
390
390
DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
391
-
0x590, 2),
391
+
0x590, 2, 0),
392
392
DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
393
-
0x594, 0),
393
+
0x594, 0, 0),
394
394
DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
395
-
0x598, 0),
395
+
0x598, 0, 0),
396
396
DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
397
-
0x5a8, 0),
397
+
0x5a8, 0, 0),
398
398
DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
399
-
0x5a8, 1),
399
+
0x5a8, 1, 0),
400
400
DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
401
-
0x5ac, 0),
401
+
0x5ac, 0, 0),
402
402
},
403
403
#ifdef CONFIG_CLK_R9A07G054
404
404
.drp = {
405
405
DEF_MOD("stpai_initclk", R9A07G054_STPAI_INITCLK, R9A07G044_OSCCLK,
406
-
0x5e8, 0),
406
+
0x5e8, 0, 0),
407
407
DEF_MOD("stpai_aclk", R9A07G054_STPAI_ACLK, R9A07G044_CLK_P1,
408
-
0x5e8, 1),
408
+
0x5e8, 1, 0),
409
409
DEF_MOD("stpai_mclk", R9A07G054_STPAI_MCLK, R9A07G054_CLK_DRP_M,
410
-
0x5e8, 2),
410
+
0x5e8, 2, 0),
411
411
DEF_MOD("stpai_dclkin", R9A07G054_STPAI_DCLKIN, R9A07G054_CLK_DRP_D,
412
-
0x5e8, 3),
412
+
0x5e8, 3, 0),
413
413
DEF_MOD("stpai_aclk_drp", R9A07G054_STPAI_ACLK_DRP, R9A07G054_CLK_DRP_A,
414
-
0x5e8, 4),
414
+
0x5e8, 4, 0),
415
415
},
416
416
#endif
417
417
};
+101
-128
drivers/clk/renesas/r9a08g045-cpg.c
+101
-128
drivers/clk/renesas/r9a08g045-cpg.c
···
192
192
};
193
193
194
194
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
195
-
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
196
-
DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
197
-
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
198
-
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
199
-
DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1),
200
-
DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0),
201
-
DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1),
202
-
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
203
-
DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1),
204
-
DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2),
205
-
DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3),
206
-
DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4),
207
-
DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5),
208
-
DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6),
209
-
DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7),
210
-
DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8),
211
-
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
212
-
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
213
-
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
214
-
DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0),
215
-
DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1),
216
-
DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2),
217
-
DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3),
218
-
DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4),
219
-
DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5),
220
-
DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6),
221
-
DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7),
222
-
DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0),
223
-
DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1),
224
-
DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2),
225
-
DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3),
226
-
DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0),
227
-
DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0),
228
-
DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8),
229
-
DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
230
-
DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
231
-
DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
232
-
DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0),
233
-
DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1),
234
-
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
235
-
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
236
-
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
237
-
DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1),
238
-
DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2),
239
-
DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3),
240
-
DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4),
241
-
DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5),
242
-
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
243
-
DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0),
244
-
DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1),
245
-
DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0),
246
-
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
195
+
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0,
196
+
MSTOP(BUS_ACPU, BIT(3))),
197
+
DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0,
198
+
MSTOP(BUS_PERI_CPU, BIT(13))),
199
+
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1,
200
+
MSTOP(BUS_PERI_CPU, BIT(13))),
201
+
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0,
202
+
MSTOP(BUS_REG1, BIT(2))),
203
+
DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1,
204
+
MSTOP(BUS_REG1, BIT(3))),
205
+
DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0,
206
+
MSTOP(BUS_REG0, BIT(0))),
207
+
DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1,
208
+
MSTOP(BUS_REG0, BIT(0))),
209
+
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0,
210
+
MSTOP(BUS_PERI_COM, BIT(0))),
211
+
DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1,
212
+
MSTOP(BUS_PERI_COM, BIT(0))),
213
+
DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2,
214
+
MSTOP(BUS_PERI_COM, BIT(0))),
215
+
DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3,
216
+
MSTOP(BUS_PERI_COM, BIT(0))),
217
+
DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4,
218
+
MSTOP(BUS_PERI_COM, BIT(1))),
219
+
DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5,
220
+
MSTOP(BUS_PERI_COM, BIT(1))),
221
+
DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6,
222
+
MSTOP(BUS_PERI_COM, BIT(1))),
223
+
DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7,
224
+
MSTOP(BUS_PERI_COM, BIT(1))),
225
+
DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8,
226
+
MSTOP(BUS_PERI_COM, BIT(11))),
227
+
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9,
228
+
MSTOP(BUS_PERI_COM, BIT(11))),
229
+
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10,
230
+
MSTOP(BUS_PERI_COM, BIT(11))),
231
+
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11,
232
+
MSTOP(BUS_PERI_COM, BIT(11))),
233
+
DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0,
234
+
MSTOP(BUS_MCPU1, BIT(10))),
235
+
DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1,
236
+
MSTOP(BUS_MCPU1, BIT(10))),
237
+
DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2,
238
+
MSTOP(BUS_MCPU1, BIT(11))),
239
+
DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3,
240
+
MSTOP(BUS_MCPU1, BIT(11))),
241
+
DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4,
242
+
MSTOP(BUS_MCPU1, BIT(12))),
243
+
DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5,
244
+
MSTOP(BUS_MCPU1, BIT(12))),
245
+
DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6,
246
+
MSTOP(BUS_MCPU1, BIT(13))),
247
+
DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7,
248
+
MSTOP(BUS_MCPU1, BIT(13))),
249
+
DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0,
250
+
MSTOP(BUS_PERI_COM, BIT(5))),
251
+
DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1,
252
+
MSTOP(BUS_PERI_COM, BIT(7))),
253
+
DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2,
254
+
MSTOP(BUS_PERI_COM, BIT(6))),
255
+
DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3,
256
+
MSTOP(BUS_PERI_COM, BIT(4))),
257
+
DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0,
258
+
MSTOP(BUS_PERI_COM, BIT(2))),
259
+
DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0,
260
+
MSTOP(BUS_PERI_COM, BIT(2))),
261
+
DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8, 0),
262
+
DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1,
263
+
MSTOP(BUS_PERI_COM, BIT(3))),
264
+
DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1,
265
+
MSTOP(BUS_PERI_COM, BIT(3))),
266
+
DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9, 0),
267
+
DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0,
268
+
MSTOP(BUS_MCPU2, BIT(10))),
269
+
DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1,
270
+
MSTOP(BUS_MCPU2, BIT(11))),
271
+
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2,
272
+
MSTOP(BUS_MCPU2, BIT(12))),
273
+
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3,
274
+
MSTOP(BUS_MCPU2, BIT(13))),
275
+
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0,
276
+
MSTOP(BUS_MCPU2, BIT(1))),
277
+
DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1,
278
+
MSTOP(BUS_MCPU2, BIT(2))),
279
+
DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2,
280
+
MSTOP(BUS_MCPU2, BIT(3))),
281
+
DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3,
282
+
MSTOP(BUS_MCPU2, BIT(4))),
283
+
DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4,
284
+
MSTOP(BUS_MCPU2, BIT(5))),
285
+
DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5,
286
+
MSTOP(BUS_MCPU3, BIT(4))),
287
+
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, 0),
288
+
DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0,
289
+
MSTOP(BUS_MCPU2, BIT(14))),
290
+
DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1,
291
+
MSTOP(BUS_MCPU2, BIT(14))),
292
+
DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0,
293
+
MSTOP(BUS_MCPU2, BIT(15))),
294
+
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0,
295
+
MSTOP(BUS_MCPU3, GENMASK(8, 7))),
247
296
};
248
297
249
298
static const struct rzg2l_reset r9a08g045_resets[] = {
···
342
293
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
343
294
};
344
295
345
-
static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
346
-
/* Keep always-on domain on the first position for proper domains registration. */
347
-
DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
348
-
DEF_REG_CONF(0, 0),
349
-
GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE),
350
-
DEF_PD("gic", R9A08G045_PD_GIC,
351
-
DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
352
-
GENPD_FLAG_ALWAYS_ON),
353
-
DEF_PD("ia55", R9A08G045_PD_IA55,
354
-
DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
355
-
GENPD_FLAG_ALWAYS_ON),
356
-
DEF_PD("dmac", R9A08G045_PD_DMAC,
357
-
DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
358
-
GENPD_FLAG_ALWAYS_ON),
359
-
DEF_PD("wdt0", R9A08G045_PD_WDT0,
360
-
DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
361
-
GENPD_FLAG_IRQ_SAFE),
362
-
DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
363
-
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0),
364
-
DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
365
-
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0),
366
-
DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
367
-
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0),
368
-
DEF_PD("ssi0", R9A08G045_PD_SSI0,
369
-
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0),
370
-
DEF_PD("ssi1", R9A08G045_PD_SSI1,
371
-
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0),
372
-
DEF_PD("ssi2", R9A08G045_PD_SSI2,
373
-
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0),
374
-
DEF_PD("ssi3", R9A08G045_PD_SSI3,
375
-
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0),
376
-
DEF_PD("usb0", R9A08G045_PD_USB0,
377
-
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0),
378
-
DEF_PD("usb1", R9A08G045_PD_USB1,
379
-
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)), 0),
380
-
DEF_PD("usb-phy", R9A08G045_PD_USB_PHY,
381
-
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)), 0),
382
-
DEF_PD("eth0", R9A08G045_PD_ETHER0,
383
-
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), 0),
384
-
DEF_PD("eth1", R9A08G045_PD_ETHER1,
385
-
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), 0),
386
-
DEF_PD("i2c0", R9A08G045_PD_I2C0,
387
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), 0),
388
-
DEF_PD("i2c1", R9A08G045_PD_I2C1,
389
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), 0),
390
-
DEF_PD("i2c2", R9A08G045_PD_I2C2,
391
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), 0),
392
-
DEF_PD("i2c3", R9A08G045_PD_I2C3,
393
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0),
394
-
DEF_PD("scif0", R9A08G045_PD_SCIF0,
395
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0),
396
-
DEF_PD("scif1", R9A08G045_PD_SCIF1,
397
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)), 0),
398
-
DEF_PD("scif2", R9A08G045_PD_SCIF2,
399
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)), 0),
400
-
DEF_PD("scif3", R9A08G045_PD_SCIF3,
401
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)), 0),
402
-
DEF_PD("scif4", R9A08G045_PD_SCIF4,
403
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0),
404
-
DEF_PD("scif5", R9A08G045_PD_SCIF5,
405
-
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0),
406
-
DEF_PD("adc", R9A08G045_PD_ADC,
407
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0),
408
-
DEF_PD("tsu", R9A08G045_PD_TSU,
409
-
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0),
410
-
DEF_PD("vbat", R9A08G045_PD_VBAT,
411
-
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
412
-
GENPD_FLAG_ALWAYS_ON),
413
-
DEF_PD("rtc", R9A08G045_PD_RTC,
414
-
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), 0),
415
-
};
416
-
417
296
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
418
297
/* Core Clocks */
419
298
.core_clks = r9a08g045_core_clks,
···
361
384
/* Resets */
362
385
.resets = r9a08g045_resets,
363
386
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
364
-
365
-
/* Power domains */
366
-
.pm_domains = r9a08g045_pm_domains,
367
-
.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
368
387
369
388
.has_clk_mon_regs = true,
370
389
};
+58
-58
drivers/clk/renesas/r9a09g011-cpg.c
+58
-58
drivers/clk/renesas/r9a09g011-cpg.c
···
151
151
};
152
152
153
153
static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
154
-
DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
155
-
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
156
-
DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0),
157
-
DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1),
158
-
DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2),
159
-
DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3),
160
-
DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4),
161
-
DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5),
162
-
DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6),
163
-
DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7),
164
-
DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8),
165
-
DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9),
166
-
DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10),
167
-
DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11),
168
-
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
169
-
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
170
-
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
171
-
DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4),
172
-
DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5),
173
-
DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6),
174
-
DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
175
-
DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12),
176
-
DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0),
177
-
DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4),
178
-
DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5),
179
-
DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6),
180
-
DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7),
181
-
DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8),
182
-
DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9),
183
-
DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10),
184
-
DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11),
185
-
DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12),
186
-
DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0),
187
-
DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4),
188
-
DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5),
189
-
DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6),
190
-
DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7),
191
-
DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8),
192
-
DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9),
193
-
DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10),
194
-
DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11),
195
-
DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12),
196
-
DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13),
197
-
DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0),
198
-
DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4),
199
-
DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5),
200
-
DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6),
201
-
DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7),
202
-
DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8),
203
-
DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9),
204
-
DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10),
205
-
DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0),
206
-
DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1),
207
-
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
208
-
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
209
-
DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8),
210
-
DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12),
211
-
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
154
+
DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2, 0),
155
+
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5, 0),
156
+
DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0, 0),
157
+
DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1, 0),
158
+
DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2, 0),
159
+
DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3, 0),
160
+
DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4, 0),
161
+
DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5, 0),
162
+
DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6, 0),
163
+
DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7, 0),
164
+
DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8, 0),
165
+
DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9, 0),
166
+
DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10, 0),
167
+
DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11, 0),
168
+
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8, 0),
169
+
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8, 0),
170
+
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9, 0),
171
+
DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4, 0),
172
+
DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5, 0),
173
+
DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6, 0),
174
+
DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12, 0),
175
+
DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12, 0),
176
+
DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0, 0),
177
+
DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4, 0),
178
+
DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5, 0),
179
+
DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6, 0),
180
+
DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7, 0),
181
+
DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8, 0),
182
+
DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9, 0),
183
+
DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10, 0),
184
+
DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11, 0),
185
+
DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12, 0),
186
+
DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0, 0),
187
+
DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4, 0),
188
+
DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5, 0),
189
+
DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6, 0),
190
+
DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7, 0),
191
+
DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8, 0),
192
+
DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9, 0),
193
+
DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10, 0),
194
+
DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11, 0),
195
+
DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12, 0),
196
+
DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13, 0),
197
+
DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0, 0),
198
+
DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4, 0),
199
+
DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5, 0),
200
+
DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6, 0),
201
+
DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7, 0),
202
+
DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8, 0),
203
+
DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9, 0),
204
+
DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10, 0),
205
+
DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0, 0),
206
+
DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1, 0),
207
+
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4, 0),
208
+
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5, 0),
209
+
DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8, 0),
210
+
DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12, 0),
211
+
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0, 0),
212
212
};
213
213
214
214
static const struct rzg2l_reset r9a09g011_resets[] = {
+72
drivers/clk/renesas/r9a09g047-cpg.c
+72
drivers/clk/renesas/r9a09g047-cpg.c
···
29
29
CLK_PLLDTY,
30
30
CLK_PLLCA55,
31
31
CLK_PLLVDO,
32
+
CLK_PLLETH,
32
33
33
34
/* Internal Core Clocks */
34
35
CLK_PLLCM33_DIV3,
···
47
46
CLK_PLLDTY_ACPU,
48
47
CLK_PLLDTY_ACPU_DIV2,
49
48
CLK_PLLDTY_ACPU_DIV4,
49
+
CLK_PLLDTY_DIV8,
50
+
CLK_PLLETH_DIV_250_FIX,
51
+
CLK_PLLETH_DIV_125_FIX,
52
+
CLK_CSDIV_PLLETH_GBE0,
53
+
CLK_CSDIV_PLLETH_GBE1,
54
+
CLK_SMUX2_GBE0_TXCLK,
55
+
CLK_SMUX2_GBE0_RXCLK,
56
+
CLK_SMUX2_GBE1_TXCLK,
57
+
CLK_SMUX2_GBE1_RXCLK,
50
58
CLK_PLLDTY_DIV16,
51
59
CLK_PLLVDO_CRU0,
52
60
CLK_PLLVDO_GPU,
···
95
85
{0, 0},
96
86
};
97
87
88
+
static const struct clk_div_table dtable_2_100[] = {
89
+
{0, 2},
90
+
{1, 10},
91
+
{2, 100},
92
+
{0, 0},
93
+
};
94
+
98
95
/* Mux clock tables */
96
+
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
97
+
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
98
+
static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
99
+
static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
99
100
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
100
101
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
101
102
···
121
100
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
122
101
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
123
102
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
103
+
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
124
104
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
125
105
126
106
/* Internal Core Clocks */
···
144
122
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
145
123
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
146
124
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
125
+
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
126
+
127
+
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
128
+
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
129
+
DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX,
130
+
CSDIV0_DIVCTL0, dtable_2_100),
131
+
DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX,
132
+
CSDIV0_DIVCTL1, dtable_2_100),
133
+
DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
134
+
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
135
+
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
136
+
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
147
137
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
148
138
149
139
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
···
173
139
CDDIV1_DIVCTL3, dtable_1_8),
174
140
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
175
141
DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
142
+
DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
143
+
CLK_PLLETH_DIV_125_FIX, 1, 1),
144
+
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
145
+
CLK_PLLETH_DIV_125_FIX, 1, 1),
176
146
};
177
147
178
148
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
···
198
160
BUS_MSTOP(5, BIT(13))),
199
161
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
200
162
BUS_MSTOP(3, BIT(14))),
163
+
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
164
+
BUS_MSTOP(10, BIT(15))),
165
+
DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
166
+
BUS_MSTOP(10, BIT(15))),
167
+
DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
168
+
BUS_MSTOP(10, BIT(15))),
201
169
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
202
170
BUS_MSTOP(3, BIT(13))),
203
171
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
···
258
214
BUS_MSTOP(8, BIT(4))),
259
215
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
260
216
BUS_MSTOP(8, BIT(4))),
217
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
218
+
BUS_MSTOP(8, BIT(5)), 1),
219
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
220
+
BUS_MSTOP(8, BIT(5)), 1),
221
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
222
+
BUS_MSTOP(8, BIT(5)), 1),
223
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
224
+
BUS_MSTOP(8, BIT(5)), 1),
225
+
DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
226
+
BUS_MSTOP(8, BIT(5))),
227
+
DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
228
+
BUS_MSTOP(8, BIT(5))),
229
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
230
+
BUS_MSTOP(8, BIT(6)), 1),
231
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
232
+
BUS_MSTOP(8, BIT(6)), 1),
233
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
234
+
BUS_MSTOP(8, BIT(6)), 1),
235
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
236
+
BUS_MSTOP(8, BIT(6)), 1),
237
+
DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
238
+
BUS_MSTOP(8, BIT(6))),
239
+
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
240
+
BUS_MSTOP(8, BIT(6))),
261
241
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
262
242
BUS_MSTOP(9, BIT(4))),
263
243
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
307
239
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
308
240
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
309
241
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
242
+
DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
243
+
DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
310
244
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
311
245
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
312
246
DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
···
325
255
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
326
256
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
327
257
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
258
+
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
259
+
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
328
260
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
329
261
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
330
262
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+201
-1
drivers/clk/renesas/r9a09g056-cpg.c
+201
-1
drivers/clk/renesas/r9a09g056-cpg.c
···
16
16
17
17
enum clk_ids {
18
18
/* Core Clock Outputs exported to DT */
19
-
LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I,
19
+
LAST_DT_CORE_CLK = R9A09G056_SPI_CLK_SPI,
20
20
21
21
/* External Input Clocks */
22
22
CLK_AUDIO_EXTAL,
···
28
28
CLK_PLLCLN,
29
29
CLK_PLLDTY,
30
30
CLK_PLLCA55,
31
+
CLK_PLLETH,
32
+
CLK_PLLGPU,
31
33
32
34
/* Internal Core Clocks */
35
+
CLK_PLLCM33_DIV3,
36
+
CLK_PLLCM33_DIV4,
37
+
CLK_PLLCM33_DIV5,
33
38
CLK_PLLCM33_DIV16,
39
+
CLK_SMUX2_XSPI_CLK0,
40
+
CLK_SMUX2_XSPI_CLK1,
41
+
CLK_PLLCM33_XSPI,
42
+
CLK_PLLCM33_GEAR,
34
43
CLK_PLLCLN_DIV2,
35
44
CLK_PLLCLN_DIV8,
45
+
CLK_PLLCLN_DIV16,
36
46
CLK_PLLDTY_ACPU,
47
+
CLK_PLLDTY_ACPU_DIV2,
37
48
CLK_PLLDTY_ACPU_DIV4,
49
+
CLK_PLLDTY_DIV8,
50
+
CLK_PLLETH_DIV_250_FIX,
51
+
CLK_PLLETH_DIV_125_FIX,
52
+
CLK_CSDIV_PLLETH_GBE0,
53
+
CLK_CSDIV_PLLETH_GBE1,
54
+
CLK_SMUX2_GBE0_TXCLK,
55
+
CLK_SMUX2_GBE0_RXCLK,
56
+
CLK_SMUX2_GBE1_TXCLK,
57
+
CLK_SMUX2_GBE1_RXCLK,
58
+
CLK_PLLGPU_GEAR,
38
59
39
60
/* Module Clocks */
40
61
MOD_CLK_BASE,
···
69
48
{0, 0},
70
49
};
71
50
51
+
static const struct clk_div_table dtable_2_16[] = {
52
+
{0, 2},
53
+
{1, 4},
54
+
{2, 8},
55
+
{3, 16},
56
+
{0, 0},
57
+
};
58
+
72
59
static const struct clk_div_table dtable_2_64[] = {
73
60
{0, 2},
74
61
{1, 4},
···
85
56
{4, 64},
86
57
{0, 0},
87
58
};
59
+
60
+
static const struct clk_div_table dtable_2_100[] = {
61
+
{0, 2},
62
+
{1, 10},
63
+
{2, 100},
64
+
{0, 0},
65
+
};
66
+
67
+
/* Mux clock tables */
68
+
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
69
+
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
70
+
static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
71
+
static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
72
+
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
73
+
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
88
74
89
75
static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
90
76
/* External Clock Inputs */
···
112
68
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
113
69
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
114
70
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
71
+
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
72
+
DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
115
73
116
74
/* Internal Core Clocks */
75
+
DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
76
+
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
77
+
DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
117
78
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
79
+
DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
80
+
DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
81
+
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
82
+
dtable_2_16),
83
+
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
118
84
119
85
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
120
86
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
87
+
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
121
88
122
89
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
90
+
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
123
91
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
92
+
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
93
+
94
+
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
95
+
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
96
+
DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
97
+
CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
98
+
DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
99
+
CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
100
+
DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
101
+
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
102
+
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
103
+
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
104
+
105
+
DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
124
106
125
107
/* Core Clocks */
126
108
DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
···
159
89
DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
160
90
CDDIV1_DIVCTL3, dtable_1_8),
161
91
DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
92
+
DEF_FIXED("usb2_0_clk_core0", R9A09G056_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
93
+
DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G056_GBETH_0_CLK_PTP_REF_I,
94
+
CLK_PLLETH_DIV_125_FIX, 1, 1),
95
+
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G056_GBETH_1_CLK_PTP_REF_I,
96
+
CLK_PLLETH_DIV_125_FIX, 1, 1),
97
+
DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G056_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
98
+
FIXED_MOD_CONF_XSPI),
162
99
};
163
100
164
101
static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
165
102
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
166
103
BUS_MSTOP(3, BIT(5))),
104
+
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
105
+
BUS_MSTOP(5, BIT(10))),
106
+
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
107
+
BUS_MSTOP(5, BIT(11))),
108
+
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
109
+
BUS_MSTOP(2, BIT(13))),
110
+
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
111
+
BUS_MSTOP(2, BIT(14))),
112
+
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
113
+
BUS_MSTOP(11, BIT(13))),
114
+
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
115
+
BUS_MSTOP(11, BIT(14))),
116
+
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
117
+
BUS_MSTOP(11, BIT(15))),
118
+
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
119
+
BUS_MSTOP(12, BIT(0))),
120
+
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
121
+
BUS_MSTOP(3, BIT(10))),
122
+
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
123
+
BUS_MSTOP(3, BIT(10))),
124
+
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
125
+
BUS_MSTOP(1, BIT(0))),
126
+
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
127
+
BUS_MSTOP(1, BIT(0))),
128
+
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
129
+
BUS_MSTOP(5, BIT(12))),
130
+
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
131
+
BUS_MSTOP(5, BIT(12))),
132
+
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
133
+
BUS_MSTOP(5, BIT(13))),
134
+
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
135
+
BUS_MSTOP(5, BIT(13))),
167
136
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
168
137
BUS_MSTOP(3, BIT(14))),
138
+
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
139
+
BUS_MSTOP(3, BIT(13))),
140
+
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
141
+
BUS_MSTOP(1, BIT(1))),
142
+
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
143
+
BUS_MSTOP(1, BIT(2))),
144
+
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
145
+
BUS_MSTOP(1, BIT(3))),
146
+
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
147
+
BUS_MSTOP(1, BIT(4))),
148
+
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
149
+
BUS_MSTOP(1, BIT(5))),
150
+
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
151
+
BUS_MSTOP(1, BIT(6))),
152
+
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
153
+
BUS_MSTOP(1, BIT(7))),
154
+
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
155
+
BUS_MSTOP(1, BIT(8))),
156
+
DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
157
+
BUS_MSTOP(4, BIT(5))),
158
+
DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
159
+
BUS_MSTOP(4, BIT(5))),
160
+
DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
161
+
BUS_MSTOP(4, BIT(5))),
169
162
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
170
163
BUS_MSTOP(8, BIT(2))),
171
164
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
···
253
120
BUS_MSTOP(8, BIT(4))),
254
121
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
255
122
BUS_MSTOP(8, BIT(4))),
123
+
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
124
+
BUS_MSTOP(7, BIT(7))),
125
+
DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
126
+
BUS_MSTOP(7, BIT(9))),
127
+
DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
128
+
BUS_MSTOP(7, BIT(10))),
129
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
130
+
BUS_MSTOP(8, BIT(5)), 1),
131
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
132
+
BUS_MSTOP(8, BIT(5)), 1),
133
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
134
+
BUS_MSTOP(8, BIT(5)), 1),
135
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
136
+
BUS_MSTOP(8, BIT(5)), 1),
137
+
DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
138
+
BUS_MSTOP(8, BIT(5))),
139
+
DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
140
+
BUS_MSTOP(8, BIT(5))),
141
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
142
+
BUS_MSTOP(8, BIT(6)), 1),
143
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
144
+
BUS_MSTOP(8, BIT(6)), 1),
145
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
146
+
BUS_MSTOP(8, BIT(6)), 1),
147
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
148
+
BUS_MSTOP(8, BIT(6)), 1),
149
+
DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
150
+
BUS_MSTOP(8, BIT(6))),
151
+
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
152
+
BUS_MSTOP(8, BIT(6))),
153
+
DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
154
+
BUS_MSTOP(3, BIT(4))),
155
+
DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
156
+
BUS_MSTOP(3, BIT(4))),
157
+
DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
158
+
BUS_MSTOP(3, BIT(4))),
256
159
};
257
160
258
161
static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
259
162
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
260
163
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
261
164
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
165
+
DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
166
+
DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
167
+
DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
168
+
DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
169
+
DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
170
+
DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
171
+
DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
172
+
DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
173
+
DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
174
+
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
175
+
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
176
+
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
262
177
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
178
+
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
179
+
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
180
+
DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
181
+
DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
182
+
DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
183
+
DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
184
+
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
185
+
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
186
+
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
187
+
DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
188
+
DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
263
189
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
264
190
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
265
191
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
192
+
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
193
+
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
194
+
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
195
+
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
196
+
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
197
+
DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
198
+
DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
199
+
DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
266
200
};
267
201
268
202
const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {
+123
-4
drivers/clk/renesas/r9a09g057-cpg.c
+123
-4
drivers/clk/renesas/r9a09g057-cpg.c
···
16
16
17
17
enum clk_ids {
18
18
/* Core Clock Outputs exported to DT */
19
-
LAST_DT_CORE_CLK = R9A09G057_GBETH_1_CLK_PTP_REF_I,
19
+
LAST_DT_CORE_CLK = R9A09G057_SPI_CLK_SPI,
20
20
21
21
/* External Input Clocks */
22
22
CLK_AUDIO_EXTAL,
···
29
29
CLK_PLLDTY,
30
30
CLK_PLLCA55,
31
31
CLK_PLLVDO,
32
+
CLK_PLLETH,
32
33
CLK_PLLGPU,
33
34
34
35
/* Internal Core Clocks */
36
+
CLK_PLLCM33_DIV3,
35
37
CLK_PLLCM33_DIV4,
36
-
CLK_PLLCM33_DIV4_PLLCM33,
38
+
CLK_PLLCM33_DIV5,
37
39
CLK_PLLCM33_DIV16,
40
+
CLK_PLLCM33_GEAR,
41
+
CLK_SMUX2_XSPI_CLK0,
42
+
CLK_SMUX2_XSPI_CLK1,
43
+
CLK_PLLCM33_XSPI,
38
44
CLK_PLLCLN_DIV2,
39
45
CLK_PLLCLN_DIV8,
40
46
CLK_PLLCLN_DIV16,
···
55
49
CLK_PLLVDO_CRU1,
56
50
CLK_PLLVDO_CRU2,
57
51
CLK_PLLVDO_CRU3,
52
+
CLK_PLLETH_DIV_250_FIX,
53
+
CLK_PLLETH_DIV_125_FIX,
54
+
CLK_CSDIV_PLLETH_GBE0,
55
+
CLK_CSDIV_PLLETH_GBE1,
56
+
CLK_SMUX2_GBE0_TXCLK,
57
+
CLK_SMUX2_GBE0_RXCLK,
58
+
CLK_SMUX2_GBE1_TXCLK,
59
+
CLK_SMUX2_GBE1_RXCLK,
58
60
CLK_PLLGPU_GEAR,
59
61
60
62
/* Module Clocks */
···
83
69
{0, 0},
84
70
};
85
71
72
+
static const struct clk_div_table dtable_2_16[] = {
73
+
{0, 2},
74
+
{1, 4},
75
+
{2, 8},
76
+
{3, 16},
77
+
{0, 0},
78
+
};
79
+
86
80
static const struct clk_div_table dtable_2_64[] = {
87
81
{0, 2},
88
82
{1, 4},
···
99
77
{4, 64},
100
78
{0, 0},
101
79
};
80
+
81
+
static const struct clk_div_table dtable_2_100[] = {
82
+
{0, 2},
83
+
{1, 10},
84
+
{2, 100},
85
+
{0, 0},
86
+
};
87
+
88
+
/* Mux clock tables */
89
+
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
90
+
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
91
+
static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
92
+
static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
93
+
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
94
+
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
102
95
103
96
static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
104
97
/* External Clock Inputs */
···
127
90
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
128
91
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
129
92
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
93
+
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
130
94
DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
131
95
132
96
/* Internal Core Clocks */
97
+
DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
133
98
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
134
-
DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33,
99
+
DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
100
+
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR,
135
101
CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
136
102
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
103
+
DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
104
+
DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
105
+
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
106
+
dtable_2_16),
137
107
138
108
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
139
109
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
···
159
115
DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
160
116
DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
161
117
118
+
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
119
+
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
120
+
DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
121
+
CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
122
+
DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
123
+
CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
124
+
DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
125
+
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
126
+
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
127
+
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
128
+
162
129
DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
163
130
164
131
/* Core Clocks */
···
185
130
DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
186
131
DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
187
132
DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
133
+
DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I,
134
+
CLK_PLLETH_DIV_125_FIX, 1, 1),
135
+
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I,
136
+
CLK_PLLETH_DIV_125_FIX, 1, 1),
137
+
DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
138
+
FIXED_MOD_CONF_XSPI),
188
139
};
189
140
190
141
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
191
-
DEF_MOD("dmac_0_aclk", CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0,
142
+
DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0,
192
143
BUS_MSTOP(5, BIT(9))),
193
144
DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
194
145
BUS_MSTOP(3, BIT(2))),
···
240
179
BUS_MSTOP(5, BIT(13))),
241
180
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
242
181
BUS_MSTOP(5, BIT(13))),
182
+
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
183
+
BUS_MSTOP(11, BIT(0))),
184
+
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
185
+
BUS_MSTOP(11, BIT(0))),
186
+
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
187
+
BUS_MSTOP(11, BIT(0))),
188
+
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
189
+
BUS_MSTOP(11, BIT(1))),
190
+
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
191
+
BUS_MSTOP(11, BIT(1))),
192
+
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
193
+
BUS_MSTOP(11, BIT(1))),
194
+
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
195
+
BUS_MSTOP(11, BIT(2))),
196
+
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
197
+
BUS_MSTOP(11, BIT(2))),
198
+
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
199
+
BUS_MSTOP(11, BIT(2))),
243
200
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
244
201
BUS_MSTOP(3, BIT(14))),
245
202
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
···
278
199
BUS_MSTOP(1, BIT(7))),
279
200
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
280
201
BUS_MSTOP(1, BIT(8))),
202
+
DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
203
+
BUS_MSTOP(4, BIT(5))),
204
+
DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
205
+
BUS_MSTOP(4, BIT(5))),
206
+
DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
207
+
BUS_MSTOP(4, BIT(5))),
281
208
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
282
209
BUS_MSTOP(8, BIT(2))),
283
210
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
···
318
233
BUS_MSTOP(7, BIT(10))),
319
234
DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
320
235
BUS_MSTOP(7, BIT(11))),
236
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
237
+
BUS_MSTOP(8, BIT(5)), 1),
238
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
239
+
BUS_MSTOP(8, BIT(5)), 1),
240
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
241
+
BUS_MSTOP(8, BIT(5)), 1),
242
+
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
243
+
BUS_MSTOP(8, BIT(5)), 1),
244
+
DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
245
+
BUS_MSTOP(8, BIT(5))),
246
+
DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
247
+
BUS_MSTOP(8, BIT(5))),
248
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
249
+
BUS_MSTOP(8, BIT(6)), 1),
250
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
251
+
BUS_MSTOP(8, BIT(6)), 1),
252
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
253
+
BUS_MSTOP(8, BIT(6)), 1),
254
+
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
255
+
BUS_MSTOP(8, BIT(6)), 1),
256
+
DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
257
+
BUS_MSTOP(8, BIT(6))),
258
+
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
259
+
BUS_MSTOP(8, BIT(6))),
321
260
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
322
261
BUS_MSTOP(9, BIT(4))),
323
262
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
396
287
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
397
288
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
398
289
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
290
+
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
291
+
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
292
+
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
293
+
DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
294
+
DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
295
+
DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
399
296
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
400
297
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
401
298
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
···
412
297
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
413
298
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
414
299
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
300
+
DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
301
+
DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
415
302
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
416
303
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
417
304
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
···
421
304
DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
422
305
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
423
306
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
307
+
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
308
+
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
424
309
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
425
310
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
426
311
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+256
drivers/clk/renesas/r9a09g077-cpg.c
+256
drivers/clk/renesas/r9a09g077-cpg.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* r9a09g077 Clock Pulse Generator / Module Standby and Software Reset
4
+
*
5
+
* Copyright (C) 2025 Renesas Electronics Corp.
6
+
*
7
+
*/
8
+
9
+
#include <linux/bitfield.h>
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/device.h>
12
+
#include <linux/init.h>
13
+
#include <linux/kernel.h>
14
+
15
+
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
16
+
#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
17
+
#include "renesas-cpg-mssr.h"
18
+
19
+
#define RZT2H_REG_BLOCK_SHIFT 11
20
+
#define RZT2H_REG_OFFSET_MASK GENMASK(10, 0)
21
+
#define RZT2H_REG_CONF(block, offset) (((block) << RZT2H_REG_BLOCK_SHIFT) | \
22
+
((offset) & RZT2H_REG_OFFSET_MASK))
23
+
24
+
#define RZT2H_REG_BLOCK(x) ((x) >> RZT2H_REG_BLOCK_SHIFT)
25
+
#define RZT2H_REG_OFFSET(x) ((x) & RZT2H_REG_OFFSET_MASK)
26
+
27
+
#define SCKCR RZT2H_REG_CONF(0, 0x00)
28
+
#define SCKCR2 RZT2H_REG_CONF(1, 0x04)
29
+
#define SCKCR3 RZT2H_REG_CONF(0, 0x08)
30
+
31
+
#define OFFSET_MASK GENMASK(31, 20)
32
+
#define SHIFT_MASK GENMASK(19, 12)
33
+
#define WIDTH_MASK GENMASK(11, 8)
34
+
35
+
#define CONF_PACK(offset, shift, width) \
36
+
(FIELD_PREP_CONST(OFFSET_MASK, (offset)) | \
37
+
FIELD_PREP_CONST(SHIFT_MASK, (shift)) | \
38
+
FIELD_PREP_CONST(WIDTH_MASK, (width)))
39
+
40
+
#define GET_SHIFT(val) FIELD_GET(SHIFT_MASK, val)
41
+
#define GET_WIDTH(val) FIELD_GET(WIDTH_MASK, val)
42
+
#define GET_REG_OFFSET(val) FIELD_GET(OFFSET_MASK, val)
43
+
44
+
#define DIVCA55C0 CONF_PACK(SCKCR2, 8, 1)
45
+
#define DIVCA55C1 CONF_PACK(SCKCR2, 9, 1)
46
+
#define DIVCA55C2 CONF_PACK(SCKCR2, 10, 1)
47
+
#define DIVCA55C3 CONF_PACK(SCKCR2, 11, 1)
48
+
#define DIVCA55S CONF_PACK(SCKCR2, 12, 1)
49
+
50
+
#define DIVSCI0ASYNC CONF_PACK(SCKCR3, 6, 2)
51
+
52
+
#define SEL_PLL CONF_PACK(SCKCR, 22, 1)
53
+
54
+
55
+
enum rzt2h_clk_types {
56
+
CLK_TYPE_RZT2H_DIV = CLK_TYPE_CUSTOM, /* Clock with divider */
57
+
CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */
58
+
};
59
+
60
+
#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
61
+
DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_DIV, .conf = _conf, \
62
+
.parent = _parent, .dtable = _dtable, .flag = 0)
63
+
#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \
64
+
DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \
65
+
.parent_names = _parent_names, .num_parents = _num_parents, \
66
+
.flag = 0, .mux_flags = _mux_flags)
67
+
68
+
enum clk_ids {
69
+
/* Core Clock Outputs exported to DT */
70
+
LAST_DT_CORE_CLK = R9A09G077_SDHI_CLKHS,
71
+
72
+
/* External Input Clocks */
73
+
CLK_EXTAL,
74
+
75
+
/* Internal Core Clocks */
76
+
CLK_LOCO,
77
+
CLK_PLL0,
78
+
CLK_PLL1,
79
+
CLK_PLL2,
80
+
CLK_PLL4,
81
+
CLK_SEL_CLK_PLL0,
82
+
CLK_SEL_CLK_PLL1,
83
+
CLK_SEL_CLK_PLL2,
84
+
CLK_SEL_CLK_PLL4,
85
+
CLK_PLL4D1,
86
+
CLK_SCI0ASYNC,
87
+
88
+
/* Module Clocks */
89
+
MOD_CLK_BASE,
90
+
};
91
+
92
+
static const struct clk_div_table dtable_1_2[] = {
93
+
{0, 2},
94
+
{1, 1},
95
+
{0, 0},
96
+
};
97
+
98
+
static const struct clk_div_table dtable_24_25_30_32[] = {
99
+
{0, 32},
100
+
{1, 30},
101
+
{2, 25},
102
+
{3, 24},
103
+
{0, 0},
104
+
};
105
+
106
+
/* Mux clock tables */
107
+
108
+
static const char * const sel_clk_pll0[] = { ".loco", ".pll0" };
109
+
static const char * const sel_clk_pll1[] = { ".loco", ".pll1" };
110
+
static const char * const sel_clk_pll2[] = { ".loco", ".pll2" };
111
+
static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };
112
+
113
+
static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
114
+
/* External Clock Inputs */
115
+
DEF_INPUT("extal", CLK_EXTAL),
116
+
117
+
/* Internal Core Clocks */
118
+
DEF_RATE(".loco", CLK_LOCO, 1000 * 1000),
119
+
DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 1, 48),
120
+
DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40),
121
+
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 1, 32),
122
+
DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96),
123
+
124
+
DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL,
125
+
sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY),
126
+
DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL,
127
+
sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY),
128
+
DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL,
129
+
sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY),
130
+
DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL,
131
+
sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
132
+
133
+
DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
134
+
DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
135
+
dtable_24_25_30_32),
136
+
137
+
/* Core output clk */
138
+
DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
139
+
dtable_1_2),
140
+
DEF_DIV("CA55C1", R9A09G077_CLK_CA55C1, CLK_SEL_CLK_PLL0, DIVCA55C1,
141
+
dtable_1_2),
142
+
DEF_DIV("CA55C2", R9A09G077_CLK_CA55C2, CLK_SEL_CLK_PLL0, DIVCA55C2,
143
+
dtable_1_2),
144
+
DEF_DIV("CA55C3", R9A09G077_CLK_CA55C3, CLK_SEL_CLK_PLL0, DIVCA55C3,
145
+
dtable_1_2),
146
+
DEF_DIV("CA55S", R9A09G077_CLK_CA55S, CLK_SEL_CLK_PLL0, DIVCA55S,
147
+
dtable_1_2),
148
+
DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
149
+
DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
150
+
DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
151
+
DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
152
+
DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
153
+
};
154
+
155
+
static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
156
+
DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
157
+
DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
158
+
DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
159
+
DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL),
160
+
DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
161
+
DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
162
+
};
163
+
164
+
static struct clk * __init
165
+
r9a09g077_cpg_div_clk_register(struct device *dev,
166
+
const struct cpg_core_clk *core,
167
+
void __iomem *addr, struct cpg_mssr_pub *pub)
168
+
{
169
+
const struct clk *parent;
170
+
const char *parent_name;
171
+
struct clk_hw *clk_hw;
172
+
173
+
parent = pub->clks[core->parent];
174
+
if (IS_ERR(parent))
175
+
return ERR_CAST(parent);
176
+
177
+
parent_name = __clk_get_name(parent);
178
+
179
+
if (core->dtable)
180
+
clk_hw = clk_hw_register_divider_table(dev, core->name,
181
+
parent_name, 0,
182
+
addr,
183
+
GET_SHIFT(core->conf),
184
+
GET_WIDTH(core->conf),
185
+
core->flag,
186
+
core->dtable,
187
+
&pub->rmw_lock);
188
+
else
189
+
clk_hw = clk_hw_register_divider(dev, core->name,
190
+
parent_name, 0,
191
+
addr,
192
+
GET_SHIFT(core->conf),
193
+
GET_WIDTH(core->conf),
194
+
core->flag, &pub->rmw_lock);
195
+
196
+
if (IS_ERR(clk_hw))
197
+
return ERR_CAST(clk_hw);
198
+
199
+
return clk_hw->clk;
200
+
201
+
}
202
+
203
+
static struct clk * __init
204
+
r9a09g077_cpg_mux_clk_register(struct device *dev,
205
+
const struct cpg_core_clk *core,
206
+
void __iomem *addr, struct cpg_mssr_pub *pub)
207
+
{
208
+
struct clk_hw *clk_hw;
209
+
210
+
clk_hw = devm_clk_hw_register_mux(dev, core->name,
211
+
core->parent_names, core->num_parents,
212
+
core->flag,
213
+
addr,
214
+
GET_SHIFT(core->conf),
215
+
GET_WIDTH(core->conf),
216
+
core->mux_flags, &pub->rmw_lock);
217
+
if (IS_ERR(clk_hw))
218
+
return ERR_CAST(clk_hw);
219
+
220
+
return clk_hw->clk;
221
+
}
222
+
223
+
static struct clk * __init
224
+
r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core,
225
+
const struct cpg_mssr_info *info,
226
+
struct cpg_mssr_pub *pub)
227
+
{
228
+
u32 offset = GET_REG_OFFSET(core->conf);
229
+
void __iomem *base = RZT2H_REG_BLOCK(offset) ? pub->base1 : pub->base0;
230
+
void __iomem *addr = base + RZT2H_REG_OFFSET(offset);
231
+
232
+
switch (core->type) {
233
+
case CLK_TYPE_RZT2H_DIV:
234
+
return r9a09g077_cpg_div_clk_register(dev, core, addr, pub);
235
+
case CLK_TYPE_RZT2H_MUX:
236
+
return r9a09g077_cpg_mux_clk_register(dev, core, addr, pub);
237
+
default:
238
+
return ERR_PTR(-EINVAL);
239
+
}
240
+
}
241
+
242
+
const struct cpg_mssr_info r9a09g077_cpg_mssr_info = {
243
+
/* Core Clocks */
244
+
.core_clks = r9a09g077_core_clks,
245
+
.num_core_clks = ARRAY_SIZE(r9a09g077_core_clks),
246
+
.last_dt_core_clk = LAST_DT_CORE_CLK,
247
+
.num_total_core_clks = MOD_CLK_BASE,
248
+
249
+
/* Module Clocks */
250
+
.mod_clks = r9a09g077_mod_clks,
251
+
.num_mod_clks = ARRAY_SIZE(r9a09g077_mod_clks),
252
+
.num_hw_mod_clks = 14 * 32,
253
+
254
+
.reg_layout = CLK_REG_LAYOUT_RZ_T2H,
255
+
.cpg_clk_register = r9a09g077_cpg_clk_register,
256
+
};
+3
-2
drivers/clk/renesas/rcar-gen2-cpg.c
+3
-2
drivers/clk/renesas/rcar-gen2-cpg.c
···
274
274
275
275
struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
276
276
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
277
-
struct clk **clks, void __iomem *base,
278
-
struct raw_notifier_head *notifiers)
277
+
struct cpg_mssr_pub *pub)
279
278
{
280
279
const struct clk_div_table *table = NULL;
280
+
void __iomem *base = pub->base0;
281
+
struct clk **clks = pub->clks;
281
282
const struct clk *parent;
282
283
const char *parent_name;
283
284
unsigned int mult = 1;
+1
-2
drivers/clk/renesas/rcar-gen2-cpg.h
+1
-2
drivers/clk/renesas/rcar-gen2-cpg.h
···
32
32
33
33
struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
34
34
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
35
-
struct clk **clks, void __iomem *base,
36
-
struct raw_notifier_head *notifiers);
35
+
struct cpg_mssr_pub *pub);
37
36
int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
38
37
unsigned int pll0_div, u32 mode);
39
38
+4
-2
drivers/clk/renesas/rcar-gen3-cpg.c
+4
-2
drivers/clk/renesas/rcar-gen3-cpg.c
···
345
345
346
346
struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
347
347
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
348
-
struct clk **clks, void __iomem *base,
349
-
struct raw_notifier_head *notifiers)
348
+
struct cpg_mssr_pub *pub)
350
349
{
350
+
struct raw_notifier_head *notifiers = &pub->notifiers;
351
+
void __iomem *base = pub->base0;
352
+
struct clk **clks = pub->clks;
351
353
const struct clk *parent;
352
354
unsigned int mult = 1;
353
355
unsigned int div = 1;
+1
-2
drivers/clk/renesas/rcar-gen3-cpg.h
+1
-2
drivers/clk/renesas/rcar-gen3-cpg.h
···
81
81
82
82
struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
83
83
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
84
-
struct clk **clks, void __iomem *base,
85
-
struct raw_notifier_head *notifiers);
84
+
struct cpg_mssr_pub *pub);
86
85
int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
87
86
unsigned int clk_extalr, u32 mode);
88
87
+4
-2
drivers/clk/renesas/rcar-gen4-cpg.c
+4
-2
drivers/clk/renesas/rcar-gen4-cpg.c
···
418
418
419
419
struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
420
420
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
421
-
struct clk **clks, void __iomem *base,
422
-
struct raw_notifier_head *notifiers)
421
+
struct cpg_mssr_pub *pub)
423
422
{
423
+
struct raw_notifier_head *notifiers = &pub->notifiers;
424
+
void __iomem *base = pub->base0;
425
+
struct clk **clks = pub->clks;
424
426
const struct clk *parent;
425
427
unsigned int mult = 1;
426
428
unsigned int div = 1;
+1
-2
drivers/clk/renesas/rcar-gen4-cpg.h
+1
-2
drivers/clk/renesas/rcar-gen4-cpg.h
···
78
78
79
79
struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
80
80
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
81
-
struct clk **clks, void __iomem *base,
82
-
struct raw_notifier_head *notifiers);
81
+
struct cpg_mssr_pub *pub);
83
82
int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
84
83
unsigned int clk_extalr, u32 mode);
85
84
+142
-53
drivers/clk/renesas/renesas-cpg-mssr.c
+142
-53
drivers/clk/renesas/renesas-cpg-mssr.c
···
81
81
};
82
82
83
83
/*
84
+
* Module Stop Control Register (RZ/T2H)
85
+
* RZ/T2H has 2 registers blocks,
86
+
* Bit 12 is used to differentiate them
87
+
*/
88
+
89
+
#define RZT2H_MSTPCR_BLOCK_SHIFT 12
90
+
#define RZT2H_MSTPCR_OFFSET_MASK GENMASK(11, 0)
91
+
#define RZT2H_MSTPCR(block, offset) (((block) << RZT2H_MSTPCR_BLOCK_SHIFT) | \
92
+
((offset) & RZT2H_MSTPCR_OFFSET_MASK))
93
+
94
+
#define RZT2H_MSTPCR_BLOCK(x) ((x) >> RZT2H_MSTPCR_BLOCK_SHIFT)
95
+
#define RZT2H_MSTPCR_OFFSET(x) ((x) & RZT2H_MSTPCR_OFFSET_MASK)
96
+
97
+
static const u16 mstpcr_for_rzt2h[] = {
98
+
RZT2H_MSTPCR(0, 0x300), /* MSTPCRA */
99
+
RZT2H_MSTPCR(0, 0x304), /* MSTPCRB */
100
+
RZT2H_MSTPCR(0, 0x308), /* MSTPCRC */
101
+
RZT2H_MSTPCR(0, 0x30c), /* MSTPCRD */
102
+
RZT2H_MSTPCR(0, 0x310), /* MSTPCRE */
103
+
0,
104
+
RZT2H_MSTPCR(1, 0x318), /* MSTPCRG */
105
+
0,
106
+
RZT2H_MSTPCR(1, 0x320), /* MSTPCRI */
107
+
RZT2H_MSTPCR(0, 0x324), /* MSTPCRJ */
108
+
RZT2H_MSTPCR(0, 0x328), /* MSTPCRK */
109
+
RZT2H_MSTPCR(0, 0x32c), /* MSTPCRL */
110
+
RZT2H_MSTPCR(0, 0x330), /* MSTPCRM */
111
+
RZT2H_MSTPCR(1, 0x334), /* MSTPCRN */
112
+
};
113
+
114
+
/*
84
115
* Standby Control Register offsets (RZ/A)
85
116
* Base address is FRQCR register
86
117
*/
···
157
126
* struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
158
127
* and Software Reset Private Data
159
128
*
129
+
* @pub: Data passed to clock registration callback
160
130
* @rcdev: Optional reset controller entity
161
131
* @dev: CPG/MSSR device
162
-
* @base: CPG/MSSR register block base address
163
132
* @reg_layout: CPG/MSSR register layout
164
-
* @rmw_lock: protects RMW register accesses
165
133
* @np: Device node in DT for this CPG/MSSR module
166
134
* @num_core_clks: Number of Core Clocks in clks[]
167
135
* @num_mod_clks: Number of Module Clocks in clks[]
168
136
* @last_dt_core_clk: ID of the last Core Clock exported to DT
169
-
* @notifiers: Notifier chain to save/restore clock state for system resume
170
137
* @status_regs: Pointer to status registers array
171
138
* @control_regs: Pointer to control registers array
172
139
* @reset_regs: Pointer to reset registers array
···
176
147
* @clks: Array containing all Core and Module Clocks
177
148
*/
178
149
struct cpg_mssr_priv {
150
+
struct cpg_mssr_pub pub;
179
151
#ifdef CONFIG_RESET_CONTROLLER
180
152
struct reset_controller_dev rcdev;
181
153
#endif
182
154
struct device *dev;
183
-
void __iomem *base;
184
155
enum clk_reg_layout reg_layout;
185
-
spinlock_t rmw_lock;
186
156
struct device_node *np;
187
157
188
158
unsigned int num_core_clks;
189
159
unsigned int num_mod_clks;
190
160
unsigned int last_dt_core_clk;
191
161
192
-
struct raw_notifier_head notifiers;
193
162
const u16 *status_regs;
194
163
const u16 *control_regs;
195
164
const u16 *reset_regs;
···
219
192
220
193
#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
221
194
195
+
static u32 cpg_rzt2h_mstp_read(struct clk_hw *hw, u16 offset)
196
+
{
197
+
struct mstp_clock *clock = to_mstp_clock(hw);
198
+
struct cpg_mssr_priv *priv = clock->priv;
199
+
void __iomem *base =
200
+
RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0;
201
+
202
+
return readl(base + RZT2H_MSTPCR_OFFSET(offset));
203
+
}
204
+
205
+
static void cpg_rzt2h_mstp_write(struct clk_hw *hw, u16 offset, u32 value)
206
+
{
207
+
struct mstp_clock *clock = to_mstp_clock(hw);
208
+
struct cpg_mssr_priv *priv = clock->priv;
209
+
void __iomem *base =
210
+
RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0;
211
+
212
+
writel(value, base + RZT2H_MSTPCR_OFFSET(offset));
213
+
}
214
+
222
215
static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
223
216
{
224
217
struct mstp_clock *clock = to_mstp_clock(hw);
···
253
206
254
207
dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
255
208
str_on_off(enable));
256
-
spin_lock_irqsave(&priv->rmw_lock, flags);
209
+
spin_lock_irqsave(&priv->pub.rmw_lock, flags);
257
210
258
211
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
259
-
value = readb(priv->base + priv->control_regs[reg]);
212
+
value = readb(priv->pub.base0 + priv->control_regs[reg]);
260
213
if (enable)
261
214
value &= ~bitmask;
262
215
else
263
216
value |= bitmask;
264
-
writeb(value, priv->base + priv->control_regs[reg]);
217
+
writeb(value, priv->pub.base0 + priv->control_regs[reg]);
265
218
266
219
/* dummy read to ensure write has completed */
267
-
readb(priv->base + priv->control_regs[reg]);
268
-
barrier_data(priv->base + priv->control_regs[reg]);
269
-
} else {
270
-
value = readl(priv->base + priv->control_regs[reg]);
220
+
readb(priv->pub.base0 + priv->control_regs[reg]);
221
+
barrier_data(priv->pub.base0 + priv->control_regs[reg]);
222
+
223
+
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
224
+
value = cpg_rzt2h_mstp_read(hw,
225
+
priv->control_regs[reg]);
226
+
271
227
if (enable)
272
228
value &= ~bitmask;
273
229
else
274
230
value |= bitmask;
275
-
writel(value, priv->base + priv->control_regs[reg]);
231
+
232
+
cpg_rzt2h_mstp_write(hw,
233
+
priv->control_regs[reg],
234
+
value);
235
+
} else {
236
+
value = readl(priv->pub.base0 + priv->control_regs[reg]);
237
+
if (enable)
238
+
value &= ~bitmask;
239
+
else
240
+
value |= bitmask;
241
+
writel(value, priv->pub.base0 + priv->control_regs[reg]);
276
242
}
277
243
278
-
spin_unlock_irqrestore(&priv->rmw_lock, flags);
244
+
spin_unlock_irqrestore(&priv->pub.rmw_lock, flags);
279
245
280
-
if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
246
+
if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A ||
247
+
priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
281
248
return 0;
282
249
283
-
error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],
250
+
error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg],
284
251
value, !(value & bitmask), 0, 10);
285
252
if (error)
286
253
dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
287
-
priv->base + priv->control_regs[reg], bit);
254
+
priv->pub.base0 + priv->control_regs[reg], bit);
288
255
289
256
return error;
290
257
}
···
317
256
{
318
257
struct mstp_clock *clock = to_mstp_clock(hw);
319
258
struct cpg_mssr_priv *priv = clock->priv;
259
+
unsigned int reg = clock->index / 32;
320
260
u32 value;
321
261
322
262
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
323
-
value = readb(priv->base + priv->control_regs[clock->index / 32]);
263
+
value = readb(priv->pub.base0 + priv->control_regs[reg]);
264
+
else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
265
+
value = cpg_rzt2h_mstp_read(hw,
266
+
priv->control_regs[reg]);
324
267
else
325
-
value = readl(priv->base + priv->status_regs[clock->index / 32]);
268
+
value = readl(priv->pub.base0 + priv->status_regs[reg]);
326
269
327
270
return !(value & BIT(clock->index % 32));
328
271
}
···
413
348
case CLK_TYPE_DIV6P1:
414
349
case CLK_TYPE_DIV6_RO:
415
350
WARN_DEBUG(core->parent >= priv->num_core_clks);
416
-
parent = priv->clks[core->parent];
351
+
parent = priv->pub.clks[core->parent];
417
352
if (IS_ERR(parent)) {
418
353
clk = parent;
419
354
goto fail;
···
423
358
424
359
if (core->type == CLK_TYPE_DIV6_RO)
425
360
/* Multiply with the DIV6 register value */
426
-
div *= (readl(priv->base + core->offset) & 0x3f) + 1;
361
+
div *= (readl(priv->pub.base0 + core->offset) & 0x3f) + 1;
427
362
428
363
if (core->type == CLK_TYPE_DIV6P1) {
429
364
clk = cpg_div6_register(core->name, 1, &parent_name,
430
-
priv->base + core->offset,
431
-
&priv->notifiers);
365
+
priv->pub.base0 + core->offset,
366
+
&priv->pub.notifiers);
432
367
} else {
433
368
clk = clk_register_fixed_factor(NULL, core->name,
434
369
parent_name, 0,
···
444
379
default:
445
380
if (info->cpg_clk_register)
446
381
clk = info->cpg_clk_register(dev, core, info,
447
-
priv->clks, priv->base,
448
-
&priv->notifiers);
382
+
&priv->pub);
449
383
else
450
384
dev_err(dev, "%s has unsupported core clock type %u\n",
451
385
core->name, core->type);
···
455
391
goto fail;
456
392
457
393
dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
458
-
priv->clks[id] = clk;
394
+
priv->pub.clks[id] = clk;
459
395
return;
460
396
461
397
fail:
···
478
414
WARN_DEBUG(id < priv->num_core_clks);
479
415
WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
480
416
WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
481
-
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
417
+
WARN_DEBUG(PTR_ERR(priv->pub.clks[id]) != -ENOENT);
482
418
483
419
if (!mod->name) {
484
420
/* Skip NULLified clock */
485
421
return;
486
422
}
487
423
488
-
parent = priv->clks[mod->parent];
424
+
parent = priv->pub.clks[mod->parent];
489
425
if (IS_ERR(parent)) {
490
426
clk = parent;
491
427
goto fail;
···
687
623
dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
688
624
689
625
/* Reset module */
690
-
writel(bitmask, priv->base + priv->reset_regs[reg]);
626
+
writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]);
691
627
692
628
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
693
629
udelay(35);
694
630
695
631
/* Release module from reset state */
696
-
writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
632
+
writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]);
697
633
698
634
return 0;
699
635
}
···
707
643
708
644
dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
709
645
710
-
writel(bitmask, priv->base + priv->reset_regs[reg]);
646
+
writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]);
711
647
return 0;
712
648
}
713
649
···
721
657
722
658
dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
723
659
724
-
writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
660
+
writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]);
725
661
return 0;
726
662
}
727
663
···
733
669
unsigned int bit = id % 32;
734
670
u32 bitmask = BIT(bit);
735
671
736
-
return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
672
+
return !!(readl(priv->pub.base0 + priv->reset_regs[reg]) & bitmask);
737
673
}
738
674
739
675
static const struct reset_control_ops cpg_mssr_reset_ops = {
···
936
872
.data = &r8a779h0_cpg_mssr_info,
937
873
},
938
874
#endif
875
+
#ifdef CONFIG_CLK_R9A09G077
876
+
{
877
+
.compatible = "renesas,r9a09g077-cpg-mssr",
878
+
.data = &r9a09g077_cpg_mssr_info,
879
+
},
880
+
#endif
881
+
#ifdef CONFIG_CLK_R9A09G087
882
+
{
883
+
.compatible = "renesas,r9a09g087-cpg-mssr",
884
+
.data = &r9a09g077_cpg_mssr_info,
885
+
},
886
+
#endif
939
887
{ /* sentinel */ }
940
888
};
941
889
···
971
895
if (priv->smstpcr_saved[reg].mask)
972
896
priv->smstpcr_saved[reg].val =
973
897
priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
974
-
readb(priv->base + priv->control_regs[reg]) :
975
-
readl(priv->base + priv->control_regs[reg]);
898
+
readb(priv->pub.base0 + priv->control_regs[reg]) :
899
+
readl(priv->pub.base0 + priv->control_regs[reg]);
976
900
}
977
901
978
902
/* Save core clocks */
979
-
raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
903
+
raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_SUSPEND, NULL);
980
904
981
905
return 0;
982
906
}
···
993
917
return 0;
994
918
995
919
/* Restore core clocks */
996
-
raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
920
+
raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_RESUME, NULL);
997
921
998
922
/* Restore module clocks */
999
923
for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
···
1002
926
continue;
1003
927
1004
928
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1005
-
oldval = readb(priv->base + priv->control_regs[reg]);
929
+
oldval = readb(priv->pub.base0 + priv->control_regs[reg]);
1006
930
else
1007
-
oldval = readl(priv->base + priv->control_regs[reg]);
931
+
oldval = readl(priv->pub.base0 + priv->control_regs[reg]);
1008
932
newval = oldval & ~mask;
1009
933
newval |= priv->smstpcr_saved[reg].val & mask;
1010
934
if (newval == oldval)
1011
935
continue;
1012
936
1013
937
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
1014
-
writeb(newval, priv->base + priv->control_regs[reg]);
938
+
writeb(newval, priv->pub.base0 + priv->control_regs[reg]);
1015
939
/* dummy read to ensure write has completed */
1016
-
readb(priv->base + priv->control_regs[reg]);
1017
-
barrier_data(priv->base + priv->control_regs[reg]);
940
+
readb(priv->pub.base0 + priv->control_regs[reg]);
941
+
barrier_data(priv->pub.base0 + priv->control_regs[reg]);
1018
942
continue;
1019
943
} else
1020
-
writel(newval, priv->base + priv->control_regs[reg]);
944
+
writel(newval, priv->pub.base0 + priv->control_regs[reg]);
1021
945
1022
946
/* Wait until enabled clocks are really enabled */
1023
947
mask &= ~priv->smstpcr_saved[reg].val;
1024
948
if (!mask)
1025
949
continue;
1026
950
1027
-
error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],
951
+
error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg],
1028
952
oldval, !(oldval & mask), 0, 10);
1029
953
if (error)
1030
954
dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg,
···
1134
1058
if (!priv)
1135
1059
return -ENOMEM;
1136
1060
1061
+
priv->pub.clks = priv->clks;
1137
1062
priv->np = np;
1138
1063
priv->dev = dev;
1139
-
spin_lock_init(&priv->rmw_lock);
1064
+
spin_lock_init(&priv->pub.rmw_lock);
1140
1065
1141
-
priv->base = of_iomap(np, 0);
1142
-
if (!priv->base) {
1066
+
priv->pub.base0 = of_iomap(np, 0);
1067
+
if (!priv->pub.base0) {
1143
1068
error = -ENOMEM;
1144
1069
goto out_err;
1070
+
}
1071
+
if (info->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
1072
+
priv->pub.base1 = of_iomap(np, 1);
1073
+
if (!priv->pub.base1) {
1074
+
error = -ENOMEM;
1075
+
goto out_err;
1076
+
}
1145
1077
}
1146
1078
1147
1079
priv->num_core_clks = info->num_total_core_clks;
1148
1080
priv->num_mod_clks = info->num_hw_mod_clks;
1149
1081
priv->last_dt_core_clk = info->last_dt_core_clk;
1150
-
RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
1082
+
RAW_INIT_NOTIFIER_HEAD(&priv->pub.notifiers);
1151
1083
priv->reg_layout = info->reg_layout;
1152
1084
if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
1153
1085
priv->status_regs = mstpsr;
···
1164
1080
priv->reset_clear_regs = srstclr;
1165
1081
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
1166
1082
priv->control_regs = stbcr;
1083
+
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
1084
+
priv->control_regs = mstpcr_for_rzt2h;
1167
1085
} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
1168
1086
priv->status_regs = mstpsr_for_gen4;
1169
1087
priv->control_regs = mstpcr_for_gen4;
···
1177
1091
}
1178
1092
1179
1093
for (i = 0; i < nclks; i++)
1180
-
priv->clks[i] = ERR_PTR(-ENOENT);
1094
+
priv->pub.clks[i] = ERR_PTR(-ENOENT);
1181
1095
1182
1096
error = cpg_mssr_reserved_init(priv, info);
1183
1097
if (error)
···
1194
1108
reserve_err:
1195
1109
cpg_mssr_reserved_exit(priv);
1196
1110
out_err:
1197
-
if (priv->base)
1198
-
iounmap(priv->base);
1111
+
if (priv->pub.base0)
1112
+
iounmap(priv->pub.base0);
1113
+
if (priv->pub.base1)
1114
+
iounmap(priv->pub.base1);
1199
1115
kfree(priv);
1200
1116
1201
1117
return error;
···
1262
1174
goto reserve_exit;
1263
1175
1264
1176
/* Reset Controller not supported for Standby Control SoCs */
1265
-
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1177
+
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A ||
1178
+
priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
1266
1179
goto reserve_exit;
1267
1180
1268
1181
error = cpg_mssr_reset_controller_register(priv);
+30
-2
drivers/clk/renesas/renesas-cpg-mssr.h
+30
-2
drivers/clk/renesas/renesas-cpg-mssr.h
···
8
8
#ifndef __CLK_RENESAS_CPG_MSSR_H__
9
9
#define __CLK_RENESAS_CPG_MSSR_H__
10
10
11
+
#include <linux/notifier.h>
12
+
11
13
/*
12
14
* Definitions of CPG Core Clocks
13
15
*
···
29
27
unsigned int div;
30
28
unsigned int mult;
31
29
unsigned int offset;
30
+
union {
31
+
const char * const *parent_names;
32
+
const struct clk_div_table *dtable;
33
+
};
34
+
u32 conf;
35
+
u16 flag;
36
+
u8 mux_flags;
37
+
u8 num_parents;
38
+
};
39
+
40
+
/**
41
+
* struct cpg_mssr_pub - data shared with device-specific clk registration code
42
+
*
43
+
* @base0: CPG/MSSR register block base0 address
44
+
* @base1: CPG/MSSR register block base1 address
45
+
* @notifiers: Notifier chain to save/restore clock state for system resume
46
+
* @rmw_lock: protects RMW register accesses
47
+
* @clks: pointer to clocks
48
+
*/
49
+
struct cpg_mssr_pub {
50
+
void __iomem *base0;
51
+
void __iomem *base1;
52
+
struct raw_notifier_head notifiers;
53
+
spinlock_t rmw_lock;
54
+
struct clk **clks;
32
55
};
33
56
34
57
enum clk_types {
···
116
89
CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
117
90
CLK_REG_LAYOUT_RZ_A,
118
91
CLK_REG_LAYOUT_RCAR_GEN4,
92
+
CLK_REG_LAYOUT_RZ_T2H,
119
93
};
120
94
121
95
/**
···
181
153
struct clk *(*cpg_clk_register)(struct device *dev,
182
154
const struct cpg_core_clk *core,
183
155
const struct cpg_mssr_info *info,
184
-
struct clk **clks, void __iomem *base,
185
-
struct raw_notifier_head *notifiers);
156
+
struct cpg_mssr_pub *pub);
186
157
};
187
158
188
159
extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
···
208
181
extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
209
182
extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info;
210
183
extern const struct cpg_mssr_info r8a779h0_cpg_mssr_info;
184
+
extern const struct cpg_mssr_info r9a09g077_cpg_mssr_info;
211
185
212
186
void __init cpg_mssr_early_init(struct device_node *np,
213
187
const struct cpg_mssr_info *info);
+300
-229
drivers/clk/renesas/rzg2l-cpg.c
+300
-229
drivers/clk/renesas/rzg2l-cpg.c
···
11
11
* Copyright (C) 2015 Renesas Electronics Corp.
12
12
*/
13
13
14
+
#include <linux/atomic.h>
14
15
#include <linux/bitfield.h>
16
+
#include <linux/cleanup.h>
15
17
#include <linux/clk.h>
16
18
#include <linux/clk-provider.h>
17
19
#include <linux/clk/renesas.h>
20
+
#include <linux/debugfs.h>
18
21
#include <linux/delay.h>
19
22
#include <linux/device.h>
20
23
#include <linux/init.h>
···
70
67
#define CPG_WEN_BIT BIT(16)
71
68
72
69
#define MAX_VCLK_FREQ (148500000)
70
+
71
+
#define MSTOP_OFF(conf) FIELD_GET(GENMASK(31, 16), (conf))
72
+
#define MSTOP_MASK(conf) FIELD_GET(GENMASK(15, 0), (conf))
73
73
74
74
/**
75
75
* struct clk_hw_data - clock hardware data
···
148
142
* @num_resets: Number of Module Resets in info->resets[]
149
143
* @last_dt_core_clk: ID of the last Core Clock exported to DT
150
144
* @info: Pointer to platform data
145
+
* @genpd: PM domain
151
146
* @mux_dsi_div_params: pll5 mux and dsi div parameters
152
147
*/
153
148
struct rzg2l_cpg_priv {
···
164
157
unsigned int last_dt_core_clk;
165
158
166
159
const struct rzg2l_cpg_info *info;
160
+
161
+
struct generic_pm_domain genpd;
167
162
168
163
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
169
164
};
···
1191
1182
}
1192
1183
1193
1184
/**
1194
-
* struct mstp_clock - MSTP gating clock
1195
-
*
1196
-
* @hw: handle between common and hardware-specific interfaces
1197
-
* @off: register offset
1198
-
* @bit: ON/MON bit
1199
-
* @enabled: soft state of the clock, if it is coupled with another clock
1200
-
* @priv: CPG/MSTP private data
1201
-
* @sibling: pointer to the other coupled clock
1185
+
* struct mstop - MSTOP specific data structure
1186
+
* @usecnt: Usage counter for MSTOP settings (when zero the settings
1187
+
* are applied to register)
1188
+
* @conf: MSTOP configuration (register offset, setup bits)
1202
1189
*/
1203
-
struct mstp_clock {
1204
-
struct clk_hw hw;
1205
-
u16 off;
1206
-
u8 bit;
1207
-
bool enabled;
1208
-
struct rzg2l_cpg_priv *priv;
1209
-
struct mstp_clock *sibling;
1190
+
struct mstop {
1191
+
atomic_t usecnt;
1192
+
u32 conf;
1210
1193
};
1211
1194
1212
-
#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
1195
+
/**
1196
+
* struct mod_clock - Module clock
1197
+
*
1198
+
* @hw: handle between common and hardware-specific interfaces
1199
+
* @priv: CPG/MSTP private data
1200
+
* @sibling: pointer to the other coupled clock
1201
+
* @mstop: MSTOP configuration
1202
+
* @shared_mstop_clks: clocks sharing the MSTOP with this clock
1203
+
* @off: register offset
1204
+
* @bit: ON/MON bit
1205
+
* @num_shared_mstop_clks: number of the clocks sharing MSTOP with this clock
1206
+
* @enabled: soft state of the clock, if it is coupled with another clock
1207
+
*/
1208
+
struct mod_clock {
1209
+
struct clk_hw hw;
1210
+
struct rzg2l_cpg_priv *priv;
1211
+
struct mod_clock *sibling;
1212
+
struct mstop *mstop;
1213
+
struct mod_clock **shared_mstop_clks;
1214
+
u16 off;
1215
+
u8 bit;
1216
+
u8 num_shared_mstop_clks;
1217
+
bool enabled;
1218
+
};
1219
+
1220
+
#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
1221
+
1222
+
#define for_each_mod_clock(mod_clock, hw, priv) \
1223
+
for (unsigned int i = 0; (priv) && i < (priv)->num_mod_clks; i++) \
1224
+
if ((priv)->clks[(priv)->num_core_clks + i] == ERR_PTR(-ENOENT)) \
1225
+
continue; \
1226
+
else if (((hw) = __clk_get_hw((priv)->clks[(priv)->num_core_clks + i])) && \
1227
+
((mod_clock) = to_mod_clock(hw)))
1228
+
1229
+
/* Need to be called with a lock held to avoid concurrent access to mstop->usecnt. */
1230
+
static void rzg2l_mod_clock_module_set_state(struct mod_clock *clock,
1231
+
bool standby)
1232
+
{
1233
+
struct rzg2l_cpg_priv *priv = clock->priv;
1234
+
struct mstop *mstop = clock->mstop;
1235
+
bool update = false;
1236
+
u32 value;
1237
+
1238
+
if (!mstop)
1239
+
return;
1240
+
1241
+
value = MSTOP_MASK(mstop->conf) << 16;
1242
+
1243
+
if (standby) {
1244
+
unsigned int criticals = 0;
1245
+
1246
+
for (unsigned int i = 0; i < clock->num_shared_mstop_clks; i++) {
1247
+
struct mod_clock *clk = clock->shared_mstop_clks[i];
1248
+
1249
+
if (clk_hw_get_flags(&clk->hw) & CLK_IS_CRITICAL)
1250
+
criticals++;
1251
+
}
1252
+
1253
+
if (!clock->num_shared_mstop_clks &&
1254
+
clk_hw_get_flags(&clock->hw) & CLK_IS_CRITICAL)
1255
+
criticals++;
1256
+
1257
+
/*
1258
+
* If this is a shared MSTOP and it is shared with critical clocks,
1259
+
* and the system boots up with this clock enabled but no driver
1260
+
* uses it the CCF will disable it (as it is unused). As we don't
1261
+
* increment reference counter for it at registration (to avoid
1262
+
* messing with clocks enabled at probe but later used by drivers)
1263
+
* do not set the MSTOP here too if it is shared with critical
1264
+
* clocks and ref counted only by those critical clocks.
1265
+
*/
1266
+
if (criticals && criticals == atomic_read(&mstop->usecnt))
1267
+
return;
1268
+
1269
+
value |= MSTOP_MASK(mstop->conf);
1270
+
1271
+
/* Allow updates on probe when usecnt = 0. */
1272
+
if (!atomic_read(&mstop->usecnt))
1273
+
update = true;
1274
+
else
1275
+
update = atomic_dec_and_test(&mstop->usecnt);
1276
+
} else {
1277
+
if (!atomic_read(&mstop->usecnt))
1278
+
update = true;
1279
+
atomic_inc(&mstop->usecnt);
1280
+
}
1281
+
1282
+
if (update)
1283
+
writel(value, priv->base + MSTOP_OFF(mstop->conf));
1284
+
}
1285
+
1286
+
static int rzg2l_mod_clock_mstop_show(struct seq_file *s, void *what)
1287
+
{
1288
+
struct rzg2l_cpg_priv *priv = s->private;
1289
+
struct mod_clock *clk;
1290
+
struct clk_hw *hw;
1291
+
1292
+
seq_printf(s, "%-20s %-5s %-10s\n", "", "", "MSTOP");
1293
+
seq_printf(s, "%-20s %-5s %-10s\n", "", "clk", "-------------------------");
1294
+
seq_printf(s, "%-20s %-5s %-5s %-5s %-6s %-6s\n",
1295
+
"clk_name", "cnt", "cnt", "off", "val", "shared");
1296
+
seq_printf(s, "%-20s %-5s %-5s %-5s %-6s %-6s\n",
1297
+
"--------", "-----", "-----", "-----", "------", "------");
1298
+
1299
+
for_each_mod_clock(clk, hw, priv) {
1300
+
u32 val;
1301
+
1302
+
if (!clk->mstop)
1303
+
continue;
1304
+
1305
+
val = readl(priv->base + MSTOP_OFF(clk->mstop->conf)) &
1306
+
MSTOP_MASK(clk->mstop->conf);
1307
+
1308
+
seq_printf(s, "%-20s %-5d %-5d 0x%-3lx 0x%-4x", clk_hw_get_name(hw),
1309
+
__clk_get_enable_count(hw->clk), atomic_read(&clk->mstop->usecnt),
1310
+
MSTOP_OFF(clk->mstop->conf), val);
1311
+
1312
+
for (unsigned int i = 0; i < clk->num_shared_mstop_clks; i++)
1313
+
seq_printf(s, " %pC", clk->shared_mstop_clks[i]->hw.clk);
1314
+
1315
+
seq_puts(s, "\n");
1316
+
}
1317
+
1318
+
return 0;
1319
+
}
1320
+
DEFINE_SHOW_ATTRIBUTE(rzg2l_mod_clock_mstop);
1213
1321
1214
1322
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
1215
1323
{
1216
-
struct mstp_clock *clock = to_mod_clock(hw);
1324
+
struct mod_clock *clock = to_mod_clock(hw);
1217
1325
struct rzg2l_cpg_priv *priv = clock->priv;
1218
1326
unsigned int reg = clock->off;
1219
1327
struct device *dev = priv->dev;
···
1350
1224
if (enable)
1351
1225
value |= bitmask;
1352
1226
1353
-
writel(value, priv->base + CLK_ON_R(reg));
1227
+
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
1228
+
if (enable) {
1229
+
writel(value, priv->base + CLK_ON_R(reg));
1230
+
rzg2l_mod_clock_module_set_state(clock, false);
1231
+
} else {
1232
+
rzg2l_mod_clock_module_set_state(clock, true);
1233
+
writel(value, priv->base + CLK_ON_R(reg));
1234
+
}
1235
+
}
1354
1236
1355
1237
if (!enable)
1356
1238
return 0;
···
1377
1243
1378
1244
static int rzg2l_mod_clock_enable(struct clk_hw *hw)
1379
1245
{
1380
-
struct mstp_clock *clock = to_mod_clock(hw);
1246
+
struct mod_clock *clock = to_mod_clock(hw);
1381
1247
1382
1248
if (clock->sibling) {
1383
1249
struct rzg2l_cpg_priv *priv = clock->priv;
···
1397
1263
1398
1264
static void rzg2l_mod_clock_disable(struct clk_hw *hw)
1399
1265
{
1400
-
struct mstp_clock *clock = to_mod_clock(hw);
1266
+
struct mod_clock *clock = to_mod_clock(hw);
1401
1267
1402
1268
if (clock->sibling) {
1403
1269
struct rzg2l_cpg_priv *priv = clock->priv;
···
1417
1283
1418
1284
static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
1419
1285
{
1420
-
struct mstp_clock *clock = to_mod_clock(hw);
1286
+
struct mod_clock *clock = to_mod_clock(hw);
1421
1287
struct rzg2l_cpg_priv *priv = clock->priv;
1422
1288
u32 bitmask = BIT(clock->bit);
1423
1289
u32 value;
···
1444
1310
.is_enabled = rzg2l_mod_clock_is_enabled,
1445
1311
};
1446
1312
1447
-
static struct mstp_clock
1448
-
*rzg2l_mod_clock_get_sibling(struct mstp_clock *clock,
1313
+
static struct mod_clock
1314
+
*rzg2l_mod_clock_get_sibling(struct mod_clock *clock,
1449
1315
struct rzg2l_cpg_priv *priv)
1450
1316
{
1317
+
struct mod_clock *clk;
1451
1318
struct clk_hw *hw;
1452
-
unsigned int i;
1453
1319
1454
-
for (i = 0; i < priv->num_mod_clks; i++) {
1455
-
struct mstp_clock *clk;
1456
-
1457
-
if (priv->clks[priv->num_core_clks + i] == ERR_PTR(-ENOENT))
1458
-
continue;
1459
-
1460
-
hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]);
1461
-
clk = to_mod_clock(hw);
1320
+
for_each_mod_clock(clk, hw, priv) {
1462
1321
if (clock->off == clk->off && clock->bit == clk->bit)
1463
1322
return clk;
1464
1323
}
···
1459
1332
return NULL;
1460
1333
}
1461
1334
1335
+
static struct mstop *rzg2l_mod_clock_get_mstop(struct rzg2l_cpg_priv *priv, u32 conf)
1336
+
{
1337
+
struct mod_clock *clk;
1338
+
struct clk_hw *hw;
1339
+
1340
+
for_each_mod_clock(clk, hw, priv) {
1341
+
if (!clk->mstop)
1342
+
continue;
1343
+
1344
+
if (clk->mstop->conf == conf)
1345
+
return clk->mstop;
1346
+
}
1347
+
1348
+
return NULL;
1349
+
}
1350
+
1351
+
static void rzg2l_mod_clock_init_mstop(struct rzg2l_cpg_priv *priv)
1352
+
{
1353
+
struct mod_clock *clk;
1354
+
struct clk_hw *hw;
1355
+
1356
+
for_each_mod_clock(clk, hw, priv) {
1357
+
if (!clk->mstop)
1358
+
continue;
1359
+
1360
+
/*
1361
+
* Out of reset all modules are enabled. Set module state
1362
+
* in case associated clocks are disabled at probe. Otherwise
1363
+
* module is in invalid HW state.
1364
+
*/
1365
+
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
1366
+
if (!rzg2l_mod_clock_is_enabled(&clk->hw))
1367
+
rzg2l_mod_clock_module_set_state(clk, true);
1368
+
}
1369
+
}
1370
+
}
1371
+
1372
+
static int rzg2l_mod_clock_update_shared_mstop_clks(struct rzg2l_cpg_priv *priv,
1373
+
struct mod_clock *clock)
1374
+
{
1375
+
struct mod_clock *clk;
1376
+
struct clk_hw *hw;
1377
+
1378
+
if (!clock->mstop)
1379
+
return 0;
1380
+
1381
+
for_each_mod_clock(clk, hw, priv) {
1382
+
int num_shared_mstop_clks, incr = 1;
1383
+
struct mod_clock **new_clks;
1384
+
1385
+
if (clk->mstop != clock->mstop)
1386
+
continue;
1387
+
1388
+
num_shared_mstop_clks = clk->num_shared_mstop_clks;
1389
+
if (!num_shared_mstop_clks)
1390
+
incr++;
1391
+
1392
+
new_clks = devm_krealloc(priv->dev, clk->shared_mstop_clks,
1393
+
(num_shared_mstop_clks + incr) * sizeof(*new_clks),
1394
+
GFP_KERNEL);
1395
+
if (!new_clks)
1396
+
return -ENOMEM;
1397
+
1398
+
if (!num_shared_mstop_clks)
1399
+
new_clks[num_shared_mstop_clks++] = clk;
1400
+
new_clks[num_shared_mstop_clks++] = clock;
1401
+
1402
+
for (unsigned int i = 0; i < num_shared_mstop_clks; i++) {
1403
+
new_clks[i]->shared_mstop_clks = new_clks;
1404
+
new_clks[i]->num_shared_mstop_clks = num_shared_mstop_clks;
1405
+
}
1406
+
break;
1407
+
}
1408
+
1409
+
return 0;
1410
+
}
1411
+
1462
1412
static void __init
1463
1413
rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
1464
1414
const struct rzg2l_cpg_info *info,
1465
1415
struct rzg2l_cpg_priv *priv)
1466
1416
{
1467
-
struct mstp_clock *clock = NULL;
1417
+
struct mod_clock *clock = NULL;
1468
1418
struct device *dev = priv->dev;
1469
1419
unsigned int id = mod->id;
1470
1420
struct clk_init_data init;
···
1587
1383
clock->priv = priv;
1588
1384
clock->hw.init = &init;
1589
1385
1386
+
if (mod->mstop_conf) {
1387
+
struct mstop *mstop = rzg2l_mod_clock_get_mstop(priv, mod->mstop_conf);
1388
+
1389
+
if (!mstop) {
1390
+
mstop = devm_kzalloc(dev, sizeof(*mstop), GFP_KERNEL);
1391
+
if (!mstop) {
1392
+
clk = ERR_PTR(-ENOMEM);
1393
+
goto fail;
1394
+
}
1395
+
mstop->conf = mod->mstop_conf;
1396
+
atomic_set(&mstop->usecnt, 0);
1397
+
}
1398
+
clock->mstop = mstop;
1399
+
}
1400
+
1590
1401
ret = devm_clk_hw_register(dev, &clock->hw);
1591
1402
if (ret) {
1592
1403
clk = ERR_PTR(ret);
1593
1404
goto fail;
1594
1405
}
1595
1406
1596
-
clk = clock->hw.clk;
1597
-
dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
1598
-
priv->clks[id] = clk;
1599
-
1600
1407
if (mod->is_coupled) {
1601
-
struct mstp_clock *sibling;
1408
+
struct mod_clock *sibling;
1602
1409
1603
1410
clock->enabled = rzg2l_mod_clock_is_enabled(&clock->hw);
1604
1411
sibling = rzg2l_mod_clock_get_sibling(clock, priv);
···
1618
1403
sibling->sibling = clock;
1619
1404
}
1620
1405
}
1406
+
1407
+
/* Keep this before priv->clks[id] is updated. */
1408
+
ret = rzg2l_mod_clock_update_shared_mstop_clks(priv, clock);
1409
+
if (ret) {
1410
+
clk = ERR_PTR(ret);
1411
+
goto fail;
1412
+
}
1413
+
1414
+
clk = clock->hw.clk;
1415
+
dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
1416
+
priv->clks[id] = clk;
1621
1417
1622
1418
return;
1623
1419
···
1766
1540
return devm_reset_controller_register(priv->dev, &priv->rcdev);
1767
1541
}
1768
1542
1769
-
/**
1770
-
* struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
1771
-
* @onecell_data: cell data
1772
-
* @domains: generic PM domains
1773
-
*/
1774
-
struct rzg2l_cpg_pm_domains {
1775
-
struct genpd_onecell_data onecell_data;
1776
-
struct generic_pm_domain *domains[];
1777
-
};
1778
-
1779
-
/**
1780
-
* struct rzg2l_cpg_pd - RZ/G2L power domain data structure
1781
-
* @genpd: generic PM domain
1782
-
* @priv: pointer to CPG private data structure
1783
-
* @conf: CPG PM domain configuration info
1784
-
* @id: RZ/G2L power domain ID
1785
-
*/
1786
-
struct rzg2l_cpg_pd {
1787
-
struct generic_pm_domain genpd;
1788
-
struct rzg2l_cpg_priv *priv;
1789
-
struct rzg2l_cpg_pm_domain_conf conf;
1790
-
u16 id;
1791
-
};
1792
-
1793
-
static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_pd *pd,
1543
+
static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
1794
1544
const struct of_phandle_args *clkspec)
1795
1545
{
1796
-
if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
1546
+
if (clkspec->np != priv->genpd.dev.of_node || clkspec->args_count != 2)
1797
1547
return false;
1798
1548
1799
1549
switch (clkspec->args[0]) {
1800
1550
case CPG_MOD: {
1801
-
struct rzg2l_cpg_priv *priv = pd->priv;
1802
1551
const struct rzg2l_cpg_info *info = priv->info;
1803
1552
unsigned int id = clkspec->args[1];
1804
1553
···
1798
1597
1799
1598
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
1800
1599
{
1801
-
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
1600
+
struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
1802
1601
struct device_node *np = dev->of_node;
1803
1602
struct of_phandle_args clkspec;
1804
1603
bool once = true;
···
1807
1606
int error;
1808
1607
1809
1608
for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) {
1810
-
if (!rzg2l_cpg_is_pm_clk(pd, &clkspec)) {
1609
+
if (!rzg2l_cpg_is_pm_clk(priv, &clkspec)) {
1811
1610
of_node_put(clkspec.np);
1812
1611
continue;
1813
1612
}
···
1853
1652
1854
1653
static void rzg2l_cpg_genpd_remove(void *data)
1855
1654
{
1856
-
struct genpd_onecell_data *celldata = data;
1857
-
1858
-
for (unsigned int i = 0; i < celldata->num_domains; i++)
1859
-
pm_genpd_remove(celldata->domains[i]);
1860
-
}
1861
-
1862
-
static void rzg2l_cpg_genpd_remove_simple(void *data)
1863
-
{
1864
1655
pm_genpd_remove(data);
1865
-
}
1866
-
1867
-
static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
1868
-
{
1869
-
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
1870
-
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
1871
-
struct rzg2l_cpg_priv *priv = pd->priv;
1872
-
1873
-
/* Set MSTOP. */
1874
-
if (mstop.mask)
1875
-
writel(mstop.mask << 16, priv->base + mstop.off);
1876
-
1877
-
return 0;
1878
-
}
1879
-
1880
-
static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
1881
-
{
1882
-
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
1883
-
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
1884
-
struct rzg2l_cpg_priv *priv = pd->priv;
1885
-
1886
-
/* Set MSTOP. */
1887
-
if (mstop.mask)
1888
-
writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
1889
-
1890
-
return 0;
1891
-
}
1892
-
1893
-
static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd)
1894
-
{
1895
-
bool always_on = !!(pd->genpd.flags & GENPD_FLAG_ALWAYS_ON);
1896
-
struct dev_power_governor *governor;
1897
-
int ret;
1898
-
1899
-
if (always_on)
1900
-
governor = &pm_domain_always_on_gov;
1901
-
else
1902
-
governor = &simple_qos_governor;
1903
-
1904
-
pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
1905
-
pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
1906
-
pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
1907
-
pd->genpd.power_on = rzg2l_cpg_power_on;
1908
-
pd->genpd.power_off = rzg2l_cpg_power_off;
1909
-
1910
-
ret = pm_genpd_init(&pd->genpd, governor, !always_on);
1911
-
if (ret)
1912
-
return ret;
1913
-
1914
-
if (always_on)
1915
-
ret = rzg2l_cpg_power_on(&pd->genpd);
1916
-
1917
-
return ret;
1918
1656
}
1919
1657
1920
1658
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
1921
1659
{
1922
1660
struct device *dev = priv->dev;
1923
1661
struct device_node *np = dev->of_node;
1924
-
struct rzg2l_cpg_pd *pd;
1662
+
struct generic_pm_domain *genpd = &priv->genpd;
1925
1663
int ret;
1926
1664
1927
-
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1928
-
if (!pd)
1929
-
return -ENOMEM;
1930
-
1931
-
pd->genpd.name = np->name;
1932
-
pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
1933
-
pd->priv = priv;
1934
-
ret = rzg2l_cpg_pd_setup(pd);
1665
+
genpd->name = np->name;
1666
+
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
1667
+
GENPD_FLAG_ACTIVE_WAKEUP;
1668
+
genpd->attach_dev = rzg2l_cpg_attach_dev;
1669
+
genpd->detach_dev = rzg2l_cpg_detach_dev;
1670
+
ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
1935
1671
if (ret)
1936
1672
return ret;
1937
1673
1938
-
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
1674
+
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
1939
1675
if (ret)
1940
1676
return ret;
1941
1677
1942
-
return of_genpd_add_provider_simple(np, &pd->genpd);
1943
-
}
1944
-
1945
-
static struct generic_pm_domain *
1946
-
rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
1947
-
{
1948
-
struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
1949
-
struct genpd_onecell_data *genpd = data;
1950
-
1951
-
if (spec->args_count != 1)
1952
-
return ERR_PTR(-EINVAL);
1953
-
1954
-
for (unsigned int i = 0; i < genpd->num_domains; i++) {
1955
-
struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
1956
-
genpd);
1957
-
1958
-
if (pd->id == spec->args[0]) {
1959
-
domain = &pd->genpd;
1960
-
break;
1961
-
}
1962
-
}
1963
-
1964
-
return domain;
1965
-
}
1966
-
1967
-
static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
1968
-
{
1969
-
const struct rzg2l_cpg_info *info = priv->info;
1970
-
struct device *dev = priv->dev;
1971
-
struct device_node *np = dev->of_node;
1972
-
struct rzg2l_cpg_pm_domains *domains;
1973
-
struct generic_pm_domain *parent;
1974
-
u32 ncells;
1975
-
int ret;
1976
-
1977
-
ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
1978
-
if (ret)
1979
-
return ret;
1980
-
1981
-
/* For backward compatibility. */
1982
-
if (!ncells)
1983
-
return rzg2l_cpg_add_clk_domain(priv);
1984
-
1985
-
domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
1986
-
GFP_KERNEL);
1987
-
if (!domains)
1988
-
return -ENOMEM;
1989
-
1990
-
domains->onecell_data.domains = domains->domains;
1991
-
domains->onecell_data.num_domains = info->num_pm_domains;
1992
-
domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
1993
-
1994
-
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
1995
-
if (ret)
1996
-
return ret;
1997
-
1998
-
for (unsigned int i = 0; i < info->num_pm_domains; i++) {
1999
-
struct rzg2l_cpg_pd *pd;
2000
-
2001
-
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
2002
-
if (!pd)
2003
-
return -ENOMEM;
2004
-
2005
-
pd->genpd.name = info->pm_domains[i].name;
2006
-
pd->genpd.flags = info->pm_domains[i].genpd_flags;
2007
-
pd->conf = info->pm_domains[i].conf;
2008
-
pd->id = info->pm_domains[i].id;
2009
-
pd->priv = priv;
2010
-
2011
-
ret = rzg2l_cpg_pd_setup(pd);
2012
-
if (ret)
2013
-
return ret;
2014
-
2015
-
domains->domains[i] = &pd->genpd;
2016
-
/* Parent should be on the very first entry of info->pm_domains[]. */
2017
-
if (!i) {
2018
-
parent = &pd->genpd;
2019
-
continue;
2020
-
}
2021
-
2022
-
ret = pm_genpd_add_subdomain(parent, &pd->genpd);
2023
-
if (ret)
2024
-
return ret;
2025
-
}
2026
-
2027
-
ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
2028
-
if (ret)
2029
-
return ret;
2030
-
2031
-
return 0;
1678
+
return of_genpd_add_provider_simple(np, genpd);
2032
1679
}
2033
1680
2034
1681
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
···
1924
1875
for (i = 0; i < info->num_mod_clks; i++)
1925
1876
rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
1926
1877
1878
+
/*
1879
+
* Initialize MSTOP after all the clocks were registered to avoid
1880
+
* invalid reference counting when multiple clocks (critical,
1881
+
* non-critical) share the same MSTOP.
1882
+
*/
1883
+
rzg2l_mod_clock_init_mstop(priv);
1884
+
1927
1885
error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv);
1928
1886
if (error)
1929
1887
return error;
···
1939
1883
if (error)
1940
1884
return error;
1941
1885
1942
-
error = rzg2l_cpg_add_pm_domains(priv);
1886
+
error = rzg2l_cpg_add_clk_domain(priv);
1943
1887
if (error)
1944
1888
return error;
1945
1889
···
1947
1891
if (error)
1948
1892
return error;
1949
1893
1894
+
debugfs_create_file("mstop", 0444, NULL, priv, &rzg2l_mod_clock_mstop_fops);
1950
1895
return 0;
1951
1896
}
1897
+
1898
+
static int rzg2l_cpg_resume(struct device *dev)
1899
+
{
1900
+
struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev);
1901
+
1902
+
rzg2l_mod_clock_init_mstop(priv);
1903
+
1904
+
return 0;
1905
+
}
1906
+
1907
+
static const struct dev_pm_ops rzg2l_cpg_pm_ops = {
1908
+
NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, rzg2l_cpg_resume)
1909
+
};
1952
1910
1953
1911
static const struct of_device_id rzg2l_cpg_match[] = {
1954
1912
#ifdef CONFIG_CLK_R9A07G043
···
2002
1932
.driver = {
2003
1933
.name = "rzg2l-cpg",
2004
1934
.of_match_table = rzg2l_cpg_match,
1935
+
.pm = pm_sleep_ptr(&rzg2l_cpg_pm_ops),
2005
1936
},
2006
1937
};
2007
1938
+10
-56
drivers/clk/renesas/rzg2l-cpg.h
+10
-56
drivers/clk/renesas/rzg2l-cpg.h
···
82
82
#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
83
83
#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
84
84
85
+
#define MSTOP(name, bitmask) ((CPG_##name##_MSTOP) << 16 | (bitmask))
86
+
85
87
#define EXTAL_FREQ_IN_MEGA_HZ (24)
86
88
87
89
/**
···
203
201
* @name: handle between common and hardware-specific interfaces
204
202
* @id: clock index in array containing all Core and Module Clocks
205
203
* @parent: id of parent clock
204
+
* @mstop_conf: MSTOP configuration
206
205
* @off: register offset
207
206
* @bit: ON/MON bit
208
207
* @is_coupled: flag to indicate coupled clock
···
212
209
const char *name;
213
210
unsigned int id;
214
211
unsigned int parent;
212
+
u32 mstop_conf;
215
213
u16 off;
216
214
u8 bit;
217
215
bool is_coupled;
218
216
};
219
217
220
-
#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \
218
+
#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \
221
219
{ \
222
220
.name = _name, \
223
221
.id = MOD_CLK_BASE + (_id), \
224
222
.parent = (_parent), \
223
+
.mstop_conf = (_mstop_conf), \
225
224
.off = (_off), \
226
225
.bit = (_bit), \
227
226
.is_coupled = (_is_coupled), \
228
227
}
229
228
230
-
#define DEF_MOD(_name, _id, _parent, _off, _bit) \
231
-
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
229
+
#define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \
230
+
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false)
232
231
233
-
#define DEF_COUPLED(_name, _id, _parent, _off, _bit) \
234
-
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
232
+
#define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \
233
+
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true)
235
234
236
235
/**
237
236
* struct rzg2l_reset - Reset definitions
···
258
253
DEF_RST_MON(_id, _off, _bit, -1)
259
254
260
255
/**
261
-
* struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
262
-
* @off: register offset
263
-
* @mask: register mask
264
-
*/
265
-
struct rzg2l_cpg_reg_conf {
266
-
u16 off;
267
-
u16 mask;
268
-
};
269
-
270
-
#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
271
-
272
-
/**
273
-
* struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
274
-
* @mstop: MSTOP register configuration
275
-
*/
276
-
struct rzg2l_cpg_pm_domain_conf {
277
-
struct rzg2l_cpg_reg_conf mstop;
278
-
};
279
-
280
-
/**
281
-
* struct rzg2l_cpg_pm_domain_init_data - PM domain init data
282
-
* @name: PM domain name
283
-
* @conf: PM domain configuration
284
-
* @genpd_flags: genpd flags (see GENPD_FLAG_*)
285
-
* @id: PM domain ID (similar to the ones defined in
286
-
* include/dt-bindings/clock/<soc-id>-cpg.h)
287
-
*/
288
-
struct rzg2l_cpg_pm_domain_init_data {
289
-
const char * const name;
290
-
struct rzg2l_cpg_pm_domain_conf conf;
291
-
u32 genpd_flags;
292
-
u16 id;
293
-
};
294
-
295
-
#define DEF_PD(_name, _id, _mstop_conf, _flags) \
296
-
{ \
297
-
.name = (_name), \
298
-
.id = (_id), \
299
-
.conf = { \
300
-
.mstop = (_mstop_conf), \
301
-
}, \
302
-
.genpd_flags = (_flags), \
303
-
}
304
-
305
-
/**
306
256
* struct rzg2l_cpg_info - SoC-specific CPG Description
307
257
*
308
258
* @core_clks: Array of Core Clock definitions
···
275
315
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
276
316
* should not be disabled without a knowledgeable driver
277
317
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
278
-
* @pm_domains: PM domains init data array
279
-
* @num_pm_domains: Number of PM domains
280
318
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
281
319
*/
282
320
struct rzg2l_cpg_info {
···
300
342
/* Critical Module Clocks that should not be disabled */
301
343
const unsigned int *crit_mod_clks;
302
344
unsigned int num_crit_mod_clks;
303
-
304
-
/* Power domain. */
305
-
const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
306
-
unsigned int num_pm_domains;
307
345
308
346
bool has_clk_mon_regs;
309
347
};
+123
-7
drivers/clk/renesas/rzv2h-cpg.c
+123
-7
drivers/clk/renesas/rzv2h-cpg.c
···
77
77
* @resets: Array of resets
78
78
* @num_resets: Number of Module Resets in info->resets[]
79
79
* @last_dt_core_clk: ID of the last Core Clock exported to DT
80
+
* @ff_mod_status_ops: Fixed Factor Module Status Clock operations
80
81
* @mstop_count: Array of mstop values
81
82
* @rcdev: Reset controller entity
82
83
*/
···
93
92
unsigned int num_resets;
94
93
unsigned int last_dt_core_clk;
95
94
95
+
struct clk_ops *ff_mod_status_ops;
96
+
96
97
atomic_t *mstop_count;
97
98
98
99
struct reset_controller_dev rcdev;
···
104
101
105
102
struct pll_clk {
106
103
struct rzv2h_cpg_priv *priv;
107
-
void __iomem *base;
108
104
struct clk_hw hw;
109
105
struct pll pll;
110
106
};
···
121
119
* @on_bit: ON/MON bit
122
120
* @mon_index: monitor register offset
123
121
* @mon_bit: monitor bit
122
+
* @ext_clk_mux_index: mux index for external clock source, or -1 if internal
124
123
*/
125
124
struct mod_clock {
126
125
struct rzv2h_cpg_priv *priv;
···
132
129
u8 on_bit;
133
130
s8 mon_index;
134
131
u8 mon_bit;
132
+
s8 ext_clk_mux_index;
135
133
};
136
134
137
135
#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
···
151
147
};
152
148
153
149
#define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div)
150
+
151
+
/**
152
+
* struct rzv2h_ff_mod_status_clk - Fixed Factor Module Status Clock
153
+
*
154
+
* @priv: CPG private data
155
+
* @conf: fixed mod configuration
156
+
* @fix: fixed factor clock
157
+
*/
158
+
struct rzv2h_ff_mod_status_clk {
159
+
struct rzv2h_cpg_priv *priv;
160
+
struct fixed_mod_conf conf;
161
+
struct clk_fixed_factor fix;
162
+
};
163
+
164
+
#define to_rzv2h_ff_mod_status_clk(_hw) \
165
+
container_of(_hw, struct rzv2h_ff_mod_status_clk, fix.hw)
154
166
155
167
static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)
156
168
{
···
248
228
struct rzv2h_cpg_priv *priv,
249
229
const struct clk_ops *ops)
250
230
{
251
-
void __iomem *base = priv->base;
252
231
struct device *dev = priv->dev;
253
232
struct clk_init_data init;
254
233
const struct clk *parent;
···
272
253
273
254
pll_clk->hw.init = &init;
274
255
pll_clk->pll = core->cfg.pll;
275
-
pll_clk->base = base;
276
256
pll_clk->priv = priv;
277
257
278
258
ret = devm_clk_hw_register(dev, &pll_clk->hw);
···
399
381
init.ops = &rzv2h_ddiv_clk_divider_ops;
400
382
init.parent_names = &parent_name;
401
383
init.num_parents = 1;
384
+
init.flags = CLK_SET_RATE_PARENT;
402
385
403
386
ddiv->priv = priv;
404
387
ddiv->mon = cfg_ddiv.monbit;
···
435
416
return ERR_CAST(clk_hw);
436
417
437
418
return clk_hw->clk;
419
+
}
420
+
421
+
static int
422
+
rzv2h_clk_ff_mod_status_is_enabled(struct clk_hw *hw)
423
+
{
424
+
struct rzv2h_ff_mod_status_clk *fix = to_rzv2h_ff_mod_status_clk(hw);
425
+
struct rzv2h_cpg_priv *priv = fix->priv;
426
+
u32 offset = GET_CLK_MON_OFFSET(fix->conf.mon_index);
427
+
u32 bitmask = BIT(fix->conf.mon_bit);
428
+
u32 val;
429
+
430
+
val = readl(priv->base + offset);
431
+
return !!(val & bitmask);
432
+
}
433
+
434
+
static struct clk * __init
435
+
rzv2h_cpg_fixed_mod_status_clk_register(const struct cpg_core_clk *core,
436
+
struct rzv2h_cpg_priv *priv)
437
+
{
438
+
struct rzv2h_ff_mod_status_clk *clk_hw_data;
439
+
struct clk_init_data init = { };
440
+
struct clk_fixed_factor *fix;
441
+
const struct clk *parent;
442
+
const char *parent_name;
443
+
int ret;
444
+
445
+
WARN_DEBUG(core->parent >= priv->num_core_clks);
446
+
parent = priv->clks[core->parent];
447
+
if (IS_ERR(parent))
448
+
return ERR_CAST(parent);
449
+
450
+
parent_name = __clk_get_name(parent);
451
+
parent = priv->clks[core->parent];
452
+
if (IS_ERR(parent))
453
+
return ERR_CAST(parent);
454
+
455
+
clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
456
+
if (!clk_hw_data)
457
+
return ERR_PTR(-ENOMEM);
458
+
459
+
clk_hw_data->priv = priv;
460
+
clk_hw_data->conf = core->cfg.fixed_mod;
461
+
462
+
init.name = core->name;
463
+
init.ops = priv->ff_mod_status_ops;
464
+
init.flags = CLK_SET_RATE_PARENT;
465
+
init.parent_names = &parent_name;
466
+
init.num_parents = 1;
467
+
468
+
fix = &clk_hw_data->fix;
469
+
fix->hw.init = &init;
470
+
fix->mult = core->mult;
471
+
fix->div = core->div;
472
+
473
+
ret = devm_clk_hw_register(priv->dev, &clk_hw_data->fix.hw);
474
+
if (ret)
475
+
return ERR_PTR(ret);
476
+
477
+
return clk_hw_data->fix.hw.clk;
438
478
}
439
479
440
480
static struct clk
···
574
496
else
575
497
clk = clk_hw->clk;
576
498
break;
499
+
case CLK_TYPE_FF_MOD_STATUS:
500
+
if (!priv->ff_mod_status_ops) {
501
+
priv->ff_mod_status_ops =
502
+
devm_kzalloc(dev, sizeof(*priv->ff_mod_status_ops), GFP_KERNEL);
503
+
if (!priv->ff_mod_status_ops) {
504
+
clk = ERR_PTR(-ENOMEM);
505
+
goto fail;
506
+
}
507
+
memcpy(priv->ff_mod_status_ops, &clk_fixed_factor_ops,
508
+
sizeof(const struct clk_ops));
509
+
priv->ff_mod_status_ops->is_enabled = rzv2h_clk_ff_mod_status_is_enabled;
510
+
}
511
+
clk = rzv2h_cpg_fixed_mod_status_clk_register(core, priv);
512
+
break;
577
513
case CLK_TYPE_PLL:
578
514
clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops);
579
515
break;
···
655
563
spin_unlock_irqrestore(&priv->rmw_lock, flags);
656
564
}
657
565
566
+
static int rzv2h_parent_clk_mux_to_index(struct clk_hw *hw)
567
+
{
568
+
struct clk_hw *parent_hw;
569
+
struct clk *parent_clk;
570
+
struct clk_mux *mux;
571
+
u32 val;
572
+
573
+
/* This will always succeed, so no need to check for IS_ERR() */
574
+
parent_clk = clk_get_parent(hw->clk);
575
+
576
+
parent_hw = __clk_get_hw(parent_clk);
577
+
mux = to_clk_mux(parent_hw);
578
+
579
+
val = readl(mux->reg) >> mux->shift;
580
+
val &= mux->mask;
581
+
return clk_mux_val_to_index(parent_hw, mux->table, 0, val);
582
+
}
583
+
658
584
static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
659
585
{
660
586
struct mod_clock *clock = to_mod_clock(hw);
661
587
struct rzv2h_cpg_priv *priv = clock->priv;
588
+
int mon_index = clock->mon_index;
662
589
u32 bitmask;
663
590
u32 offset;
664
591
665
-
if (clock->mon_index >= 0) {
666
-
offset = GET_CLK_MON_OFFSET(clock->mon_index);
592
+
if (clock->ext_clk_mux_index >= 0 &&
593
+
rzv2h_parent_clk_mux_to_index(hw) == clock->ext_clk_mux_index)
594
+
mon_index = -1;
595
+
596
+
if (mon_index >= 0) {
597
+
offset = GET_CLK_MON_OFFSET(mon_index);
667
598
bitmask = BIT(clock->mon_bit);
668
599
669
600
if (!(readl(priv->base + offset) & bitmask))
···
802
687
clock->mon_index = mod->mon_index;
803
688
clock->mon_bit = mod->mon_bit;
804
689
clock->no_pm = mod->no_pm;
690
+
clock->ext_clk_mux_index = mod->ext_clk_mux_index;
805
691
clock->priv = priv;
806
692
clock->hw.init = &init;
807
693
clock->mstop_data = mod->mstop_data;
···
1120
1004
/* Adjust for CPG_BUS_m_MSTOP starting from m = 1 */
1121
1005
priv->mstop_count -= 16;
1122
1006
1123
-
priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *
1124
-
info->num_resets, GFP_KERNEL);
1007
+
priv->resets = devm_kmemdup_array(dev, info->resets, info->num_resets,
1008
+
sizeof(*info->resets), GFP_KERNEL);
1125
1009
if (!priv->resets)
1126
1010
return -ENOMEM;
1127
1011
+45
-4
drivers/clk/renesas/rzv2h-cpg.h
+45
-4
drivers/clk/renesas/rzv2h-cpg.h
···
9
9
#define __RENESAS_RZV2H_CPG_H__
10
10
11
11
#include <linux/bitfield.h>
12
+
#include <linux/types.h>
12
13
13
14
/**
14
15
* struct pll - Structure for PLL configuration
···
94
93
.width = (_width), \
95
94
})
96
95
96
+
/**
97
+
* struct fixed_mod_conf - Structure for fixed module configuration
98
+
*
99
+
* @mon_index: monitor index
100
+
* @mon_bit: monitor bit
101
+
*/
102
+
struct fixed_mod_conf {
103
+
u8 mon_index;
104
+
u8 mon_bit;
105
+
};
106
+
107
+
#define FIXED_MOD_CONF_PACK(_index, _bit) \
108
+
((struct fixed_mod_conf){ \
109
+
.mon_index = (_index), \
110
+
.mon_bit = (_bit), \
111
+
})
112
+
113
+
#define CPG_SSEL0 (0x300)
97
114
#define CPG_SSEL1 (0x304)
98
115
#define CPG_CDDIV0 (0x400)
99
116
#define CPG_CDDIV1 (0x404)
···
132
113
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
133
114
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
134
115
116
+
#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
117
+
#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
135
118
#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
136
119
120
+
#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1)
121
+
#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1)
122
+
#define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1)
123
+
#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1)
137
124
#define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1)
138
125
#define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1)
139
126
···
148
123
#define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
149
124
FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
150
125
#define BUS_MSTOP_NONE GENMASK(31, 0)
126
+
127
+
#define FIXED_MOD_CONF_XSPI FIXED_MOD_CONF_PACK(5, 1)
151
128
152
129
/**
153
130
* Definitions of CPG Core Clocks
···
171
144
struct ddiv ddiv;
172
145
struct pll pll;
173
146
struct smuxed smux;
147
+
struct fixed_mod_conf fixed_mod;
174
148
} cfg;
175
149
const struct clk_div_table *dtable;
176
150
const char * const *parent_names;
···
184
156
/* Generic */
185
157
CLK_TYPE_IN, /* External Clock Input */
186
158
CLK_TYPE_FF, /* Fixed Factor Clock */
159
+
CLK_TYPE_FF_MOD_STATUS, /* Fixed Factor Clock which can report the status of module clock */
187
160
CLK_TYPE_PLL,
188
161
CLK_TYPE_DDIV, /* Dynamic Switching Divider */
189
162
CLK_TYPE_SMUX, /* Static Mux */
···
200
171
DEF_TYPE(_name, _id, CLK_TYPE_IN)
201
172
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
202
173
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
174
+
#define DEF_FIXED_MOD_STATUS(_name, _id, _parent, _mult, _div, _gate) \
175
+
DEF_BASE(_name, _id, CLK_TYPE_FF_MOD_STATUS, _parent, .div = _div, \
176
+
.mult = _mult, .cfg.fixed_mod = _gate)
203
177
#define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
204
178
DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
205
179
.cfg.ddiv = _ddiv_packed, \
···
231
199
* @on_bit: ON bit
232
200
* @mon_index: monitor register index
233
201
* @mon_bit: monitor bit
202
+
* @ext_clk_mux_index: mux index for external clock source, or -1 if internal
234
203
*/
235
204
struct rzv2h_mod_clk {
236
205
const char *name;
···
243
210
u8 on_bit;
244
211
s8 mon_index;
245
212
u8 mon_bit;
213
+
s8 ext_clk_mux_index;
246
214
};
247
215
248
-
#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
216
+
#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \
217
+
_onbit, _monindex, _monbit, _ext_clk_mux_index) \
249
218
{ \
250
219
.name = (_name), \
251
220
.mstop_data = (_mstop), \
···
258
223
.on_bit = (_onbit), \
259
224
.mon_index = (_monindex), \
260
225
.mon_bit = (_monbit), \
226
+
.ext_clk_mux_index = (_ext_clk_mux_index), \
261
227
}
262
228
263
229
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
264
-
DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
230
+
DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1)
265
231
266
232
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
267
-
DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
233
+
DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1)
268
234
269
235
#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
270
-
DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
236
+
DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1)
237
+
238
+
#define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
239
+
_ext_clk_mux_index) \
240
+
DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
241
+
_ext_clk_mux_index)
271
242
272
243
/**
273
244
* struct rzv2h_reset - Reset definitions
+1
-1
drivers/clk/samsung/clk-exynos850.c
+1
-1
drivers/clk/samsung/clk-exynos850.c
···
1360
1360
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
1361
1361
};
1362
1362
1363
-
/* List of parent clocks for Muxes in CMU_CPUCL0 */
1363
+
/* List of parent clocks for Muxes in CMU_CPUCL1 */
1364
1364
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
1365
1365
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
1366
1366
PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };
+72
drivers/clk/samsung/clk-exynosautov920.c
+72
drivers/clk/samsung/clk-exynosautov920.c
···
26
26
#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
27
27
#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
28
28
#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
29
+
#define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1)
29
30
30
31
/* ---- CMU_TOP ------------------------------------------------------------ */
31
32
···
1753
1752
.clk_name = "noc",
1754
1753
};
1755
1754
1755
+
/* ---- CMU_HSI2 --------------------------------------------------------- */
1756
+
1757
+
/* Register Offset definitions for CMU_HSI2 (0x16b00000) */
1758
+
#define PLL_LOCKTIME_PLL_ETH 0x0
1759
+
#define PLL_CON3_PLL_ETH 0x10c
1760
+
#define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER 0x600
1761
+
#define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER 0x610
1762
+
#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x630
1763
+
#define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET 0x1000
1764
+
#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET 0x1800
1765
+
#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP 0x1804
1766
+
1767
+
static const unsigned long hsi2_clk_regs[] __initconst = {
1768
+
PLL_LOCKTIME_PLL_ETH,
1769
+
PLL_CON3_PLL_ETH,
1770
+
PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER,
1771
+
PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER,
1772
+
PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
1773
+
CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET,
1774
+
CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
1775
+
CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
1776
+
};
1777
+
1778
+
static const struct samsung_pll_clock hsi2_pll_clks[] __initconst = {
1779
+
/* CMU_HSI2_PLL */
1780
+
PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",
1781
+
PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL),
1782
+
};
1783
+
1784
+
/* List of parent clocks for Muxes in CMU_HSI2 */
1785
+
PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) = { "oscclk", "dout_clkcmu_hsi2_noc_ufs" };
1786
+
PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi2_ufs_embd" };
1787
+
PNAME(mout_hsi2_ethernet_p) = { "fout_pll_eth", "mout_clkcmu_hsi2_ethernet_user" };
1788
+
PNAME(mout_clkcmu_hsi2_ethernet_user_p) = { "oscclk", "dout_clkcmu_hsi2_ethernet" };
1789
+
1790
+
static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
1791
+
MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",
1792
+
mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 4, 1),
1793
+
MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",
1794
+
mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 4, 1),
1795
+
MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",
1796
+
mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1),
1797
+
MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",
1798
+
mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 4, 1),
1799
+
};
1800
+
1801
+
static const struct samsung_div_clock hsi2_div_clks[] __initconst = {
1802
+
DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",
1803
+
"mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
1804
+
0, 4),
1805
+
DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",
1806
+
"mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
1807
+
0, 4),
1808
+
};
1809
+
1810
+
static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
1811
+
.pll_clks = hsi2_pll_clks,
1812
+
.nr_pll_clks = ARRAY_SIZE(hsi2_pll_clks),
1813
+
.mux_clks = hsi2_mux_clks,
1814
+
.nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
1815
+
.div_clks = hsi2_div_clks,
1816
+
.nr_div_clks = ARRAY_SIZE(hsi2_div_clks),
1817
+
.nr_clk_ids = CLKS_NR_HSI2,
1818
+
.clk_regs = hsi2_clk_regs,
1819
+
.nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs),
1820
+
.clk_name = "noc",
1821
+
};
1822
+
1756
1823
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
1757
1824
{
1758
1825
const struct samsung_cmu_info *info;
···
1848
1779
}, {
1849
1780
.compatible = "samsung,exynosautov920-cmu-hsi1",
1850
1781
.data = &hsi1_cmu_info,
1782
+
}, {
1783
+
.compatible = "samsung,exynosautov920-cmu-hsi2",
1784
+
.data = &hsi2_cmu_info,
1851
1785
},
1852
1786
{ }
1853
1787
};
+2
-2
drivers/clk/samsung/clk-gs101.c
+2
-2
drivers/clk/samsung/clk-gs101.c
···
1154
1154
CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
1155
1155
DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa",
1156
1156
CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
1157
-
DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
1157
+
DIV(CLK_DOUT_CMU_G3D_BUSD, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
1158
1158
CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
1159
1159
DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
1160
1160
CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
···
2129
2129
"dout_cmu_hsi0_usbdpdbg" };
2130
2130
PNAME(mout_hsi0_bus_p) = { "mout_hsi0_bus_user",
2131
2131
"mout_hsi0_alt_user" };
2132
-
PNAME(mout_hsi0_usb20_ref_p) = { "fout_usb_pll",
2132
+
PNAME(mout_hsi0_usb20_ref_p) = { "mout_pll_usb",
2133
2133
"mout_hsi0_tcxo_user" };
2134
2134
PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll",
2135
2135
"mout_hsi0_usb31drd_user",
+1
drivers/clk/spacemit/Kconfig
+1
drivers/clk/spacemit/Kconfig
+121
-121
drivers/clk/spacemit/ccu-k1.c
+121
-121
drivers/clk/spacemit/ccu-k1.c
···
5
5
*/
6
6
7
7
#include <linux/array_size.h>
8
+
#include <linux/auxiliary_bus.h>
8
9
#include <linux/clk-provider.h>
9
10
#include <linux/delay.h>
11
+
#include <linux/idr.h>
10
12
#include <linux/mfd/syscon.h>
11
13
#include <linux/minmax.h>
12
14
#include <linux/module.h>
13
15
#include <linux/platform_device.h>
16
+
#include <linux/slab.h>
17
+
#include <soc/spacemit/k1-syscon.h>
14
18
15
19
#include "ccu_common.h"
16
20
#include "ccu_pll.h"
···
23
19
24
20
#include <dt-bindings/clock/spacemit,k1-syscon.h>
25
21
26
-
/* APBS register offset */
27
-
#define APBS_PLL1_SWCR1 0x100
28
-
#define APBS_PLL1_SWCR2 0x104
29
-
#define APBS_PLL1_SWCR3 0x108
30
-
#define APBS_PLL2_SWCR1 0x118
31
-
#define APBS_PLL2_SWCR2 0x11c
32
-
#define APBS_PLL2_SWCR3 0x120
33
-
#define APBS_PLL3_SWCR1 0x124
34
-
#define APBS_PLL3_SWCR2 0x128
35
-
#define APBS_PLL3_SWCR3 0x12c
36
-
37
-
/* MPMU register offset */
38
-
#define MPMU_POSR 0x0010
39
-
#define POSR_PLL1_LOCK BIT(27)
40
-
#define POSR_PLL2_LOCK BIT(28)
41
-
#define POSR_PLL3_LOCK BIT(29)
42
-
#define MPMU_SUCCR 0x0014
43
-
#define MPMU_ISCCR 0x0044
44
-
#define MPMU_WDTPCR 0x0200
45
-
#define MPMU_RIPCCR 0x0210
46
-
#define MPMU_ACGR 0x1024
47
-
#define MPMU_APBCSCR 0x1050
48
-
#define MPMU_SUCCR_1 0x10b0
49
-
50
-
/* APBC register offset */
51
-
#define APBC_UART1_CLK_RST 0x00
52
-
#define APBC_UART2_CLK_RST 0x04
53
-
#define APBC_GPIO_CLK_RST 0x08
54
-
#define APBC_PWM0_CLK_RST 0x0c
55
-
#define APBC_PWM1_CLK_RST 0x10
56
-
#define APBC_PWM2_CLK_RST 0x14
57
-
#define APBC_PWM3_CLK_RST 0x18
58
-
#define APBC_TWSI8_CLK_RST 0x20
59
-
#define APBC_UART3_CLK_RST 0x24
60
-
#define APBC_RTC_CLK_RST 0x28
61
-
#define APBC_TWSI0_CLK_RST 0x2c
62
-
#define APBC_TWSI1_CLK_RST 0x30
63
-
#define APBC_TIMERS1_CLK_RST 0x34
64
-
#define APBC_TWSI2_CLK_RST 0x38
65
-
#define APBC_AIB_CLK_RST 0x3c
66
-
#define APBC_TWSI4_CLK_RST 0x40
67
-
#define APBC_TIMERS2_CLK_RST 0x44
68
-
#define APBC_ONEWIRE_CLK_RST 0x48
69
-
#define APBC_TWSI5_CLK_RST 0x4c
70
-
#define APBC_DRO_CLK_RST 0x58
71
-
#define APBC_IR_CLK_RST 0x5c
72
-
#define APBC_TWSI6_CLK_RST 0x60
73
-
#define APBC_COUNTER_CLK_SEL 0x64
74
-
#define APBC_TWSI7_CLK_RST 0x68
75
-
#define APBC_TSEN_CLK_RST 0x6c
76
-
#define APBC_UART4_CLK_RST 0x70
77
-
#define APBC_UART5_CLK_RST 0x74
78
-
#define APBC_UART6_CLK_RST 0x78
79
-
#define APBC_SSP3_CLK_RST 0x7c
80
-
#define APBC_SSPA0_CLK_RST 0x80
81
-
#define APBC_SSPA1_CLK_RST 0x84
82
-
#define APBC_IPC_AP2AUD_CLK_RST 0x90
83
-
#define APBC_UART7_CLK_RST 0x94
84
-
#define APBC_UART8_CLK_RST 0x98
85
-
#define APBC_UART9_CLK_RST 0x9c
86
-
#define APBC_CAN0_CLK_RST 0xa0
87
-
#define APBC_PWM4_CLK_RST 0xa8
88
-
#define APBC_PWM5_CLK_RST 0xac
89
-
#define APBC_PWM6_CLK_RST 0xb0
90
-
#define APBC_PWM7_CLK_RST 0xb4
91
-
#define APBC_PWM8_CLK_RST 0xb8
92
-
#define APBC_PWM9_CLK_RST 0xbc
93
-
#define APBC_PWM10_CLK_RST 0xc0
94
-
#define APBC_PWM11_CLK_RST 0xc4
95
-
#define APBC_PWM12_CLK_RST 0xc8
96
-
#define APBC_PWM13_CLK_RST 0xcc
97
-
#define APBC_PWM14_CLK_RST 0xd0
98
-
#define APBC_PWM15_CLK_RST 0xd4
99
-
#define APBC_PWM16_CLK_RST 0xd8
100
-
#define APBC_PWM17_CLK_RST 0xdc
101
-
#define APBC_PWM18_CLK_RST 0xe0
102
-
#define APBC_PWM19_CLK_RST 0xe4
103
-
104
-
/* APMU register offset */
105
-
#define APMU_JPG_CLK_RES_CTRL 0x020
106
-
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
107
-
#define APMU_ISP_CLK_RES_CTRL 0x038
108
-
#define APMU_LCD_CLK_RES_CTRL1 0x044
109
-
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
110
-
#define APMU_LCD_CLK_RES_CTRL2 0x04c
111
-
#define APMU_CCIC_CLK_RES_CTRL 0x050
112
-
#define APMU_SDH0_CLK_RES_CTRL 0x054
113
-
#define APMU_SDH1_CLK_RES_CTRL 0x058
114
-
#define APMU_USB_CLK_RES_CTRL 0x05c
115
-
#define APMU_QSPI_CLK_RES_CTRL 0x060
116
-
#define APMU_DMA_CLK_RES_CTRL 0x064
117
-
#define APMU_AES_CLK_RES_CTRL 0x068
118
-
#define APMU_VPU_CLK_RES_CTRL 0x0a4
119
-
#define APMU_GPU_CLK_RES_CTRL 0x0cc
120
-
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
121
-
#define APMU_PMUA_MC_CTRL 0x0e8
122
-
#define APMU_PMU_CC2_AP 0x100
123
-
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
124
-
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
125
-
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
126
-
#define APMU_CCI550_CLK_CTRL 0x300
127
-
#define APMU_ACLK_CLK_CTRL 0x388
128
-
#define APMU_CPU_C0_CLK_CTRL 0x38C
129
-
#define APMU_CPU_C1_CLK_CTRL 0x390
130
-
#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
131
-
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
132
-
#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
133
-
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
134
-
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
135
-
136
22
struct spacemit_ccu_data {
23
+
const char *reset_name;
137
24
struct clk_hw **hws;
138
25
size_t num;
139
26
};
27
+
28
+
static DEFINE_IDA(auxiliary_ids);
140
29
141
30
/* APBS clocks start, APBS region contains and only contains all PLL clocks */
142
31
···
67
170
CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1);
68
171
CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1);
69
172
CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1);
70
-
CCU_FACTOR_GATE_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1);
173
+
CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1,
174
+
CLK_IS_CRITICAL);
71
175
CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1);
72
176
CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1);
73
177
CCU_FACTOR_GATE_DEFINE(pll1_d23_106p8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(20), 23, 1);
···
717
819
};
718
820
719
821
static const struct spacemit_ccu_data k1_ccu_pll_data = {
720
-
.hws = k1_ccu_pll_hws,
721
-
.num = ARRAY_SIZE(k1_ccu_pll_hws),
822
+
/* The PLL CCU implements no resets */
823
+
.hws = k1_ccu_pll_hws,
824
+
.num = ARRAY_SIZE(k1_ccu_pll_hws),
722
825
};
723
826
724
827
static struct clk_hw *k1_ccu_mpmu_hws[] = {
···
759
860
};
760
861
761
862
static const struct spacemit_ccu_data k1_ccu_mpmu_data = {
762
-
.hws = k1_ccu_mpmu_hws,
763
-
.num = ARRAY_SIZE(k1_ccu_mpmu_hws),
863
+
.reset_name = "mpmu-reset",
864
+
.hws = k1_ccu_mpmu_hws,
865
+
.num = ARRAY_SIZE(k1_ccu_mpmu_hws),
764
866
};
765
867
766
868
static struct clk_hw *k1_ccu_apbc_hws[] = {
···
868
968
};
869
969
870
970
static const struct spacemit_ccu_data k1_ccu_apbc_data = {
871
-
.hws = k1_ccu_apbc_hws,
872
-
.num = ARRAY_SIZE(k1_ccu_apbc_hws),
971
+
.reset_name = "apbc-reset",
972
+
.hws = k1_ccu_apbc_hws,
973
+
.num = ARRAY_SIZE(k1_ccu_apbc_hws),
873
974
};
874
975
875
976
static struct clk_hw *k1_ccu_apmu_hws[] = {
···
939
1038
};
940
1039
941
1040
static const struct spacemit_ccu_data k1_ccu_apmu_data = {
942
-
.hws = k1_ccu_apmu_hws,
943
-
.num = ARRAY_SIZE(k1_ccu_apmu_hws),
1041
+
.reset_name = "apmu-reset",
1042
+
.hws = k1_ccu_apmu_hws,
1043
+
.num = ARRAY_SIZE(k1_ccu_apmu_hws),
1044
+
};
1045
+
1046
+
static const struct spacemit_ccu_data k1_ccu_rcpu_data = {
1047
+
.reset_name = "rcpu-reset",
1048
+
};
1049
+
1050
+
static const struct spacemit_ccu_data k1_ccu_rcpu2_data = {
1051
+
.reset_name = "rcpu2-reset",
1052
+
};
1053
+
1054
+
static const struct spacemit_ccu_data k1_ccu_apbc2_data = {
1055
+
.reset_name = "apbc2-reset",
944
1056
};
945
1057
946
1058
static int spacemit_ccu_register(struct device *dev,
···
963
1049
{
964
1050
struct clk_hw_onecell_data *clk_data;
965
1051
int i, ret;
1052
+
1053
+
/* Nothing to do if the CCU does not implement any clocks */
1054
+
if (!data->hws)
1055
+
return 0;
966
1056
967
1057
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
968
1058
GFP_KERNEL);
···
1008
1090
return ret;
1009
1091
}
1010
1092
1093
+
static void spacemit_cadev_release(struct device *dev)
1094
+
{
1095
+
struct auxiliary_device *adev = to_auxiliary_dev(dev);
1096
+
1097
+
ida_free(&auxiliary_ids, adev->id);
1098
+
kfree(to_spacemit_ccu_adev(adev));
1099
+
}
1100
+
1101
+
static void spacemit_adev_unregister(void *data)
1102
+
{
1103
+
struct auxiliary_device *adev = data;
1104
+
1105
+
auxiliary_device_delete(adev);
1106
+
auxiliary_device_uninit(adev);
1107
+
}
1108
+
1109
+
static int spacemit_ccu_reset_register(struct device *dev,
1110
+
struct regmap *regmap,
1111
+
const char *reset_name)
1112
+
{
1113
+
struct spacemit_ccu_adev *cadev;
1114
+
struct auxiliary_device *adev;
1115
+
int ret;
1116
+
1117
+
/* Nothing to do if the CCU does not implement a reset controller */
1118
+
if (!reset_name)
1119
+
return 0;
1120
+
1121
+
cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
1122
+
if (!cadev)
1123
+
return -ENOMEM;
1124
+
1125
+
cadev->regmap = regmap;
1126
+
1127
+
adev = &cadev->adev;
1128
+
adev->name = reset_name;
1129
+
adev->dev.parent = dev;
1130
+
adev->dev.release = spacemit_cadev_release;
1131
+
adev->dev.of_node = dev->of_node;
1132
+
ret = ida_alloc(&auxiliary_ids, GFP_KERNEL);
1133
+
if (ret < 0)
1134
+
goto err_free_cadev;
1135
+
adev->id = ret;
1136
+
1137
+
ret = auxiliary_device_init(adev);
1138
+
if (ret)
1139
+
goto err_free_aux_id;
1140
+
1141
+
ret = auxiliary_device_add(adev);
1142
+
if (ret) {
1143
+
auxiliary_device_uninit(adev);
1144
+
return ret;
1145
+
}
1146
+
1147
+
return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev);
1148
+
1149
+
err_free_aux_id:
1150
+
ida_free(&auxiliary_ids, adev->id);
1151
+
err_free_cadev:
1152
+
kfree(cadev);
1153
+
1154
+
return ret;
1155
+
}
1156
+
1011
1157
static int k1_ccu_probe(struct platform_device *pdev)
1012
1158
{
1013
1159
struct regmap *base_regmap, *lock_regmap = NULL;
1160
+
const struct spacemit_ccu_data *data;
1014
1161
struct device *dev = &pdev->dev;
1015
1162
int ret;
1016
1163
···
1104
1121
"failed to get lock regmap\n");
1105
1122
}
1106
1123
1107
-
ret = spacemit_ccu_register(dev, base_regmap, lock_regmap,
1108
-
of_device_get_match_data(dev));
1124
+
data = of_device_get_match_data(dev);
1125
+
1126
+
ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data);
1109
1127
if (ret)
1110
1128
return dev_err_probe(dev, ret, "failed to register clocks\n");
1129
+
1130
+
ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name);
1131
+
if (ret)
1132
+
return dev_err_probe(dev, ret, "failed to register resets\n");
1111
1133
1112
1134
return 0;
1113
1135
}
···
1133
1145
{
1134
1146
.compatible = "spacemit,k1-syscon-apmu",
1135
1147
.data = &k1_ccu_apmu_data,
1148
+
},
1149
+
{
1150
+
.compatible = "spacemit,k1-syscon-rcpu",
1151
+
.data = &k1_ccu_rcpu_data,
1152
+
},
1153
+
{
1154
+
.compatible = "spacemit,k1-syscon-rcpu2",
1155
+
.data = &k1_ccu_rcpu2_data,
1156
+
},
1157
+
{
1158
+
.compatible = "spacemit,k1-syscon-apbc2",
1159
+
.data = &k1_ccu_apbc2_data,
1136
1160
},
1137
1161
{ }
1138
1162
};
+8
-3
drivers/clk/spacemit/ccu_mix.h
+8
-3
drivers/clk/spacemit/ccu_mix.h
···
101
101
} \
102
102
}
103
103
104
-
#define CCU_FACTOR_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
105
-
_mul) \
104
+
#define CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
105
+
_mul, _flags) \
106
106
static struct ccu_mix _name = { \
107
107
.gate = CCU_GATE_INIT(_mask_gate), \
108
108
.factor = CCU_FACTOR_INIT(_div, _mul), \
109
109
.common = { \
110
110
.reg_ctrl = _reg_ctrl, \
111
-
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_gate_ops, 0) \
111
+
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_gate_ops, _flags) \
112
112
} \
113
113
}
114
+
115
+
#define CCU_FACTOR_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
116
+
_mul) \
117
+
CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
118
+
_mul, 0)
114
119
115
120
#define CCU_MUX_GATE_DEFINE(_name, _parents, _reg_ctrl, _shift, _width, \
116
121
_mask_gate, _flags) \
+1
-1
drivers/clk/spacemit/ccu_pll.c
+1
-1
drivers/clk/spacemit/ccu_pll.c
+1
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
+1
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
+19
-3
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+19
-3
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
···
347
347
348
348
static const char * const de_parents[] = { "pll-video", "pll-periph0" };
349
349
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
350
-
0x104, 0, 4, 24, 2, BIT(31),
351
-
CLK_SET_RATE_PARENT);
350
+
0x104, 0, 4, 24, 3, BIT(31),
351
+
CLK_SET_RATE_NO_REPARENT);
352
352
353
353
static const char * const tcon_parents[] = { "pll-video" };
354
354
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
355
-
0x118, 0, 4, 24, 3, BIT(31), 0);
355
+
0x118, 0, 4, 24, 3, BIT(31),
356
+
CLK_SET_RATE_NO_REPARENT);
356
357
357
358
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
358
359
0x130, BIT(31), 0);
···
754
753
val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
755
754
val &= ~GENMASK(19, 16);
756
755
writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG);
756
+
757
+
/*
758
+
* Assign the DE and TCON clock to the video PLL. Both clocks need to
759
+
* have the same parent for the units to work together.
760
+
*/
761
+
762
+
val = readl(reg + de_clk.common.reg);
763
+
val &= ~GENMASK(de_clk.mux.shift + de_clk.mux.width - 1,
764
+
de_clk.mux.shift);
765
+
writel(val, reg + de_clk.common.reg);
766
+
767
+
val = readl(reg + tcon_clk.common.reg);
768
+
val &= ~GENMASK(tcon_clk.mux.shift + tcon_clk.mux.width - 1,
769
+
tcon_clk.mux.shift);
770
+
writel(val, reg + tcon_clk.common.reg);
757
771
758
772
return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
759
773
}
+8
-6
drivers/clk/sunxi-ng/ccu_gate.c
+8
-6
drivers/clk/sunxi-ng/ccu_gate.c
···
91
91
return rate;
92
92
}
93
93
94
-
static long ccu_gate_round_rate(struct clk_hw *hw, unsigned long rate,
95
-
unsigned long *prate)
94
+
static int ccu_gate_determine_rate(struct clk_hw *hw,
95
+
struct clk_rate_request *req)
96
96
{
97
97
struct ccu_gate *cg = hw_to_ccu_gate(hw);
98
98
int div = 1;
···
101
101
div = cg->common.prediv;
102
102
103
103
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
104
-
unsigned long best_parent = rate;
104
+
unsigned long best_parent = req->rate;
105
105
106
106
if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
107
107
best_parent *= div;
108
-
*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
108
+
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
109
109
}
110
110
111
-
return *prate / div;
111
+
req->rate = req->best_parent_rate / div;
112
+
113
+
return 0;
112
114
}
113
115
114
116
static int ccu_gate_set_rate(struct clk_hw *hw, unsigned long rate,
···
129
127
.disable = ccu_gate_disable,
130
128
.enable = ccu_gate_enable,
131
129
.is_enabled = ccu_gate_is_enabled,
132
-
.round_rate = ccu_gate_round_rate,
130
+
.determine_rate = ccu_gate_determine_rate,
133
131
.set_rate = ccu_gate_set_rate,
134
132
.recalc_rate = ccu_gate_recalc_rate,
135
133
};
+7
-7
drivers/clk/sunxi-ng/ccu_nk.c
+7
-7
drivers/clk/sunxi-ng/ccu_nk.c
···
92
92
return rate;
93
93
}
94
94
95
-
static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
96
-
unsigned long *parent_rate)
95
+
static int ccu_nk_determine_rate(struct clk_hw *hw,
96
+
struct clk_rate_request *req)
97
97
{
98
98
struct ccu_nk *nk = hw_to_ccu_nk(hw);
99
99
struct _ccu_nk _nk;
100
100
101
101
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
102
-
rate *= nk->fixed_post_div;
102
+
req->rate *= nk->fixed_post_div;
103
103
104
104
_nk.min_n = nk->n.min ?: 1;
105
105
_nk.max_n = nk->n.max ?: 1 << nk->n.width;
106
106
_nk.min_k = nk->k.min ?: 1;
107
107
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
108
108
109
-
rate = ccu_nk_find_best(*parent_rate, rate, &_nk);
109
+
req->rate = ccu_nk_find_best(req->best_parent_rate, req->rate, &_nk);
110
110
111
111
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
112
-
rate = rate / nk->fixed_post_div;
112
+
req->rate = req->rate / nk->fixed_post_div;
113
113
114
-
return rate;
114
+
return 0;
115
115
}
116
116
117
117
static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
···
155
155
.is_enabled = ccu_nk_is_enabled,
156
156
157
157
.recalc_rate = ccu_nk_recalc_rate,
158
-
.round_rate = ccu_nk_round_rate,
158
+
.determine_rate = ccu_nk_determine_rate,
159
159
.set_rate = ccu_nk_set_rate,
160
160
};
161
161
EXPORT_SYMBOL_NS_GPL(ccu_nk_ops, "SUNXI_CCU");
+12
-11
drivers/clk/sunxi-ng/ccu_nkmp.c
+12
-11
drivers/clk/sunxi-ng/ccu_nkmp.c
···
127
127
return rate;
128
128
}
129
129
130
-
static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
131
-
unsigned long *parent_rate)
130
+
static int ccu_nkmp_determine_rate(struct clk_hw *hw,
131
+
struct clk_rate_request *req)
132
132
{
133
133
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
134
134
struct _ccu_nkmp _nkmp;
135
135
136
136
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
137
-
rate *= nkmp->fixed_post_div;
137
+
req->rate *= nkmp->fixed_post_div;
138
138
139
-
if (nkmp->max_rate && rate > nkmp->max_rate) {
140
-
rate = nkmp->max_rate;
139
+
if (nkmp->max_rate && req->rate > nkmp->max_rate) {
140
+
req->rate = nkmp->max_rate;
141
141
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
142
-
rate /= nkmp->fixed_post_div;
143
-
return rate;
142
+
req->rate /= nkmp->fixed_post_div;
143
+
return 0;
144
144
}
145
145
146
146
_nkmp.min_n = nkmp->n.min ?: 1;
···
152
152
_nkmp.min_p = 1;
153
153
_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
154
154
155
-
rate = ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
155
+
req->rate = ccu_nkmp_find_best(req->best_parent_rate, req->rate,
156
+
&_nkmp);
156
157
157
158
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
158
-
rate = rate / nkmp->fixed_post_div;
159
+
req->rate = req->rate / nkmp->fixed_post_div;
159
160
160
-
return rate;
161
+
return 0;
161
162
}
162
163
163
164
static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
···
228
227
.is_enabled = ccu_nkmp_is_enabled,
229
228
230
229
.recalc_rate = ccu_nkmp_recalc_rate,
231
-
.round_rate = ccu_nkmp_round_rate,
230
+
.determine_rate = ccu_nkmp_determine_rate,
232
231
.set_rate = ccu_nkmp_set_rate,
233
232
};
234
233
EXPORT_SYMBOL_NS_GPL(ccu_nkmp_ops, "SUNXI_CCU");
+22
-21
drivers/clk/sunxi-ng/ccu_nm.c
+22
-21
drivers/clk/sunxi-ng/ccu_nm.c
···
116
116
return rate;
117
117
}
118
118
119
-
static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
120
-
unsigned long *parent_rate)
119
+
static int ccu_nm_determine_rate(struct clk_hw *hw,
120
+
struct clk_rate_request *req)
121
121
{
122
122
struct ccu_nm *nm = hw_to_ccu_nm(hw);
123
123
struct _ccu_nm _nm;
124
124
125
125
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
126
-
rate *= nm->fixed_post_div;
126
+
req->rate *= nm->fixed_post_div;
127
127
128
-
if (rate < nm->min_rate) {
129
-
rate = nm->min_rate;
128
+
if (req->rate < nm->min_rate) {
129
+
req->rate = nm->min_rate;
130
130
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
131
-
rate /= nm->fixed_post_div;
132
-
return rate;
131
+
req->rate /= nm->fixed_post_div;
132
+
return 0;
133
133
}
134
134
135
-
if (nm->max_rate && rate > nm->max_rate) {
136
-
rate = nm->max_rate;
135
+
if (nm->max_rate && req->rate > nm->max_rate) {
136
+
req->rate = nm->max_rate;
137
137
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
138
-
rate /= nm->fixed_post_div;
139
-
return rate;
138
+
req->rate /= nm->fixed_post_div;
139
+
return 0;
140
140
}
141
141
142
-
if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
142
+
if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, req->rate)) {
143
143
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
144
-
rate /= nm->fixed_post_div;
145
-
return rate;
144
+
req->rate /= nm->fixed_post_div;
145
+
return 0;
146
146
}
147
147
148
-
if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate)) {
148
+
if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, req->rate)) {
149
149
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
150
-
rate /= nm->fixed_post_div;
151
-
return rate;
150
+
req->rate /= nm->fixed_post_div;
151
+
return 0;
152
152
}
153
153
154
154
_nm.min_n = nm->n.min ?: 1;
···
156
156
_nm.min_m = 1;
157
157
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
158
158
159
-
rate = ccu_nm_find_best(&nm->common, *parent_rate, rate, &_nm);
159
+
req->rate = ccu_nm_find_best(&nm->common, req->best_parent_rate,
160
+
req->rate, &_nm);
160
161
161
162
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
162
-
rate /= nm->fixed_post_div;
163
+
req->rate /= nm->fixed_post_div;
163
164
164
-
return rate;
165
+
return 0;
165
166
}
166
167
167
168
static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
···
234
233
.is_enabled = ccu_nm_is_enabled,
235
234
236
235
.recalc_rate = ccu_nm_recalc_rate,
237
-
.round_rate = ccu_nm_round_rate,
236
+
.determine_rate = ccu_nm_determine_rate,
238
237
.set_rate = ccu_nm_set_rate,
239
238
};
240
239
EXPORT_SYMBOL_NS_GPL(ccu_nm_ops, "SUNXI_CCU");
+9
drivers/reset/Kconfig
+9
drivers/reset/Kconfig
···
270
270
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
271
271
driver gets initialized early during platform init calls.
272
272
273
+
config RESET_SPACEMIT
274
+
tristate "SpacemiT reset driver"
275
+
depends on ARCH_SPACEMIT || COMPILE_TEST
276
+
select AUXILIARY_BUS
277
+
default ARCH_SPACEMIT
278
+
help
279
+
This enables the reset controller driver for SpacemiT SoCs,
280
+
including the K1.
281
+
273
282
config RESET_SUNPLUS
274
283
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
275
284
default ARCH_SUNPLUS
+1
drivers/reset/Makefile
+1
drivers/reset/Makefile
···
35
35
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
36
36
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
37
37
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
38
+
obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
38
39
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
39
40
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
40
41
obj-$(CONFIG_RESET_TH1520) += reset-th1520.o
+304
drivers/reset/reset-spacemit.c
+304
drivers/reset/reset-spacemit.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
/* SpacemiT reset controller driver */
4
+
5
+
#include <linux/auxiliary_bus.h>
6
+
#include <linux/container_of.h>
7
+
#include <linux/device.h>
8
+
#include <linux/module.h>
9
+
#include <linux/regmap.h>
10
+
#include <linux/reset-controller.h>
11
+
#include <linux/types.h>
12
+
13
+
#include <soc/spacemit/k1-syscon.h>
14
+
#include <dt-bindings/clock/spacemit,k1-syscon.h>
15
+
16
+
struct ccu_reset_data {
17
+
u32 offset;
18
+
u32 assert_mask;
19
+
u32 deassert_mask;
20
+
};
21
+
22
+
struct ccu_reset_controller_data {
23
+
const struct ccu_reset_data *reset_data; /* array */
24
+
size_t count;
25
+
};
26
+
27
+
struct ccu_reset_controller {
28
+
struct reset_controller_dev rcdev;
29
+
const struct ccu_reset_controller_data *data;
30
+
struct regmap *regmap;
31
+
};
32
+
33
+
#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \
34
+
{ \
35
+
.offset = (_offset), \
36
+
.assert_mask = (_assert_mask), \
37
+
.deassert_mask = (_deassert_mask), \
38
+
}
39
+
40
+
static const struct ccu_reset_data k1_mpmu_resets[] = {
41
+
[RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0),
42
+
};
43
+
44
+
static const struct ccu_reset_controller_data k1_mpmu_reset_data = {
45
+
.reset_data = k1_mpmu_resets,
46
+
.count = ARRAY_SIZE(k1_mpmu_resets),
47
+
};
48
+
49
+
static const struct ccu_reset_data k1_apbc_resets[] = {
50
+
[RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0),
51
+
[RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
52
+
[RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0),
53
+
[RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)),
54
+
[RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)),
55
+
[RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)),
56
+
[RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)),
57
+
[RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)),
58
+
[RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)),
59
+
[RESET_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)),
60
+
[RESET_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)),
61
+
[RESET_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)),
62
+
[RESET_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)),
63
+
[RESET_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)),
64
+
[RESET_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)),
65
+
[RESET_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)),
66
+
[RESET_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)),
67
+
[RESET_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)),
68
+
[RESET_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)),
69
+
[RESET_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)),
70
+
[RESET_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)),
71
+
[RESET_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)),
72
+
[RESET_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)),
73
+
[RESET_SSP3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0),
74
+
[RESET_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0),
75
+
[RESET_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0),
76
+
[RESET_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0),
77
+
[RESET_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0),
78
+
[RESET_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0),
79
+
[RESET_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0),
80
+
[RESET_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0),
81
+
[RESET_SSPA0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0),
82
+
[RESET_SSPA1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0),
83
+
[RESET_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0),
84
+
[RESET_IR] = RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0),
85
+
[RESET_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0),
86
+
[RESET_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0),
87
+
[RESET_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0),
88
+
[RESET_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0),
89
+
[RESET_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0),
90
+
[RESET_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0),
91
+
[RESET_TWSI7] = RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0),
92
+
[RESET_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0),
93
+
[RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0),
94
+
[RESET_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0),
95
+
[RESET_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0),
96
+
[RESET_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0),
97
+
[RESET_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0),
98
+
[RESET_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0),
99
+
[RESET_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0),
100
+
[RESET_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0),
101
+
};
102
+
103
+
static const struct ccu_reset_controller_data k1_apbc_reset_data = {
104
+
.reset_data = k1_apbc_resets,
105
+
.count = ARRAY_SIZE(k1_apbc_resets),
106
+
};
107
+
108
+
static const struct ccu_reset_data k1_apmu_resets[] = {
109
+
[RESET_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)),
110
+
[RESET_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)),
111
+
[RESET_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)),
112
+
[RESET_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
113
+
[RESET_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
114
+
[RESET_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
115
+
[RESET_USBP1_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)),
116
+
[RESET_USB_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)),
117
+
[RESET_USB30_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
118
+
[RESET_USB30_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
119
+
[RESET_USB30_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
120
+
[RESET_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
121
+
[RESET_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
122
+
[RESET_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
123
+
[RESET_AES] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)),
124
+
[RESET_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)),
125
+
[RESET_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)),
126
+
[RESET_EMMC] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)),
127
+
[RESET_EMMC_X] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)),
128
+
[RESET_AUDIO_SYS] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(0)),
129
+
[RESET_AUDIO_MCU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(2)),
130
+
[RESET_AUDIO_APMU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(3)),
131
+
[RESET_HDMI] = RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)),
132
+
[RESET_PCIE0_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(3)),
133
+
[RESET_PCIE0_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(4)),
134
+
[RESET_PCIE0_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(5)),
135
+
[RESET_PCIE0_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0),
136
+
[RESET_PCIE1_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(3)),
137
+
[RESET_PCIE1_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(4)),
138
+
[RESET_PCIE1_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(5)),
139
+
[RESET_PCIE1_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), 0),
140
+
[RESET_PCIE2_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(3)),
141
+
[RESET_PCIE2_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(4)),
142
+
[RESET_PCIE2_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(5)),
143
+
[RESET_PCIE2_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), 0),
144
+
[RESET_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
145
+
[RESET_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
146
+
[RESET_JPG] = RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)),
147
+
[RESET_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)),
148
+
[RESET_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)),
149
+
[RESET_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)),
150
+
[RESET_ISP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)),
151
+
[RESET_ISP_CPP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)),
152
+
[RESET_ISP_BUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)),
153
+
[RESET_ISP_CI] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)),
154
+
[RESET_DPU_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)),
155
+
[RESET_DPU_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)),
156
+
[RESET_DPU_HCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)),
157
+
[RESET_DPU_SPIBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)),
158
+
[RESET_DPU_SPI_HBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)),
159
+
[RESET_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)),
160
+
[RESET_MIPI] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)),
161
+
[RESET_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)),
162
+
};
163
+
164
+
static const struct ccu_reset_controller_data k1_apmu_reset_data = {
165
+
.reset_data = k1_apmu_resets,
166
+
.count = ARRAY_SIZE(k1_apmu_resets),
167
+
};
168
+
169
+
static const struct ccu_reset_data k1_rcpu_resets[] = {
170
+
[RESET_RCPU_SSP0] = RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)),
171
+
[RESET_RCPU_I2C0] = RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)),
172
+
[RESET_RCPU_UART1] = RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)),
173
+
[RESET_RCPU_IR] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)),
174
+
[RESET_RCPU_CAN] = RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)),
175
+
[RESET_RCPU_UART0] = RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)),
176
+
[RESET_RCPU_HDMI_AUDIO] = RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)),
177
+
};
178
+
179
+
static const struct ccu_reset_controller_data k1_rcpu_reset_data = {
180
+
.reset_data = k1_rcpu_resets,
181
+
.count = ARRAY_SIZE(k1_rcpu_resets),
182
+
};
183
+
184
+
static const struct ccu_reset_data k1_rcpu2_resets[] = {
185
+
[RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
186
+
[RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
187
+
[RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
188
+
[RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
189
+
[RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
190
+
[RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
191
+
[RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
192
+
[RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
193
+
[RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
194
+
[RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
195
+
};
196
+
197
+
static const struct ccu_reset_controller_data k1_rcpu2_reset_data = {
198
+
.reset_data = k1_rcpu2_resets,
199
+
.count = ARRAY_SIZE(k1_rcpu2_resets),
200
+
};
201
+
202
+
static const struct ccu_reset_data k1_apbc2_resets[] = {
203
+
[RESET_APBC2_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0),
204
+
[RESET_APBC2_SSP2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0),
205
+
[RESET_APBC2_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0),
206
+
[RESET_APBC2_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0),
207
+
[RESET_APBC2_TIMERS0] = RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0),
208
+
[RESET_APBC2_KPC] = RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0),
209
+
[RESET_APBC2_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0),
210
+
};
211
+
212
+
static const struct ccu_reset_controller_data k1_apbc2_reset_data = {
213
+
.reset_data = k1_apbc2_resets,
214
+
.count = ARRAY_SIZE(k1_apbc2_resets),
215
+
};
216
+
217
+
static int spacemit_reset_update(struct reset_controller_dev *rcdev,
218
+
unsigned long id, bool assert)
219
+
{
220
+
struct ccu_reset_controller *controller;
221
+
const struct ccu_reset_data *data;
222
+
u32 mask;
223
+
u32 val;
224
+
225
+
controller = container_of(rcdev, struct ccu_reset_controller, rcdev);
226
+
data = &controller->data->reset_data[id];
227
+
mask = data->assert_mask | data->deassert_mask;
228
+
val = assert ? data->assert_mask : data->deassert_mask;
229
+
230
+
return regmap_update_bits(controller->regmap, data->offset, mask, val);
231
+
}
232
+
233
+
static int spacemit_reset_assert(struct reset_controller_dev *rcdev,
234
+
unsigned long id)
235
+
{
236
+
return spacemit_reset_update(rcdev, id, true);
237
+
}
238
+
239
+
static int spacemit_reset_deassert(struct reset_controller_dev *rcdev,
240
+
unsigned long id)
241
+
{
242
+
return spacemit_reset_update(rcdev, id, false);
243
+
}
244
+
245
+
static const struct reset_control_ops spacemit_reset_control_ops = {
246
+
.assert = spacemit_reset_assert,
247
+
.deassert = spacemit_reset_deassert,
248
+
};
249
+
250
+
static int spacemit_reset_controller_register(struct device *dev,
251
+
struct ccu_reset_controller *controller)
252
+
{
253
+
struct reset_controller_dev *rcdev = &controller->rcdev;
254
+
255
+
rcdev->ops = &spacemit_reset_control_ops;
256
+
rcdev->owner = THIS_MODULE;
257
+
rcdev->of_node = dev->of_node;
258
+
rcdev->nr_resets = controller->data->count;
259
+
260
+
return devm_reset_controller_register(dev, &controller->rcdev);
261
+
}
262
+
263
+
static int spacemit_reset_probe(struct auxiliary_device *adev,
264
+
const struct auxiliary_device_id *id)
265
+
{
266
+
struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev);
267
+
struct ccu_reset_controller *controller;
268
+
struct device *dev = &adev->dev;
269
+
270
+
controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
271
+
if (!controller)
272
+
return -ENOMEM;
273
+
controller->data = (const struct ccu_reset_controller_data *)id->driver_data;
274
+
controller->regmap = rdev->regmap;
275
+
276
+
return spacemit_reset_controller_register(dev, controller);
277
+
}
278
+
279
+
#define K1_AUX_DEV_ID(_unit) \
280
+
{ \
281
+
.name = "spacemit_ccu_k1." #_unit "-reset", \
282
+
.driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \
283
+
}
284
+
285
+
static const struct auxiliary_device_id spacemit_reset_ids[] = {
286
+
K1_AUX_DEV_ID(mpmu),
287
+
K1_AUX_DEV_ID(apbc),
288
+
K1_AUX_DEV_ID(apmu),
289
+
K1_AUX_DEV_ID(rcpu),
290
+
K1_AUX_DEV_ID(rcpu2),
291
+
K1_AUX_DEV_ID(apbc2),
292
+
{ },
293
+
};
294
+
MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids);
295
+
296
+
static struct auxiliary_driver spacemit_k1_reset_driver = {
297
+
.probe = spacemit_reset_probe,
298
+
.id_table = spacemit_reset_ids,
299
+
};
300
+
module_auxiliary_driver(spacemit_k1_reset_driver);
301
+
302
+
MODULE_AUTHOR("Alex Elder <elder@kernel.org>");
303
+
MODULE_DESCRIPTION("SpacemiT reset controller driver");
304
+
MODULE_LICENSE("GPL");
-53
include/dt-bindings/clock/r9a07g043-cpg.h
-53
include/dt-bindings/clock/r9a07g043-cpg.h
···
200
200
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
201
201
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
202
202
203
-
/* Power domain IDs. */
204
-
#define R9A07G043_PD_ALWAYS_ON 0
205
-
#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
206
-
#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
207
-
#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
208
-
#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
209
-
#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
210
-
#define R9A07G043_PD_DMAC 6
211
-
#define R9A07G043_PD_GTM0 7
212
-
#define R9A07G043_PD_GTM1 8
213
-
#define R9A07G043_PD_GTM2 9
214
-
#define R9A07G043_PD_MTU 10
215
-
#define R9A07G043_PD_POE3 11
216
-
#define R9A07G043_PD_WDT0 12
217
-
#define R9A07G043_PD_SPI 13
218
-
#define R9A07G043_PD_SDHI0 14
219
-
#define R9A07G043_PD_SDHI1 15
220
-
#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
221
-
#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
222
-
#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
223
-
#define R9A07G043_PD_SSI0 19
224
-
#define R9A07G043_PD_SSI1 20
225
-
#define R9A07G043_PD_SSI2 21
226
-
#define R9A07G043_PD_SSI3 22
227
-
#define R9A07G043_PD_SRC 23
228
-
#define R9A07G043_PD_USB0 24
229
-
#define R9A07G043_PD_USB1 25
230
-
#define R9A07G043_PD_USB_PHY 26
231
-
#define R9A07G043_PD_ETHER0 27
232
-
#define R9A07G043_PD_ETHER1 28
233
-
#define R9A07G043_PD_I2C0 29
234
-
#define R9A07G043_PD_I2C1 30
235
-
#define R9A07G043_PD_I2C2 31
236
-
#define R9A07G043_PD_I2C3 32
237
-
#define R9A07G043_PD_SCIF0 33
238
-
#define R9A07G043_PD_SCIF1 34
239
-
#define R9A07G043_PD_SCIF2 35
240
-
#define R9A07G043_PD_SCIF3 36
241
-
#define R9A07G043_PD_SCIF4 37
242
-
#define R9A07G043_PD_SCI0 38
243
-
#define R9A07G043_PD_SCI1 39
244
-
#define R9A07G043_PD_IRDA 40
245
-
#define R9A07G043_PD_RSPI0 41
246
-
#define R9A07G043_PD_RSPI1 42
247
-
#define R9A07G043_PD_RSPI2 43
248
-
#define R9A07G043_PD_CANFD 44
249
-
#define R9A07G043_PD_ADC 45
250
-
#define R9A07G043_PD_TSU 46
251
-
#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
252
-
#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
253
-
#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
254
-
#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
255
-
256
203
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
-58
include/dt-bindings/clock/r9a07g044-cpg.h
-58
include/dt-bindings/clock/r9a07g044-cpg.h
···
217
217
#define R9A07G044_ADC_ADRST_N 82
218
218
#define R9A07G044_TSU_PRESETN 83
219
219
220
-
/* Power domain IDs. */
221
-
#define R9A07G044_PD_ALWAYS_ON 0
222
-
#define R9A07G044_PD_GIC 1
223
-
#define R9A07G044_PD_IA55 2
224
-
#define R9A07G044_PD_MHU 3
225
-
#define R9A07G044_PD_CORESIGHT 4
226
-
#define R9A07G044_PD_SYC 5
227
-
#define R9A07G044_PD_DMAC 6
228
-
#define R9A07G044_PD_GTM0 7
229
-
#define R9A07G044_PD_GTM1 8
230
-
#define R9A07G044_PD_GTM2 9
231
-
#define R9A07G044_PD_MTU 10
232
-
#define R9A07G044_PD_POE3 11
233
-
#define R9A07G044_PD_GPT 12
234
-
#define R9A07G044_PD_POEGA 13
235
-
#define R9A07G044_PD_POEGB 14
236
-
#define R9A07G044_PD_POEGC 15
237
-
#define R9A07G044_PD_POEGD 16
238
-
#define R9A07G044_PD_WDT0 17
239
-
#define R9A07G044_PD_WDT1 18
240
-
#define R9A07G044_PD_SPI 19
241
-
#define R9A07G044_PD_SDHI0 20
242
-
#define R9A07G044_PD_SDHI1 21
243
-
#define R9A07G044_PD_3DGE 22
244
-
#define R9A07G044_PD_ISU 23
245
-
#define R9A07G044_PD_VCPL4 24
246
-
#define R9A07G044_PD_CRU 25
247
-
#define R9A07G044_PD_MIPI_DSI 26
248
-
#define R9A07G044_PD_LCDC 27
249
-
#define R9A07G044_PD_SSI0 28
250
-
#define R9A07G044_PD_SSI1 29
251
-
#define R9A07G044_PD_SSI2 30
252
-
#define R9A07G044_PD_SSI3 31
253
-
#define R9A07G044_PD_SRC 32
254
-
#define R9A07G044_PD_USB0 33
255
-
#define R9A07G044_PD_USB1 34
256
-
#define R9A07G044_PD_USB_PHY 35
257
-
#define R9A07G044_PD_ETHER0 36
258
-
#define R9A07G044_PD_ETHER1 37
259
-
#define R9A07G044_PD_I2C0 38
260
-
#define R9A07G044_PD_I2C1 39
261
-
#define R9A07G044_PD_I2C2 40
262
-
#define R9A07G044_PD_I2C3 41
263
-
#define R9A07G044_PD_SCIF0 42
264
-
#define R9A07G044_PD_SCIF1 43
265
-
#define R9A07G044_PD_SCIF2 44
266
-
#define R9A07G044_PD_SCIF3 45
267
-
#define R9A07G044_PD_SCIF4 46
268
-
#define R9A07G044_PD_SCI0 47
269
-
#define R9A07G044_PD_SCI1 48
270
-
#define R9A07G044_PD_IRDA 49
271
-
#define R9A07G044_PD_RSPI0 50
272
-
#define R9A07G044_PD_RSPI1 51
273
-
#define R9A07G044_PD_RSPI2 52
274
-
#define R9A07G044_PD_CANFD 53
275
-
#define R9A07G044_PD_ADC 54
276
-
#define R9A07G044_PD_TSU 55
277
-
278
220
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
-58
include/dt-bindings/clock/r9a07g054-cpg.h
-58
include/dt-bindings/clock/r9a07g054-cpg.h
···
226
226
#define R9A07G054_TSU_PRESETN 83
227
227
#define R9A07G054_STPAI_ARESETN 84
228
228
229
-
/* Power domain IDs. */
230
-
#define R9A07G054_PD_ALWAYS_ON 0
231
-
#define R9A07G054_PD_GIC 1
232
-
#define R9A07G054_PD_IA55 2
233
-
#define R9A07G054_PD_MHU 3
234
-
#define R9A07G054_PD_CORESIGHT 4
235
-
#define R9A07G054_PD_SYC 5
236
-
#define R9A07G054_PD_DMAC 6
237
-
#define R9A07G054_PD_GTM0 7
238
-
#define R9A07G054_PD_GTM1 8
239
-
#define R9A07G054_PD_GTM2 9
240
-
#define R9A07G054_PD_MTU 10
241
-
#define R9A07G054_PD_POE3 11
242
-
#define R9A07G054_PD_GPT 12
243
-
#define R9A07G054_PD_POEGA 13
244
-
#define R9A07G054_PD_POEGB 14
245
-
#define R9A07G054_PD_POEGC 15
246
-
#define R9A07G054_PD_POEGD 16
247
-
#define R9A07G054_PD_WDT0 17
248
-
#define R9A07G054_PD_WDT1 18
249
-
#define R9A07G054_PD_SPI 19
250
-
#define R9A07G054_PD_SDHI0 20
251
-
#define R9A07G054_PD_SDHI1 21
252
-
#define R9A07G054_PD_3DGE 22
253
-
#define R9A07G054_PD_ISU 23
254
-
#define R9A07G054_PD_VCPL4 24
255
-
#define R9A07G054_PD_CRU 25
256
-
#define R9A07G054_PD_MIPI_DSI 26
257
-
#define R9A07G054_PD_LCDC 27
258
-
#define R9A07G054_PD_SSI0 28
259
-
#define R9A07G054_PD_SSI1 29
260
-
#define R9A07G054_PD_SSI2 30
261
-
#define R9A07G054_PD_SSI3 31
262
-
#define R9A07G054_PD_SRC 32
263
-
#define R9A07G054_PD_USB0 33
264
-
#define R9A07G054_PD_USB1 34
265
-
#define R9A07G054_PD_USB_PHY 35
266
-
#define R9A07G054_PD_ETHER0 36
267
-
#define R9A07G054_PD_ETHER1 37
268
-
#define R9A07G054_PD_I2C0 38
269
-
#define R9A07G054_PD_I2C1 39
270
-
#define R9A07G054_PD_I2C2 40
271
-
#define R9A07G054_PD_I2C3 41
272
-
#define R9A07G054_PD_SCIF0 42
273
-
#define R9A07G054_PD_SCIF1 43
274
-
#define R9A07G054_PD_SCIF2 44
275
-
#define R9A07G054_PD_SCIF3 45
276
-
#define R9A07G054_PD_SCIF4 46
277
-
#define R9A07G054_PD_SCI0 47
278
-
#define R9A07G054_PD_SCI1 48
279
-
#define R9A07G054_PD_IRDA 49
280
-
#define R9A07G054_PD_RSPI0 50
281
-
#define R9A07G054_PD_RSPI1 51
282
-
#define R9A07G054_PD_RSPI2 52
283
-
#define R9A07G054_PD_CANFD 53
284
-
#define R9A07G054_PD_ADC 54
285
-
#define R9A07G054_PD_TSU 55
286
-
287
229
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
-71
include/dt-bindings/clock/r9a08g045-cpg.h
-71
include/dt-bindings/clock/r9a08g045-cpg.h
···
239
239
#define R9A08G045_I3C_PRESETN 92
240
240
#define R9A08G045_VBAT_BRESETN 93
241
241
242
-
/* Power domain IDs. */
243
-
#define R9A08G045_PD_ALWAYS_ON 0
244
-
#define R9A08G045_PD_GIC 1
245
-
#define R9A08G045_PD_IA55 2
246
-
#define R9A08G045_PD_MHU 3
247
-
#define R9A08G045_PD_CORESIGHT 4
248
-
#define R9A08G045_PD_SYC 5
249
-
#define R9A08G045_PD_DMAC 6
250
-
#define R9A08G045_PD_GTM0 7
251
-
#define R9A08G045_PD_GTM1 8
252
-
#define R9A08G045_PD_GTM2 9
253
-
#define R9A08G045_PD_GTM3 10
254
-
#define R9A08G045_PD_GTM4 11
255
-
#define R9A08G045_PD_GTM5 12
256
-
#define R9A08G045_PD_GTM6 13
257
-
#define R9A08G045_PD_GTM7 14
258
-
#define R9A08G045_PD_MTU 15
259
-
#define R9A08G045_PD_POE3 16
260
-
#define R9A08G045_PD_GPT 17
261
-
#define R9A08G045_PD_POEGA 18
262
-
#define R9A08G045_PD_POEGB 19
263
-
#define R9A08G045_PD_POEGC 20
264
-
#define R9A08G045_PD_POEGD 21
265
-
#define R9A08G045_PD_WDT0 22
266
-
#define R9A08G045_PD_XSPI 23
267
-
#define R9A08G045_PD_SDHI0 24
268
-
#define R9A08G045_PD_SDHI1 25
269
-
#define R9A08G045_PD_SDHI2 26
270
-
#define R9A08G045_PD_SSI0 27
271
-
#define R9A08G045_PD_SSI1 28
272
-
#define R9A08G045_PD_SSI2 29
273
-
#define R9A08G045_PD_SSI3 30
274
-
#define R9A08G045_PD_SRC 31
275
-
#define R9A08G045_PD_USB0 32
276
-
#define R9A08G045_PD_USB1 33
277
-
#define R9A08G045_PD_USB_PHY 34
278
-
#define R9A08G045_PD_ETHER0 35
279
-
#define R9A08G045_PD_ETHER1 36
280
-
#define R9A08G045_PD_I2C0 37
281
-
#define R9A08G045_PD_I2C1 38
282
-
#define R9A08G045_PD_I2C2 39
283
-
#define R9A08G045_PD_I2C3 40
284
-
#define R9A08G045_PD_SCIF0 41
285
-
#define R9A08G045_PD_SCIF1 42
286
-
#define R9A08G045_PD_SCIF2 43
287
-
#define R9A08G045_PD_SCIF3 44
288
-
#define R9A08G045_PD_SCIF4 45
289
-
#define R9A08G045_PD_SCIF5 46
290
-
#define R9A08G045_PD_SCI0 47
291
-
#define R9A08G045_PD_SCI1 48
292
-
#define R9A08G045_PD_IRDA 49
293
-
#define R9A08G045_PD_RSPI0 50
294
-
#define R9A08G045_PD_RSPI1 51
295
-
#define R9A08G045_PD_RSPI2 52
296
-
#define R9A08G045_PD_RSPI3 53
297
-
#define R9A08G045_PD_RSPI4 54
298
-
#define R9A08G045_PD_CANFD 55
299
-
#define R9A08G045_PD_ADC 56
300
-
#define R9A08G045_PD_TSU 57
301
-
#define R9A08G045_PD_OCTA 58
302
-
#define R9A08G045_PD_PDM 59
303
-
#define R9A08G045_PD_PCI 60
304
-
#define R9A08G045_PD_SPDIF 61
305
-
#define R9A08G045_PD_I3C 62
306
-
#define R9A08G045_PD_VBAT 63
307
-
308
-
#define R9A08G045_PD_DDR 64
309
-
#define R9A08G045_PD_TZCDDR 65
310
-
#define R9A08G045_PD_OTFDE_DDR 66
311
-
#define R9A08G045_PD_RTC 67
312
-
313
242
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
+1
include/dt-bindings/clock/renesas,r9a09g056-cpg.h
+1
include/dt-bindings/clock/renesas,r9a09g056-cpg.h
+1
include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+1
include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+29
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+29
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
*
3
+
* Copyright (C) 2025 Renesas Electronics Corp.
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
7
+
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
8
+
9
+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
10
+
11
+
/* R9A09G077 CPG Core Clocks */
12
+
#define R9A09G077_CLK_CA55C0 0
13
+
#define R9A09G077_CLK_CA55C1 1
14
+
#define R9A09G077_CLK_CA55C2 2
15
+
#define R9A09G077_CLK_CA55C3 3
16
+
#define R9A09G077_CLK_CA55S 4
17
+
#define R9A09G077_CLK_CR52_CPU0 5
18
+
#define R9A09G077_CLK_CR52_CPU1 6
19
+
#define R9A09G077_CLK_CKIO 7
20
+
#define R9A09G077_CLK_PCLKAH 8
21
+
#define R9A09G077_CLK_PCLKAM 9
22
+
#define R9A09G077_CLK_PCLKAL 10
23
+
#define R9A09G077_CLK_PCLKGPTL 11
24
+
#define R9A09G077_CLK_PCLKH 12
25
+
#define R9A09G077_CLK_PCLKM 13
26
+
#define R9A09G077_CLK_PCLKL 14
27
+
#define R9A09G077_SDHI_CLKHS 15
28
+
29
+
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
+29
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+29
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
*
3
+
* Copyright (C) 2025 Renesas Electronics Corp.
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
7
+
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
8
+
9
+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
10
+
11
+
/* R9A09G087 CPG Core Clocks */
12
+
#define R9A09G087_CLK_CA55C0 0
13
+
#define R9A09G087_CLK_CA55C1 1
14
+
#define R9A09G087_CLK_CA55C2 2
15
+
#define R9A09G087_CLK_CA55C3 3
16
+
#define R9A09G087_CLK_CA55S 4
17
+
#define R9A09G087_CLK_CR52_CPU0 5
18
+
#define R9A09G087_CLK_CR52_CPU1 6
19
+
#define R9A09G087_CLK_CKIO 7
20
+
#define R9A09G087_CLK_PCLKAH 8
21
+
#define R9A09G087_CLK_PCLKAM 9
22
+
#define R9A09G087_CLK_PCLKAL 10
23
+
#define R9A09G087_CLK_PCLKGPTL 11
24
+
#define R9A09G087_CLK_PCLKH 12
25
+
#define R9A09G087_CLK_PCLKM 13
26
+
#define R9A09G087_CLK_PCLKL 14
27
+
#define R9A09G087_SDHI_CLKHS 15
28
+
29
+
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
+9
include/dt-bindings/clock/samsung,exynosautov920.h
+9
include/dt-bindings/clock/samsung,exynosautov920.h
···
286
286
#define CLK_MOUT_HSI1_USBDRD_USER 3
287
287
#define CLK_MOUT_HSI1_USBDRD 4
288
288
289
+
/* CMU_HSI2 */
290
+
#define FOUT_PLL_ETH 1
291
+
#define CLK_MOUT_HSI2_NOC_UFS_USER 2
292
+
#define CLK_MOUT_HSI2_UFS_EMBD_USER 3
293
+
#define CLK_MOUT_HSI2_ETHERNET 4
294
+
#define CLK_MOUT_HSI2_ETHERNET_USER 5
295
+
#define CLK_DOUT_HSI2_ETHERNET 6
296
+
#define CLK_DOUT_HSI2_ETHERNET_PTP 7
297
+
289
298
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
+141
include/dt-bindings/clock/spacemit,k1-syscon.h
+141
include/dt-bindings/clock/spacemit,k1-syscon.h
···
78
78
#define CLK_APB 31
79
79
#define CLK_WDT_BUS 32
80
80
81
+
/* MPMU resets */
82
+
#define RESET_WDT 0
83
+
81
84
/* APBC clocks */
82
85
#define CLK_UART0 0
83
86
#define CLK_UART2 1
···
183
180
#define CLK_TSEN_BUS 98
184
181
#define CLK_IPC_AP2AUD_BUS 99
185
182
183
+
/* APBC resets */
184
+
#define RESET_UART0 0
185
+
#define RESET_UART2 1
186
+
#define RESET_UART3 2
187
+
#define RESET_UART4 3
188
+
#define RESET_UART5 4
189
+
#define RESET_UART6 5
190
+
#define RESET_UART7 6
191
+
#define RESET_UART8 7
192
+
#define RESET_UART9 8
193
+
#define RESET_GPIO 9
194
+
#define RESET_PWM0 10
195
+
#define RESET_PWM1 11
196
+
#define RESET_PWM2 12
197
+
#define RESET_PWM3 13
198
+
#define RESET_PWM4 14
199
+
#define RESET_PWM5 15
200
+
#define RESET_PWM6 16
201
+
#define RESET_PWM7 17
202
+
#define RESET_PWM8 18
203
+
#define RESET_PWM9 19
204
+
#define RESET_PWM10 20
205
+
#define RESET_PWM11 21
206
+
#define RESET_PWM12 22
207
+
#define RESET_PWM13 23
208
+
#define RESET_PWM14 24
209
+
#define RESET_PWM15 25
210
+
#define RESET_PWM16 26
211
+
#define RESET_PWM17 27
212
+
#define RESET_PWM18 28
213
+
#define RESET_PWM19 29
214
+
#define RESET_SSP3 30
215
+
#define RESET_RTC 31
216
+
#define RESET_TWSI0 32
217
+
#define RESET_TWSI1 33
218
+
#define RESET_TWSI2 34
219
+
#define RESET_TWSI4 35
220
+
#define RESET_TWSI5 36
221
+
#define RESET_TWSI6 37
222
+
#define RESET_TWSI7 38
223
+
#define RESET_TWSI8 39
224
+
#define RESET_TIMERS1 40
225
+
#define RESET_TIMERS2 41
226
+
#define RESET_AIB 42
227
+
#define RESET_ONEWIRE 43
228
+
#define RESET_SSPA0 44
229
+
#define RESET_SSPA1 45
230
+
#define RESET_DRO 46
231
+
#define RESET_IR 47
232
+
#define RESET_TSEN 48
233
+
#define RESET_IPC_AP2AUD 49
234
+
#define RESET_CAN0 50
235
+
186
236
/* APMU clocks */
187
237
#define CLK_CCI550 0
188
238
#define CLK_CPU_C0_HI 1
···
299
243
#define CLK_DPU_SPI_ACLK 59
300
244
#define CLK_V2D 60
301
245
#define CLK_EMMC_BUS 61
246
+
247
+
/* APMU resets */
248
+
#define RESET_CCIC_4X 0
249
+
#define RESET_CCIC1_PHY 1
250
+
#define RESET_SDH_AXI 2
251
+
#define RESET_SDH0 3
252
+
#define RESET_SDH1 4
253
+
#define RESET_SDH2 5
254
+
#define RESET_USBP1_AXI 6
255
+
#define RESET_USB_AXI 7
256
+
#define RESET_USB30_AHB 8
257
+
#define RESET_USB30_VCC 9
258
+
#define RESET_USB30_PHY 10
259
+
#define RESET_QSPI 11
260
+
#define RESET_QSPI_BUS 12
261
+
#define RESET_DMA 13
262
+
#define RESET_AES 14
263
+
#define RESET_VPU 15
264
+
#define RESET_GPU 16
265
+
#define RESET_EMMC 17
266
+
#define RESET_EMMC_X 18
267
+
#define RESET_AUDIO_SYS 19
268
+
#define RESET_AUDIO_MCU 20
269
+
#define RESET_AUDIO_APMU 21
270
+
#define RESET_HDMI 22
271
+
#define RESET_PCIE0_MASTER 23
272
+
#define RESET_PCIE0_SLAVE 24
273
+
#define RESET_PCIE0_DBI 25
274
+
#define RESET_PCIE0_GLOBAL 26
275
+
#define RESET_PCIE1_MASTER 27
276
+
#define RESET_PCIE1_SLAVE 28
277
+
#define RESET_PCIE1_DBI 29
278
+
#define RESET_PCIE1_GLOBAL 30
279
+
#define RESET_PCIE2_MASTER 31
280
+
#define RESET_PCIE2_SLAVE 32
281
+
#define RESET_PCIE2_DBI 33
282
+
#define RESET_PCIE2_GLOBAL 34
283
+
#define RESET_EMAC0 35
284
+
#define RESET_EMAC1 36
285
+
#define RESET_JPG 37
286
+
#define RESET_CCIC2PHY 38
287
+
#define RESET_CCIC3PHY 39
288
+
#define RESET_CSI 40
289
+
#define RESET_ISP_CPP 41
290
+
#define RESET_ISP_BUS 42
291
+
#define RESET_ISP 43
292
+
#define RESET_ISP_CI 44
293
+
#define RESET_DPU_MCLK 45
294
+
#define RESET_DPU_ESC 46
295
+
#define RESET_DPU_HCLK 47
296
+
#define RESET_DPU_SPIBUS 48
297
+
#define RESET_DPU_SPI_HBUS 49
298
+
#define RESET_V2D 50
299
+
#define RESET_MIPI 51
300
+
#define RESET_MC 52
301
+
302
+
/* RCPU resets */
303
+
#define RESET_RCPU_SSP0 0
304
+
#define RESET_RCPU_I2C0 1
305
+
#define RESET_RCPU_UART1 2
306
+
#define RESET_RCPU_IR 3
307
+
#define RESET_RCPU_CAN 4
308
+
#define RESET_RCPU_UART0 5
309
+
#define RESET_RCPU_HDMI_AUDIO 6
310
+
311
+
/* RCPU2 resets */
312
+
#define RESET_RCPU2_PWM0 0
313
+
#define RESET_RCPU2_PWM1 1
314
+
#define RESET_RCPU2_PWM2 2
315
+
#define RESET_RCPU2_PWM3 3
316
+
#define RESET_RCPU2_PWM4 4
317
+
#define RESET_RCPU2_PWM5 5
318
+
#define RESET_RCPU2_PWM6 6
319
+
#define RESET_RCPU2_PWM7 7
320
+
#define RESET_RCPU2_PWM8 8
321
+
#define RESET_RCPU2_PWM9 9
322
+
323
+
/* APBC2 resets */
324
+
#define RESET_APBC2_UART1 0
325
+
#define RESET_APBC2_SSP2 1
326
+
#define RESET_APBC2_TWSI3 2
327
+
#define RESET_APBC2_RTC 3
328
+
#define RESET_APBC2_TIMERS0 4
329
+
#define RESET_APBC2_KPC 5
330
+
#define RESET_APBC2_GPIO 6
302
331
303
332
#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */
+1
include/dt-bindings/reset/sun55i-a523-r-ccu.h
+1
include/dt-bindings/reset/sun55i-a523-r-ccu.h
+160
include/soc/spacemit/k1-syscon.h
+160
include/soc/spacemit/k1-syscon.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
3
+
/* SpacemiT clock and reset driver definitions for the K1 SoC */
4
+
5
+
#ifndef __SOC_K1_SYSCON_H__
6
+
#define __SOC_K1_SYSCON_H__
7
+
8
+
/* Auxiliary device used to represent a CCU reset controller */
9
+
struct spacemit_ccu_adev {
10
+
struct auxiliary_device adev;
11
+
struct regmap *regmap;
12
+
};
13
+
14
+
static inline struct spacemit_ccu_adev *
15
+
to_spacemit_ccu_adev(struct auxiliary_device *adev)
16
+
{
17
+
return container_of(adev, struct spacemit_ccu_adev, adev);
18
+
}
19
+
20
+
/* APBS register offset */
21
+
#define APBS_PLL1_SWCR1 0x100
22
+
#define APBS_PLL1_SWCR2 0x104
23
+
#define APBS_PLL1_SWCR3 0x108
24
+
#define APBS_PLL2_SWCR1 0x118
25
+
#define APBS_PLL2_SWCR2 0x11c
26
+
#define APBS_PLL2_SWCR3 0x120
27
+
#define APBS_PLL3_SWCR1 0x124
28
+
#define APBS_PLL3_SWCR2 0x128
29
+
#define APBS_PLL3_SWCR3 0x12c
30
+
31
+
/* MPMU register offset */
32
+
#define MPMU_POSR 0x0010
33
+
#define POSR_PLL1_LOCK BIT(27)
34
+
#define POSR_PLL2_LOCK BIT(28)
35
+
#define POSR_PLL3_LOCK BIT(29)
36
+
#define MPMU_SUCCR 0x0014
37
+
#define MPMU_ISCCR 0x0044
38
+
#define MPMU_WDTPCR 0x0200
39
+
#define MPMU_RIPCCR 0x0210
40
+
#define MPMU_ACGR 0x1024
41
+
#define MPMU_APBCSCR 0x1050
42
+
#define MPMU_SUCCR_1 0x10b0
43
+
44
+
/* APBC register offset */
45
+
#define APBC_UART1_CLK_RST 0x00
46
+
#define APBC_UART2_CLK_RST 0x04
47
+
#define APBC_GPIO_CLK_RST 0x08
48
+
#define APBC_PWM0_CLK_RST 0x0c
49
+
#define APBC_PWM1_CLK_RST 0x10
50
+
#define APBC_PWM2_CLK_RST 0x14
51
+
#define APBC_PWM3_CLK_RST 0x18
52
+
#define APBC_TWSI8_CLK_RST 0x20
53
+
#define APBC_UART3_CLK_RST 0x24
54
+
#define APBC_RTC_CLK_RST 0x28
55
+
#define APBC_TWSI0_CLK_RST 0x2c
56
+
#define APBC_TWSI1_CLK_RST 0x30
57
+
#define APBC_TIMERS1_CLK_RST 0x34
58
+
#define APBC_TWSI2_CLK_RST 0x38
59
+
#define APBC_AIB_CLK_RST 0x3c
60
+
#define APBC_TWSI4_CLK_RST 0x40
61
+
#define APBC_TIMERS2_CLK_RST 0x44
62
+
#define APBC_ONEWIRE_CLK_RST 0x48
63
+
#define APBC_TWSI5_CLK_RST 0x4c
64
+
#define APBC_DRO_CLK_RST 0x58
65
+
#define APBC_IR_CLK_RST 0x5c
66
+
#define APBC_TWSI6_CLK_RST 0x60
67
+
#define APBC_COUNTER_CLK_SEL 0x64
68
+
#define APBC_TWSI7_CLK_RST 0x68
69
+
#define APBC_TSEN_CLK_RST 0x6c
70
+
#define APBC_UART4_CLK_RST 0x70
71
+
#define APBC_UART5_CLK_RST 0x74
72
+
#define APBC_UART6_CLK_RST 0x78
73
+
#define APBC_SSP3_CLK_RST 0x7c
74
+
#define APBC_SSPA0_CLK_RST 0x80
75
+
#define APBC_SSPA1_CLK_RST 0x84
76
+
#define APBC_IPC_AP2AUD_CLK_RST 0x90
77
+
#define APBC_UART7_CLK_RST 0x94
78
+
#define APBC_UART8_CLK_RST 0x98
79
+
#define APBC_UART9_CLK_RST 0x9c
80
+
#define APBC_CAN0_CLK_RST 0xa0
81
+
#define APBC_PWM4_CLK_RST 0xa8
82
+
#define APBC_PWM5_CLK_RST 0xac
83
+
#define APBC_PWM6_CLK_RST 0xb0
84
+
#define APBC_PWM7_CLK_RST 0xb4
85
+
#define APBC_PWM8_CLK_RST 0xb8
86
+
#define APBC_PWM9_CLK_RST 0xbc
87
+
#define APBC_PWM10_CLK_RST 0xc0
88
+
#define APBC_PWM11_CLK_RST 0xc4
89
+
#define APBC_PWM12_CLK_RST 0xc8
90
+
#define APBC_PWM13_CLK_RST 0xcc
91
+
#define APBC_PWM14_CLK_RST 0xd0
92
+
#define APBC_PWM15_CLK_RST 0xd4
93
+
#define APBC_PWM16_CLK_RST 0xd8
94
+
#define APBC_PWM17_CLK_RST 0xdc
95
+
#define APBC_PWM18_CLK_RST 0xe0
96
+
#define APBC_PWM19_CLK_RST 0xe4
97
+
98
+
/* APMU register offset */
99
+
#define APMU_JPG_CLK_RES_CTRL 0x020
100
+
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
101
+
#define APMU_ISP_CLK_RES_CTRL 0x038
102
+
#define APMU_LCD_CLK_RES_CTRL1 0x044
103
+
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
104
+
#define APMU_LCD_CLK_RES_CTRL2 0x04c
105
+
#define APMU_CCIC_CLK_RES_CTRL 0x050
106
+
#define APMU_SDH0_CLK_RES_CTRL 0x054
107
+
#define APMU_SDH1_CLK_RES_CTRL 0x058
108
+
#define APMU_USB_CLK_RES_CTRL 0x05c
109
+
#define APMU_QSPI_CLK_RES_CTRL 0x060
110
+
#define APMU_DMA_CLK_RES_CTRL 0x064
111
+
#define APMU_AES_CLK_RES_CTRL 0x068
112
+
#define APMU_VPU_CLK_RES_CTRL 0x0a4
113
+
#define APMU_GPU_CLK_RES_CTRL 0x0cc
114
+
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
115
+
#define APMU_PMUA_MC_CTRL 0x0e8
116
+
#define APMU_PMU_CC2_AP 0x100
117
+
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
118
+
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
119
+
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
120
+
#define APMU_CCI550_CLK_CTRL 0x300
121
+
#define APMU_ACLK_CLK_CTRL 0x388
122
+
#define APMU_CPU_C0_CLK_CTRL 0x38C
123
+
#define APMU_CPU_C1_CLK_CTRL 0x390
124
+
#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
125
+
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
126
+
#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
127
+
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
128
+
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
129
+
130
+
/* RCPU register offsets */
131
+
#define RCPU_SSP0_CLK_RST 0x0028
132
+
#define RCPU_I2C0_CLK_RST 0x0030
133
+
#define RCPU_UART1_CLK_RST 0x003c
134
+
#define RCPU_CAN_CLK_RST 0x0048
135
+
#define RCPU_IR_CLK_RST 0x004c
136
+
#define RCPU_UART0_CLK_RST 0x00d8
137
+
#define AUDIO_HDMI_CLK_CTRL 0x2044
138
+
139
+
/* RCPU2 register offsets */
140
+
#define RCPU2_PWM0_CLK_RST 0x0000
141
+
#define RCPU2_PWM1_CLK_RST 0x0004
142
+
#define RCPU2_PWM2_CLK_RST 0x0008
143
+
#define RCPU2_PWM3_CLK_RST 0x000c
144
+
#define RCPU2_PWM4_CLK_RST 0x0010
145
+
#define RCPU2_PWM5_CLK_RST 0x0014
146
+
#define RCPU2_PWM6_CLK_RST 0x0018
147
+
#define RCPU2_PWM7_CLK_RST 0x001c
148
+
#define RCPU2_PWM8_CLK_RST 0x0020
149
+
#define RCPU2_PWM9_CLK_RST 0x0024
150
+
151
+
/* APBC2 register offsets */
152
+
#define APBC2_UART1_CLK_RST 0x0000
153
+
#define APBC2_SSP2_CLK_RST 0x0004
154
+
#define APBC2_TWSI3_CLK_RST 0x0008
155
+
#define APBC2_RTC_CLK_RST 0x000c
156
+
#define APBC2_TIMERS0_CLK_RST 0x0010
157
+
#define APBC2_KPC_CLK_RST 0x0014
158
+
#define APBC2_GPIO_CLK_RST 0x001c
159
+
160
+
#endif /* __SOC_K1_SYSCON_H__ */