Merge remote-tracking branches 'asoc/topic/rt5641', 'asoc/topic/rt5677' and 'asoc/topic/sh-cleanup' into asoc-next

+1 -2

arch/arm/mach-shmobile/board-armadillo800eva.c

··· 1015 1015 .platform = "sh_fsi2", 1016 1016 .daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, 1017 1017 .cpu_dai = { 1018 - .fmt = SND_SOC_DAIFMT_IB_NF, 1019 1018 .name = "fsia-dai", 1020 1019 }, 1021 1020 .codec_dai = { ··· 1039 1040 .card = "FSI2B-HDMI", 1040 1041 .codec = "sh-mobile-hdmi", 1041 1042 .platform = "sh_fsi2", 1043 + .daifmt = SND_SOC_DAIFMT_CBS_CFS, 1042 1044 .cpu_dai = { 1043 1045 .name = "fsib-dai", 1044 - .fmt = SND_SOC_DAIFMT_CBS_CFS, 1045 1046 }, 1046 1047 .codec_dai = { 1047 1048 .name = "sh_mobile_hdmi-hifi",

-1

include/sound/simple_card.h

··· 16 16 17 17 struct asoc_simple_dai { 18 18 const char *name; 19 - unsigned int fmt; 20 19 unsigned int sysclk; 21 20 int slots; 22 21 int slot_width;

+1 -1

sound/soc/codecs/rt5631.c

··· 1675 1675 MODULE_DEVICE_TABLE(i2c, rt5631_i2c_id); 1676 1676 1677 1677 #ifdef CONFIG_OF 1678 - static struct of_device_id rt5631_i2c_dt_ids[] = { 1678 + static const struct of_device_id rt5631_i2c_dt_ids[] = { 1679 1679 { .compatible = "realtek,rt5631"}, 1680 1680 { .compatible = "realtek,alc5631"}, 1681 1681 { }

+163

sound/soc/codecs/rt5677.c

··· 1034 1034 return 0; 1035 1035 } 1036 1036 1037 + /** 1038 + * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters 1039 + * @codec: SoC audio codec device. 1040 + * @filter_mask: mask of filters. 1041 + * @clk_src: clock source 1042 + * 1043 + * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can 1044 + * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1045 + * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1046 + * ASRC function will track i2s clock and generate a corresponding system clock 1047 + * for codec. This function provides an API to select the clock source for a 1048 + * set of filters specified by the mask. And the codec driver will turn on ASRC 1049 + * for these filters if ASRC is selected as their clock source. 1050 + */ 1051 + int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec, 1052 + unsigned int filter_mask, unsigned int clk_src) 1053 + { 1054 + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 1055 + unsigned int asrc3_mask = 0, asrc3_value = 0; 1056 + unsigned int asrc4_mask = 0, asrc4_value = 0; 1057 + unsigned int asrc5_mask = 0, asrc5_value = 0; 1058 + unsigned int asrc6_mask = 0, asrc6_value = 0; 1059 + unsigned int asrc7_mask = 0, asrc7_value = 0; 1060 + 1061 + switch (clk_src) { 1062 + case RT5677_CLK_SEL_SYS: 1063 + case RT5677_CLK_SEL_I2S1_ASRC: 1064 + case RT5677_CLK_SEL_I2S2_ASRC: 1065 + case RT5677_CLK_SEL_I2S3_ASRC: 1066 + case RT5677_CLK_SEL_I2S4_ASRC: 1067 + case RT5677_CLK_SEL_I2S5_ASRC: 1068 + case RT5677_CLK_SEL_I2S6_ASRC: 1069 + case RT5677_CLK_SEL_SYS2: 1070 + case RT5677_CLK_SEL_SYS3: 1071 + case RT5677_CLK_SEL_SYS4: 1072 + case RT5677_CLK_SEL_SYS5: 1073 + case RT5677_CLK_SEL_SYS6: 1074 + case RT5677_CLK_SEL_SYS7: 1075 + break; 1076 + 1077 + default: 1078 + return -EINVAL; 1079 + } 1080 + 1081 + /* ASRC 3 */ 1082 + if (filter_mask & RT5677_DA_STEREO_FILTER) { 1083 + asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK; 1084 + asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK) 1085 + | (clk_src << RT5677_DA_STO_CLK_SEL_SFT); 1086 + } 1087 + 1088 + if (filter_mask & RT5677_DA_MONO2_L_FILTER) { 1089 + asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK; 1090 + asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK) 1091 + | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT); 1092 + } 1093 + 1094 + if (filter_mask & RT5677_DA_MONO2_R_FILTER) { 1095 + asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK; 1096 + asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK) 1097 + | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT); 1098 + } 1099 + 1100 + if (asrc3_mask) 1101 + regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, 1102 + asrc3_value); 1103 + 1104 + /* ASRC 4 */ 1105 + if (filter_mask & RT5677_DA_MONO3_L_FILTER) { 1106 + asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK; 1107 + asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK) 1108 + | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT); 1109 + } 1110 + 1111 + if (filter_mask & RT5677_DA_MONO3_R_FILTER) { 1112 + asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK; 1113 + asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK) 1114 + | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT); 1115 + } 1116 + 1117 + if (filter_mask & RT5677_DA_MONO4_L_FILTER) { 1118 + asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK; 1119 + asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK) 1120 + | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT); 1121 + } 1122 + 1123 + if (filter_mask & RT5677_DA_MONO4_R_FILTER) { 1124 + asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK; 1125 + asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK) 1126 + | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT); 1127 + } 1128 + 1129 + if (asrc4_mask) 1130 + regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, 1131 + asrc4_value); 1132 + 1133 + /* ASRC 5 */ 1134 + if (filter_mask & RT5677_AD_STEREO1_FILTER) { 1135 + asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK; 1136 + asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK) 1137 + | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT); 1138 + } 1139 + 1140 + if (filter_mask & RT5677_AD_STEREO2_FILTER) { 1141 + asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK; 1142 + asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK) 1143 + | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT); 1144 + } 1145 + 1146 + if (filter_mask & RT5677_AD_STEREO3_FILTER) { 1147 + asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK; 1148 + asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK) 1149 + | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT); 1150 + } 1151 + 1152 + if (filter_mask & RT5677_AD_STEREO4_FILTER) { 1153 + asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK; 1154 + asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK) 1155 + | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT); 1156 + } 1157 + 1158 + if (asrc5_mask) 1159 + regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, 1160 + asrc5_value); 1161 + 1162 + /* ASRC 6 */ 1163 + if (filter_mask & RT5677_AD_MONO_L_FILTER) { 1164 + asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK; 1165 + asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK) 1166 + | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT); 1167 + } 1168 + 1169 + if (filter_mask & RT5677_AD_MONO_R_FILTER) { 1170 + asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK; 1171 + asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK) 1172 + | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT); 1173 + } 1174 + 1175 + if (asrc6_mask) 1176 + regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, 1177 + asrc6_value); 1178 + 1179 + /* ASRC 7 */ 1180 + if (filter_mask & RT5677_DSP_OB_0_3_FILTER) { 1181 + asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK; 1182 + asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK) 1183 + | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT); 1184 + } 1185 + 1186 + if (filter_mask & RT5677_DSP_OB_4_7_FILTER) { 1187 + asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK; 1188 + asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK) 1189 + | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT); 1190 + } 1191 + 1192 + if (asrc7_mask) 1193 + regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, 1194 + asrc7_value); 1195 + 1196 + return 0; 1197 + } 1198 + EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src); 1199 + 1037 1200 /* Digital Mixer */ 1038 1201 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { 1039 1202 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,

+79

sound/soc/codecs/rt5677.h

··· 1406 1406 #define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7) 1407 1407 #define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7) 1408 1408 1409 + /* ASRC Control 3 (0x85) */ 1410 + #define RT5677_DA_STO_CLK_SEL_MASK (0xf << 12) 1411 + #define RT5677_DA_STO_CLK_SEL_SFT 12 1412 + #define RT5677_DA_MONO2L_CLK_SEL_MASK (0xf << 4) 1413 + #define RT5677_DA_MONO2L_CLK_SEL_SFT 4 1414 + #define RT5677_DA_MONO2R_CLK_SEL_MASK (0xf << 0) 1415 + #define RT5677_DA_MONO2R_CLK_SEL_SFT 0 1416 + 1417 + /* ASRC Control 4 (0x86) */ 1418 + #define RT5677_DA_MONO3L_CLK_SEL_MASK (0xf << 12) 1419 + #define RT5677_DA_MONO3L_CLK_SEL_SFT 12 1420 + #define RT5677_DA_MONO3R_CLK_SEL_MASK (0xf << 8) 1421 + #define RT5677_DA_MONO3R_CLK_SEL_SFT 8 1422 + #define RT5677_DA_MONO4L_CLK_SEL_MASK (0xf << 4) 1423 + #define RT5677_DA_MONO4L_CLK_SEL_SFT 4 1424 + #define RT5677_DA_MONO4R_CLK_SEL_MASK (0xf << 0) 1425 + #define RT5677_DA_MONO4R_CLK_SEL_SFT 0 1426 + 1427 + /* ASRC Control 5 (0x87) */ 1428 + #define RT5677_AD_STO1_CLK_SEL_MASK (0xf << 12) 1429 + #define RT5677_AD_STO1_CLK_SEL_SFT 12 1430 + #define RT5677_AD_STO2_CLK_SEL_MASK (0xf << 8) 1431 + #define RT5677_AD_STO2_CLK_SEL_SFT 8 1432 + #define RT5677_AD_STO3_CLK_SEL_MASK (0xf << 4) 1433 + #define RT5677_AD_STO3_CLK_SEL_SFT 4 1434 + #define RT5677_AD_STO4_CLK_SEL_MASK (0xf << 0) 1435 + #define RT5677_AD_STO4_CLK_SEL_SFT 0 1436 + 1437 + /* ASRC Control 6 (0x88) */ 1438 + #define RT5677_AD_MONOL_CLK_SEL_MASK (0xf << 12) 1439 + #define RT5677_AD_MONOL_CLK_SEL_SFT 12 1440 + #define RT5677_AD_MONOR_CLK_SEL_MASK (0xf << 8) 1441 + #define RT5677_AD_MONOR_CLK_SEL_SFT 8 1442 + 1443 + /* ASRC Control 7 (0x89) */ 1444 + #define RT5677_DSP_OB_0_3_CLK_SEL_MASK (0xf << 12) 1445 + #define RT5677_DSP_OB_0_3_CLK_SEL_SFT 12 1446 + #define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8) 1447 + #define RT5677_DSP_OB_4_7_CLK_SEL_SFT 8 1448 + 1409 1449 /* VAD Function Control 4 (0x9f) */ 1410 1450 #define RT5677_VAD_SRC_MASK (0x7 << 8) 1411 1451 #define RT5677_VAD_SRC_SFT 8 ··· 1710 1670 RT5676, 1711 1671 }; 1712 1672 1673 + /* ASRC clock source selection */ 1674 + enum { 1675 + RT5677_CLK_SEL_SYS, 1676 + RT5677_CLK_SEL_I2S1_ASRC, 1677 + RT5677_CLK_SEL_I2S2_ASRC, 1678 + RT5677_CLK_SEL_I2S3_ASRC, 1679 + RT5677_CLK_SEL_I2S4_ASRC, 1680 + RT5677_CLK_SEL_I2S5_ASRC, 1681 + RT5677_CLK_SEL_I2S6_ASRC, 1682 + RT5677_CLK_SEL_SYS2, 1683 + RT5677_CLK_SEL_SYS3, 1684 + RT5677_CLK_SEL_SYS4, 1685 + RT5677_CLK_SEL_SYS5, 1686 + RT5677_CLK_SEL_SYS6, 1687 + RT5677_CLK_SEL_SYS7, 1688 + }; 1689 + 1690 + /* filter mask */ 1691 + enum { 1692 + RT5677_DA_STEREO_FILTER = 0x1, 1693 + RT5677_DA_MONO2_L_FILTER = (0x1 << 1), 1694 + RT5677_DA_MONO2_R_FILTER = (0x1 << 2), 1695 + RT5677_DA_MONO3_L_FILTER = (0x1 << 3), 1696 + RT5677_DA_MONO3_R_FILTER = (0x1 << 4), 1697 + RT5677_DA_MONO4_L_FILTER = (0x1 << 5), 1698 + RT5677_DA_MONO4_R_FILTER = (0x1 << 6), 1699 + RT5677_AD_STEREO1_FILTER = (0x1 << 7), 1700 + RT5677_AD_STEREO2_FILTER = (0x1 << 8), 1701 + RT5677_AD_STEREO3_FILTER = (0x1 << 9), 1702 + RT5677_AD_STEREO4_FILTER = (0x1 << 10), 1703 + RT5677_AD_MONO_L_FILTER = (0x1 << 11), 1704 + RT5677_AD_MONO_R_FILTER = (0x1 << 12), 1705 + RT5677_DSP_OB_0_3_FILTER = (0x1 << 13), 1706 + RT5677_DSP_OB_4_7_FILTER = (0x1 << 14), 1707 + }; 1708 + 1713 1709 struct rt5677_priv { 1714 1710 struct snd_soc_codec *codec; 1715 1711 struct rt5677_platform_data pdata; ··· 1771 1695 bool is_dsp_mode; 1772 1696 bool is_vref_slow; 1773 1697 }; 1698 + 1699 + int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec, 1700 + unsigned int filter_mask, unsigned int clk_src); 1774 1701 1775 1702 #endif /* __RT5677_H__ */

+8 -22

sound/soc/generic/simple-card.c

··· 125 125 { 126 126 int ret; 127 127 128 - if (set->fmt) { 129 - ret = snd_soc_dai_set_fmt(dai, set->fmt); 130 - if (ret && ret != -ENOTSUPP) { 131 - dev_err(dai->dev, "simple-card: set_fmt error\n"); 132 - goto err; 133 - } 134 - } 135 - 136 128 if (set->sysclk) { 137 129 ret = snd_soc_dai_set_sysclk(dai, 0, set->sysclk, 0); 138 130 if (ret && ret != -ENOTSUPP) { ··· 261 269 struct device_node *codec, 262 270 char *prefix, int idx) 263 271 { 272 + struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, idx); 264 273 struct device *dev = simple_priv_to_dev(priv); 265 274 struct device_node *bitclkmaster = NULL; 266 275 struct device_node *framemaster = NULL; 267 - struct simple_dai_props *dai_props = simple_priv_to_props(priv, idx); 268 - struct asoc_simple_dai *cpu_dai = &dai_props->cpu_dai; 269 - struct asoc_simple_dai *codec_dai = &dai_props->codec_dai; 270 276 unsigned int daifmt; 271 277 272 278 daifmt = snd_soc_of_parse_daifmt(node, prefix, ··· 279 289 */ 280 290 dev_dbg(dev, "Revert to legacy daifmt parsing\n"); 281 291 282 - cpu_dai->fmt = codec_dai->fmt = 283 - snd_soc_of_parse_daifmt(codec, NULL, NULL, NULL) | 292 + daifmt = snd_soc_of_parse_daifmt(codec, NULL, NULL, NULL) | 284 293 (daifmt & ~SND_SOC_DAIFMT_CLOCK_MASK); 285 294 } else { 286 295 if (codec == bitclkmaster) ··· 288 299 else 289 300 daifmt |= (codec == framemaster) ? 290 301 SND_SOC_DAIFMT_CBS_CFM : SND_SOC_DAIFMT_CBS_CFS; 291 - 292 - cpu_dai->fmt = daifmt; 293 - codec_dai->fmt = daifmt; 294 302 } 303 + 304 + dai_link->dai_fmt = daifmt; 295 305 296 306 of_node_put(bitclkmaster); 297 307 of_node_put(framemaster); ··· 372 384 dai_link->init = asoc_simple_card_dai_init; 373 385 374 386 dev_dbg(dev, "\tname : %s\n", dai_link->stream_name); 375 - dev_dbg(dev, "\tcpu : %s / %04x / %d\n", 387 + dev_dbg(dev, "\tformat : %04x\n", dai_link->dai_fmt); 388 + dev_dbg(dev, "\tcpu : %s / %d\n", 376 389 dai_link->cpu_dai_name, 377 - dai_props->cpu_dai.fmt, 378 390 dai_props->cpu_dai.sysclk); 379 - dev_dbg(dev, "\tcodec : %s / %04x / %d\n", 391 + dev_dbg(dev, "\tcodec : %s / %d\n", 380 392 dai_link->codec_dai_name, 381 - dai_props->codec_dai.fmt, 382 393 dai_props->codec_dai.sysclk); 383 394 384 395 /* ··· 564 577 dai_link->codec_name = cinfo->codec; 565 578 dai_link->cpu_dai_name = cinfo->cpu_dai.name; 566 579 dai_link->codec_dai_name = cinfo->codec_dai.name; 580 + dai_link->dai_fmt = cinfo->daifmt; 567 581 dai_link->init = asoc_simple_card_dai_init; 568 582 memcpy(&priv->dai_props->cpu_dai, &cinfo->cpu_dai, 569 583 sizeof(priv->dai_props->cpu_dai)); 570 584 memcpy(&priv->dai_props->codec_dai, &cinfo->codec_dai, 571 585 sizeof(priv->dai_props->codec_dai)); 572 586 573 - priv->dai_props->cpu_dai.fmt |= cinfo->daifmt; 574 - priv->dai_props->codec_dai.fmt |= cinfo->daifmt; 575 587 } 576 588 577 589 snd_soc_card_set_drvdata(&priv->snd_card, priv);