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kernel
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linux
drm/amdgpu: add psp v11.0.8 driver for cyan_skillfish
Introduce the psp v11.0.8 driver for cyan_skillfish.
Signed-off-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Lang Yu
and committed by
Alex Deucher
e330a68f
2766534b
+239
+1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
drivers/gpu/drm/amd/amdgpu/Makefile
+208
drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c
+208
drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c
···
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v11_0_8.h"
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#include "mp/mp_11_0_8_offset.h"
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static int psp_v11_0_8_ring_init(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring;
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struct amdgpu_device *adev = psp->adev;
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ring = &psp->km_ring;
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ring->ring_type = ring_type;
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/* allocate 4k Page of Local Frame Buffer memory for ring */
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ring->ring_size = 0x1000;
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ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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if (ret) {
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ring->ring_size = 0;
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return ret;
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}
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return 0;
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}
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static int psp_v11_0_8_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev)) {
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/* Write the ring destroy command*/
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
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0x80000000, 0x80000000, false);
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} else {
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/* Write the ring destroy command*/
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
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GFX_CTRL_CMD_ID_DESTROY_RINGS);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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}
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return ret;
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}
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static int psp_v11_0_8_ring_create(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev)) {
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ret = psp_v11_0_8_ring_stop(psp, ring_type);
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if (ret) {
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DRM_ERROR("psp_v11_0_8_ring_stop_sriov failed!\n");
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return ret;
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}
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/* Write low address of the ring to C2PMSG_102 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_103 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_101 */
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_101 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
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0x80000000, 0x8000FFFF, false);
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} else {
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/* Wait for sOS ready for ring creation */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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if (ret) {
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DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
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return ret;
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}
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_70 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
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/* Write size of ring to C2PMSG_71 */
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psp_ring_reg = ring->ring_size;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_64 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x8000FFFF, false);
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}
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return ret;
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}
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static int psp_v11_0_8_ring_destroy(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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ret = psp_v11_0_8_ring_stop(psp, ring_type);
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if (ret)
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DRM_ERROR("Fail to stop psp ring\n");
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amdgpu_bo_free_kernel(&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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return ret;
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}
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static uint32_t psp_v11_0_8_ring_get_wptr(struct psp_context *psp)
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{
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uint32_t data;
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev))
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data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
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else
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data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
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return data;
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}
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static void psp_v11_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value)
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{
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev)) {
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_CONSUME_CMD);
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} else
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
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}
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static const struct psp_funcs psp_v11_0_8_funcs = {
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.ring_init = psp_v11_0_8_ring_init,
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.ring_create = psp_v11_0_8_ring_create,
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.ring_stop = psp_v11_0_8_ring_stop,
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.ring_destroy = psp_v11_0_8_ring_destroy,
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.ring_get_wptr = psp_v11_0_8_ring_get_wptr,
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.ring_set_wptr = psp_v11_0_8_ring_set_wptr,
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};
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void psp_v11_0_8_set_psp_funcs(struct psp_context *psp)
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{
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psp->funcs = &psp_v11_0_8_funcs;
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}
+30
drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.h
+30
drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.h
···
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __PSP_V11_0_8_H__
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#define __PSP_V11_0_8_H__
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#include "amdgpu_psp.h"
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void psp_v11_0_8_set_psp_funcs(struct psp_context *psp);
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#endif