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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: display: lvds-data-mapping: Add 30-bit RGB pixel data mappings

Add "jeida-30" and "vesa-30" data mappings that are compatible with JEIDA
and VESA respectively.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241104032806.611890-8-victor.liu@nxp.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

authored by

Liu Ying and committed by
Dmitry Baryshkov e3160748 60641029

+31
+31
Documentation/devicetree/bindings/display/lvds-data-mapping.yaml
··· 26 26 Device compatible with those specifications have been marketed under the 27 27 FPD-Link and FlatLink brands. 28 28 29 + This bindings also supports 30-bit data mapping compatible with JEIDA and 30 + VESA. 31 + 29 32 properties: 30 33 data-mapping: 31 34 enum: 32 35 - jeida-18 33 36 - jeida-24 37 + - jeida-30 34 38 - vesa-24 39 + - vesa-30 35 40 description: | 36 41 The color signals mapping order. 37 42 ··· 65 60 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< 66 61 DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 67 62 63 + - "jeida-30" - 30-bit data mapping compatible with JEIDA and VESA. Data 64 + are transferred as follows on 5 LVDS lanes. 65 + 66 + Slot 0 1 2 3 4 5 6 67 + ________________ _________________ 68 + Clock \_______________________/ 69 + ______ ______ ______ ______ ______ ______ ______ 70 + DATA0 ><__G4__><__R9__><__R8__><__R7__><__R6__><__R5__><__R4__>< 71 + DATA1 ><__B5__><__B4__><__G9__><__G8__><__G7__><__G6__><__G5__>< 72 + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B9__><__B8__><__B7__><__B6__>< 73 + DATA3 ><_CTL3_><__B3__><__B2__><__G3__><__G2__><__R3__><__R2__>< 74 + DATA4 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 75 + 68 76 - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. 69 77 Data are transferred as follows on 4 LVDS lanes. 70 78 ··· 89 71 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 90 72 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 91 73 DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 74 + 75 + - "vesa-30" - 30-bit data mapping compatible with VESA. Data are 76 + transferred as follows on 5 LVDS lanes. 77 + 78 + Slot 0 1 2 3 4 5 6 79 + ________________ _________________ 80 + Clock \_______________________/ 81 + ______ ______ ______ ______ ______ ______ ______ 82 + DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 83 + DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 84 + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 85 + DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 86 + DATA4 ><_CTL3_><__B9__><__B8__><__G9__><__G8__><__R9__><__R8__>< 92 87 93 88 Control signals are mapped as follows. 94 89