CRIS: Drop code related to obsolete or unused kconfigs

-106

arch/cris/arch-v10/kernel/head.S

··· 354 354 blo 1b 355 355 nop 356 356 357 - #ifdef CONFIG_BLK_DEV_ETRAXIDE 358 - ;; disable ATA before enabling it in genconfig below 359 - moveq 0,$r0 360 - move.d $r0,[R_ATA_CTRL_DATA] 361 - move.d $r0,[R_ATA_TRANSFER_CNT] 362 - move.d $r0,[R_ATA_CONFIG] 363 - #if 0 364 - move.d R_PORT_G_DATA, $r1 365 - move.d $r0, [$r1]; assert ATA bus-reset 366 - nop 367 - nop 368 - nop 369 - nop 370 - nop 371 - nop 372 - move.d 0x08000000,$r0 373 - move.d $r0,[$r1] 374 - #endif 375 - #endif 376 - 377 - #ifdef CONFIG_JULIETTE 378 - ;; configure external DMA channel 0 before enabling it in genconfig 379 - 380 - moveq 0,$r0 381 - move.d $r0,[R_EXT_DMA_0_ADDR] 382 - ; cnt enable, word size, output, stop, size 0 383 - move.d IO_STATE (R_EXT_DMA_0_CMD, cnt, enable) \ 384 - | IO_STATE (R_EXT_DMA_0_CMD, rqpol, ahigh) \ 385 - | IO_STATE (R_EXT_DMA_0_CMD, apol, ahigh) \ 386 - | IO_STATE (R_EXT_DMA_0_CMD, rq_ack, burst) \ 387 - | IO_STATE (R_EXT_DMA_0_CMD, wid, word) \ 388 - | IO_STATE (R_EXT_DMA_0_CMD, dir, output) \ 389 - | IO_STATE (R_EXT_DMA_0_CMD, run, stop) \ 390 - | IO_FIELD (R_EXT_DMA_0_CMD, trf_count, 0),$r0 391 - move.d $r0,[R_EXT_DMA_0_CMD] 392 - 393 - ;; reset dma4 and wait for completion 394 - 395 - moveq IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0 396 - move.b $r0,[R_DMA_CH4_CMD] 397 - 1: move.b [R_DMA_CH4_CMD],$r0 398 - and.b IO_MASK (R_DMA_CH4_CMD, cmd),$r0 399 - cmp.b IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0 400 - beq 1b 401 - nop 402 - 403 - ;; reset dma5 and wait for completion 404 - 405 - moveq IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0 406 - move.b $r0,[R_DMA_CH5_CMD] 407 - 1: move.b [R_DMA_CH5_CMD],$r0 408 - and.b IO_MASK (R_DMA_CH5_CMD, cmd),$r0 409 - cmp.b IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0 410 - beq 1b 411 - nop 412 - #endif 413 - 414 357 ;; Etrax product HW genconfig setup 415 358 416 359 moveq 0,$r0 ··· 389 446 | IO_STATE (R_GEN_CONFIG, dma8, usb) \ 390 447 | IO_STATE (R_GEN_CONFIG, dma9, usb),$r0 391 448 392 - 393 - #if defined(CONFIG_ETRAX_DEF_R_PORT_G0_DIR_OUT) 394 - or.d IO_STATE (R_GEN_CONFIG, g0dir, out),$r0 395 - #endif 396 - 397 - #if defined(CONFIG_ETRAX_DEF_R_PORT_G8_15_DIR_OUT) 398 - or.d IO_STATE (R_GEN_CONFIG, g8_15dir, out),$r0 399 - #endif 400 - #if defined(CONFIG_ETRAX_DEF_R_PORT_G16_23_DIR_OUT) 401 - or.d IO_STATE (R_GEN_CONFIG, g16_23dir, out),$r0 402 - #endif 403 - 404 - #if defined(CONFIG_ETRAX_DEF_R_PORT_G24_DIR_OUT) 405 - or.d IO_STATE (R_GEN_CONFIG, g24dir, out),$r0 406 - #endif 407 449 408 450 move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG 409 451 ··· 428 500 ;; including their shadow registers 429 501 430 502 move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0 431 - #if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7) 432 - or.b IO_STATE (R_PORT_PA_DIR, dir7, output),$r0 433 - #endif 434 503 move.b $r0,[port_pa_dir_shadow] 435 504 move.b $r0,[R_PORT_PA_DIR] 436 505 move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA,$r0 437 - #if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7) 438 - #if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH) 439 - and.b ~(1 << 7),$r0 440 - #else 441 - or.b (1 << 7),$r0 442 - #endif 443 - #endif 444 506 move.b $r0,[port_pa_data_shadow] 445 507 move.b $r0,[R_PORT_PA_DATA] 446 508 ··· 438 520 move.b $r0,[port_pb_config_shadow] 439 521 move.b $r0,[R_PORT_PB_CONFIG] 440 522 move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR,$r0 441 - #if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5) 442 - or.b IO_STATE (R_PORT_PB_DIR, dir5, output),$r0 443 - #endif 444 523 move.b $r0,[port_pb_dir_shadow] 445 524 move.b $r0,[R_PORT_PB_DIR] 446 525 move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA,$r0 447 - #if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5) 448 - #if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH) 449 - and.b ~(1 << 5),$r0 450 - #else 451 - or.b (1 << 5),$r0 452 - #endif 453 - #endif 454 526 move.b $r0,[port_pb_data_shadow] 455 527 move.b $r0,[R_PORT_PB_DATA] 456 528 ··· 449 541 move.d $r0, [R_PORT_PB_I2C] 450 542 451 543 moveq 0,$r0 452 - #if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G10) 453 - #if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH) 454 - and.d ~(1 << 10),$r0 455 - #else 456 - or.d (1 << 10),$r0 457 - #endif 458 - #endif 459 - #if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G11) 460 - #if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH) 461 - and.d ~(1 << 11),$r0 462 - #else 463 - or.d (1 << 11),$r0 464 - #endif 465 - #endif 466 544 move.d $r0,[port_g_data_shadow] 467 545 move.d $r0,[R_PORT_G_DATA] 468 546

+3 -11

arch/cris/arch-v10/mm/init.c

··· 68 68 69 69 *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */ 70 70 IO_STATE(R_MMU_KSEG, seg_e, page ) | 71 - IO_STATE(R_MMU_KSEG, seg_d, page ) | 72 - IO_STATE(R_MMU_KSEG, seg_c, page ) | 71 + IO_STATE(R_MMU_KSEG, seg_d, page ) | 72 + IO_STATE(R_MMU_KSEG, seg_c, page ) | 73 73 IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */ 74 - #ifdef CONFIG_JULIETTE 75 - IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* ARTPEC etc. */ 76 - #else 77 74 IO_STATE(R_MMU_KSEG, seg_a, page ) | 78 - #endif 79 75 IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */ 80 76 IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */ 81 77 IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */ ··· 88 92 IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) | 89 93 IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) | 90 94 IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) | 91 - #ifdef CONFIG_JULIETTE 92 - IO_FIELD(R_MMU_KBASE_HI, base_a, 0xa ) | 93 - #else 94 95 IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) | 95 - #endif 96 96 IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) | 97 97 IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) ); 98 - 98 + 99 99 *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) | 100 100 IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) | 101 101 IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |

-2

arch/cris/arch-v32/kernel/debugport.c

··· 77 77 &ports[2]; 78 78 #elif defined(CONFIG_ETRAX_DEBUG_PORT3) 79 79 &ports[3]; 80 - #elif defined(CONFIG_ETRAX_DEBUG_PORT4) 81 - &ports[4]; 82 80 #else 83 81 NULL; 84 82 #endif

-4

arch/cris/arch-v32/kernel/head.S

··· 292 292 ;; For cramfs, partition starts with magic and length. 293 293 ;; For jffs2, a jhead is prepended which contains with magic and length. 294 294 ;; The jhead is not part of the jffs2 partition however. 295 - #ifndef CONFIG_ETRAXFS_SIM 296 295 move.d __bss_start, $r0 297 - #else 298 - move.d __end, $r0 299 - #endif 300 296 move.d [$r0], $r1 301 297 cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic? 302 298 beq 2f ; yes, jump

+1 -1

arch/cris/arch-v32/kernel/irq.c

··· 37 37 #define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ)) 38 38 #elif defined(CONFIG_ETRAX_KGDB_PORT1) 39 39 #define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ)) 40 - #elif defined(CONFIG_ETRAX_KGB_PORT2) 40 + #elif defined(CONFIG_ETRAX_KGDB_PORT2) 41 41 #define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ)) 42 42 #elif defined(CONFIG_ETRAX_KGDB_PORT3) 43 43 #define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))

-8

arch/cris/arch-v32/kernel/setup.c

··· 129 129 #ifdef CONFIG_RTC_DRV_PCF8563 130 130 {I2C_BOARD_INFO("pcf8563", 0x51)}, 131 131 #endif 132 - #ifdef CONFIG_ETRAX_VIRTUAL_GPIO 133 - {I2C_BOARD_INFO("vgpio", 0x20)}, 134 - {I2C_BOARD_INFO("vgpio", 0x21)}, 135 - #endif 136 132 {I2C_BOARD_INFO("pca9536", 0x41)}, 137 133 {I2C_BOARD_INFO("fnp300", 0x40)}, 138 134 {I2C_BOARD_INFO("fnp300", 0x42)}, ··· 142 146 {I2C_BOARD_INFO("tmp100", 0x4C)}, 143 147 {I2C_BOARD_INFO("tmp100", 0x4D)}, 144 148 {I2C_BOARD_INFO("tmp100", 0x4E)}, 145 - #ifdef CONFIG_ETRAX_VIRTUAL_GPIO 146 - {I2C_BOARD_INFO("vgpio", 0x20)}, 147 - {I2C_BOARD_INFO("vgpio", 0x21)}, 148 - #endif 149 149 {I2C_BOARD_INFO("pca9536", 0x41)}, 150 150 {I2C_BOARD_INFO("fnp300", 0x40)}, 151 151 {I2C_BOARD_INFO("fnp300", 0x42)},

-19

arch/cris/arch-v32/mach-fs/Kconfig

··· 192 192 Configures the initial data for the general port E bits. Most 193 193 products should use 00000 here. 194 194 195 - config ETRAX_DEF_GIO_PV_OE 196 - hex "GIO_PV_OE" 197 - depends on ETRAX_VIRTUAL_GPIO 198 - default "0000" 199 - help 200 - Configures the direction of virtual general port V bits. 1 is out, 201 - 0 is in. This is often totally different depending on the product 202 - used. These bits are used for all kinds of stuff. If you don't know 203 - what to use, it is always safe to put all as inputs, although 204 - floating inputs isn't good. 205 - 206 - config ETRAX_DEF_GIO_PV_OUT 207 - hex "GIO_PV_OUT" 208 - depends on ETRAX_VIRTUAL_GPIO 209 - default "0000" 210 - help 211 - Configures the initial data for the virtual general port V bits. 212 - Most products should use 0000 here. 213 - 214 195 endmenu 215 196 216 197 endif

-3

arch/cris/boot/rescue/head_v10.S

··· 281 281 #ifdef CONFIG_ETRAX_PB_LEDS 282 282 move.b $r2, [R_PORT_PB_DATA] 283 283 #endif 284 - #ifdef CONFIG_ETRAX_90000000_LEDS 285 - move.b $r2, [0x90000000] 286 - #endif 287 284 #endif 288 285 289 286 ;; check if we got something on the serial port

+1 -2

arch/cris/include/asm/eshlibld.h

··· 45 45 assumed that we want to share code when debugging (exposes more 46 46 trouble). */ 47 47 #ifndef SHARE_LIB_CORE 48 - # if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \ 49 - && !defined(CONFIG_SHARE_SHLIB_CORE) 48 + # if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) 50 49 # define SHARE_LIB_CORE 0 51 50 # else 52 51 # define SHARE_LIB_CORE 1

-157

arch/cris/include/uapi/asm/etraxgpio.h

··· 11 11 * g1-g7 and g25-g31 is both input and outputs but on different pins 12 12 * Also note that some bits change pins depending on what interfaces 13 13 * are enabled. 14 - * 15 - * For ETRAX FS (CONFIG_ETRAXFS): 16 - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction 17 - * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction 18 - * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction 19 - * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction 20 - * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction 21 - * /dev/leds minor 2, Access to leds depending on kernelconfig 22 - * 23 - * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): 24 - * /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction 25 - * /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction 26 - * /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction 27 - * /dev/gpiod minor 4, 32 bit GPIO, input only 28 - * /dev/leds minor 2, Access to leds depending on kernelconfig 29 - * /dev/pwm0 minor 16, PWM channel 0 on PA30 30 - * /dev/pwm1 minor 17, PWM channel 1 on PA31 31 - * /dev/pwm2 minor 18, PWM channel 2 on PB26 32 - * /dev/ppwm minor 19, PPWM channel 33 - * 34 14 */ 35 15 #ifndef _ASM_ETRAXGPIO_H 36 16 #define _ASM_ETRAXGPIO_H ··· 20 40 #define ETRAXGPIO_IOCTYPE 43 21 41 22 42 /* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ 23 - #ifdef CONFIG_ETRAX_ARCH_V10 24 43 #define GPIO_MINOR_A 0 25 44 #define GPIO_MINOR_B 1 26 45 #define GPIO_MINOR_LEDS 2 27 46 #define GPIO_MINOR_G 3 28 47 #define GPIO_MINOR_LAST 3 29 48 #define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST 30 - #endif 31 - 32 - #ifdef CONFIG_ETRAXFS 33 - #define GPIO_MINOR_A 0 34 - #define GPIO_MINOR_B 1 35 - #define GPIO_MINOR_LEDS 2 36 - #define GPIO_MINOR_C 3 37 - #define GPIO_MINOR_D 4 38 - #define GPIO_MINOR_E 5 39 - #ifdef CONFIG_ETRAX_VIRTUAL_GPIO 40 - #define GPIO_MINOR_V 6 41 - #define GPIO_MINOR_LAST 6 42 - #else 43 - #define GPIO_MINOR_LAST 5 44 - #endif 45 - #define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST 46 - #endif 47 - 48 - #ifdef CONFIG_CRIS_MACH_ARTPEC3 49 - #define GPIO_MINOR_A 0 50 - #define GPIO_MINOR_B 1 51 - #define GPIO_MINOR_LEDS 2 52 - #define GPIO_MINOR_C 3 53 - #define GPIO_MINOR_D 4 54 - #ifdef CONFIG_ETRAX_VIRTUAL_GPIO 55 - #define GPIO_MINOR_V 6 56 - #define GPIO_MINOR_LAST 6 57 - #else 58 - #define GPIO_MINOR_LAST 4 59 - #endif 60 - #define GPIO_MINOR_FIRST_PWM 16 61 - #define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0) 62 - #define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1) 63 - #define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2) 64 - #define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3) 65 - #define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM 66 - #define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM 67 - #endif 68 - 69 49 70 50 71 51 /* supported ioctl _IOC_NR's */ ··· 78 138 /* *arg updated with current input pins. */ 79 139 #define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */ 80 140 /* *arg updated with current output pins. */ 81 - 82 - /* The following ioctl's are applicable to the PWM channels only */ 83 - 84 - #define IO_PWM_SET_MODE 0x20 85 - 86 - enum io_pwm_mode { 87 - PWM_OFF = 0, /* disabled, deallocated */ 88 - PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ 89 - PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ 90 - PWM_VARFREQ = 3, /* individually configurable high/low periods */ 91 - PWM_SOFT = 4 /* software generated */ 92 - }; 93 - 94 - struct io_pwm_set_mode { 95 - enum io_pwm_mode mode; 96 - }; 97 - 98 - /* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns 99 - * from 10ns (value = 0) to 81920ns (value = 8191) 100 - * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to 101 - * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty 102 - * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) 103 - */ 104 - #define IO_PWM_SET_PERIOD 0x21 105 - 106 - struct io_pwm_set_period { 107 - unsigned int lo; /* 0..8191 */ 108 - unsigned int hi; /* 0..8191 */ 109 - }; 110 - 111 - /* Only for modes PWM_STANDARD and PWM_FAST. 112 - * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from 113 - * 0 (value = 0) to 255/256 (value = 255). 114 - * For PWM_FAST, set duty cycle of PWM output signal from 115 - * 0% (value = 0) to 100% (value = 255). Output signal in this mode 116 - * is a 10ns pulse surrounded by a high or low level depending on duty 117 - * cycle (except for 0% and 100% which result in a constant output). 118 - * Resulting output frequency varies from 50 MHz at 50% duty cycle, 119 - * down to 390 kHz at min/max duty cycle. 120 - */ 121 - #define IO_PWM_SET_DUTY 0x22 122 - 123 - struct io_pwm_set_duty { 124 - int duty; /* 0..255 */ 125 - }; 126 - 127 - /* Returns information about the latest PWM pulse. 128 - * lo: Length of the latest low period, in units of 10ns. 129 - * hi: Length of the latest high period, in units of 10ns. 130 - * cnt: Time since last detected edge, in units of 10ns. 131 - * 132 - * The input source to PWM is decied by IO_PWM_SET_INPUT_SRC. 133 - * 134 - * NOTE: All PWM devices is connected to the same input source. 135 - */ 136 - #define IO_PWM_GET_PERIOD 0x23 137 - 138 - struct io_pwm_get_period { 139 - unsigned int lo; 140 - unsigned int hi; 141 - unsigned int cnt; 142 - }; 143 - 144 - /* Sets the input source for the PWM input. For the src value see the 145 - * register description for gio:rw_pwm_in_cfg. 146 - * 147 - * NOTE: All PWM devices is connected to the same input source. 148 - */ 149 - #define IO_PWM_SET_INPUT_SRC 0x24 150 - struct io_pwm_set_input_src { 151 - unsigned int src; /* 0..7 */ 152 - }; 153 - 154 - /* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */ 155 - #define IO_PPWM_SET_DUTY 0x25 156 - 157 - struct io_ppwm_set_duty { 158 - int duty; /* 0..255 */ 159 - }; 160 - 161 - /* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure 162 - * PWM capable gpio pins: 163 - */ 164 - #define IO_PWMCLK_SETGET_CONFIG 0x26 165 - struct gpio_pwmclk_conf { 166 - unsigned int gpiopin; /* The pin number based on the opened device */ 167 - unsigned int baseclk; /* The base clock to use, or sw will select one close*/ 168 - unsigned int low; /* The number of low periods of the baseclk */ 169 - unsigned int high; /* The number of high periods of the baseclk */ 170 - }; 171 - 172 - /* Examples: 173 - * To get a symmetric 12 MHz clock without knowing anything about the hardware: 174 - * baseclk = 12000000, low = 0, high = 0 175 - * To just get info of current setting: 176 - * baseclk = 0, low = 0, high = 0, the values will be updated by driver. 177 - */ 178 141 179 142 #endif