ASoC: dt-bindings: rename q6afe.h to q6dsp-lpass-ports.h

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

move all LPASS audio ports defines from q6afe.h to q6dsp-lpass-ports.h
as these belong to LPASS IP.
Also this move helps in reusing this header across multiple audio
frameworks on Qualcomm Audio DSP.

This patch is split out of the dt-bindings patch to enable easy review.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211026111655.1702-4-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Srinivas Kandagatla and committed by

Mark Brown 4 years ago e3008b7c e44cfc9d

+210 -201

2 changed files

expand all

include

dt-bindings

sound

qcom,q6afe.h

qcom,q6dsp-lpass-ports.h

+2 -201

include/dt-bindings/sound/qcom,q6afe.h

··· 2 2 #ifndef __DT_BINDINGS_Q6_AFE_H__ 3 3 #define __DT_BINDINGS_Q6_AFE_H__ 4 4 5 - /* Audio Front End (AFE) virtual ports IDs */ 6 - #define HDMI_RX 1 7 - #define SLIMBUS_0_RX 2 8 - #define SLIMBUS_0_TX 3 9 - #define SLIMBUS_1_RX 4 10 - #define SLIMBUS_1_TX 5 11 - #define SLIMBUS_2_RX 6 12 - #define SLIMBUS_2_TX 7 13 - #define SLIMBUS_3_RX 8 14 - #define SLIMBUS_3_TX 9 15 - #define SLIMBUS_4_RX 10 16 - #define SLIMBUS_4_TX 11 17 - #define SLIMBUS_5_RX 12 18 - #define SLIMBUS_5_TX 13 19 - #define SLIMBUS_6_RX 14 20 - #define SLIMBUS_6_TX 15 21 - #define PRIMARY_MI2S_RX 16 22 - #define PRIMARY_MI2S_TX 17 23 - #define SECONDARY_MI2S_RX 18 24 - #define SECONDARY_MI2S_TX 19 25 - #define TERTIARY_MI2S_RX 20 26 - #define TERTIARY_MI2S_TX 21 27 - #define QUATERNARY_MI2S_RX 22 28 - #define QUATERNARY_MI2S_TX 23 29 - #define PRIMARY_TDM_RX_0 24 30 - #define PRIMARY_TDM_TX_0 25 31 - #define PRIMARY_TDM_RX_1 26 32 - #define PRIMARY_TDM_TX_1 27 33 - #define PRIMARY_TDM_RX_2 28 34 - #define PRIMARY_TDM_TX_2 29 35 - #define PRIMARY_TDM_RX_3 30 36 - #define PRIMARY_TDM_TX_3 31 37 - #define PRIMARY_TDM_RX_4 32 38 - #define PRIMARY_TDM_TX_4 33 39 - #define PRIMARY_TDM_RX_5 34 40 - #define PRIMARY_TDM_TX_5 35 41 - #define PRIMARY_TDM_RX_6 36 42 - #define PRIMARY_TDM_TX_6 37 43 - #define PRIMARY_TDM_RX_7 38 44 - #define PRIMARY_TDM_TX_7 39 45 - #define SECONDARY_TDM_RX_0 40 46 - #define SECONDARY_TDM_TX_0 41 47 - #define SECONDARY_TDM_RX_1 42 48 - #define SECONDARY_TDM_TX_1 43 49 - #define SECONDARY_TDM_RX_2 44 50 - #define SECONDARY_TDM_TX_2 45 51 - #define SECONDARY_TDM_RX_3 46 52 - #define SECONDARY_TDM_TX_3 47 53 - #define SECONDARY_TDM_RX_4 48 54 - #define SECONDARY_TDM_TX_4 49 55 - #define SECONDARY_TDM_RX_5 50 56 - #define SECONDARY_TDM_TX_5 51 57 - #define SECONDARY_TDM_RX_6 52 58 - #define SECONDARY_TDM_TX_6 53 59 - #define SECONDARY_TDM_RX_7 54 60 - #define SECONDARY_TDM_TX_7 55 61 - #define TERTIARY_TDM_RX_0 56 62 - #define TERTIARY_TDM_TX_0 57 63 - #define TERTIARY_TDM_RX_1 58 64 - #define TERTIARY_TDM_TX_1 59 65 - #define TERTIARY_TDM_RX_2 60 66 - #define TERTIARY_TDM_TX_2 61 67 - #define TERTIARY_TDM_RX_3 62 68 - #define TERTIARY_TDM_TX_3 63 69 - #define TERTIARY_TDM_RX_4 64 70 - #define TERTIARY_TDM_TX_4 65 71 - #define TERTIARY_TDM_RX_5 66 72 - #define TERTIARY_TDM_TX_5 67 73 - #define TERTIARY_TDM_RX_6 68 74 - #define TERTIARY_TDM_TX_6 69 75 - #define TERTIARY_TDM_RX_7 70 76 - #define TERTIARY_TDM_TX_7 71 77 - #define QUATERNARY_TDM_RX_0 72 78 - #define QUATERNARY_TDM_TX_0 73 79 - #define QUATERNARY_TDM_RX_1 74 80 - #define QUATERNARY_TDM_TX_1 75 81 - #define QUATERNARY_TDM_RX_2 76 82 - #define QUATERNARY_TDM_TX_2 77 83 - #define QUATERNARY_TDM_RX_3 78 84 - #define QUATERNARY_TDM_TX_3 79 85 - #define QUATERNARY_TDM_RX_4 80 86 - #define QUATERNARY_TDM_TX_4 81 87 - #define QUATERNARY_TDM_RX_5 82 88 - #define QUATERNARY_TDM_TX_5 83 89 - #define QUATERNARY_TDM_RX_6 84 90 - #define QUATERNARY_TDM_TX_6 85 91 - #define QUATERNARY_TDM_RX_7 86 92 - #define QUATERNARY_TDM_TX_7 87 93 - #define QUINARY_TDM_RX_0 88 94 - #define QUINARY_TDM_TX_0 89 95 - #define QUINARY_TDM_RX_1 90 96 - #define QUINARY_TDM_TX_1 91 97 - #define QUINARY_TDM_RX_2 92 98 - #define QUINARY_TDM_TX_2 93 99 - #define QUINARY_TDM_RX_3 94 100 - #define QUINARY_TDM_TX_3 95 101 - #define QUINARY_TDM_RX_4 96 102 - #define QUINARY_TDM_TX_4 97 103 - #define QUINARY_TDM_RX_5 98 104 - #define QUINARY_TDM_TX_5 99 105 - #define QUINARY_TDM_RX_6 100 106 - #define QUINARY_TDM_TX_6 101 107 - #define QUINARY_TDM_RX_7 102 108 - #define QUINARY_TDM_TX_7 103 109 - #define DISPLAY_PORT_RX 104 110 - #define WSA_CODEC_DMA_RX_0 105 111 - #define WSA_CODEC_DMA_TX_0 106 112 - #define WSA_CODEC_DMA_RX_1 107 113 - #define WSA_CODEC_DMA_TX_1 108 114 - #define WSA_CODEC_DMA_TX_2 109 115 - #define VA_CODEC_DMA_TX_0 110 116 - #define VA_CODEC_DMA_TX_1 111 117 - #define VA_CODEC_DMA_TX_2 112 118 - #define RX_CODEC_DMA_RX_0 113 119 - #define TX_CODEC_DMA_TX_0 114 120 - #define RX_CODEC_DMA_RX_1 115 121 - #define TX_CODEC_DMA_TX_1 116 122 - #define RX_CODEC_DMA_RX_2 117 123 - #define TX_CODEC_DMA_TX_2 118 124 - #define RX_CODEC_DMA_RX_3 119 125 - #define TX_CODEC_DMA_TX_3 120 126 - #define RX_CODEC_DMA_RX_4 121 127 - #define TX_CODEC_DMA_TX_4 122 128 - #define RX_CODEC_DMA_RX_5 123 129 - #define TX_CODEC_DMA_TX_5 124 130 - #define RX_CODEC_DMA_RX_6 125 131 - #define RX_CODEC_DMA_RX_7 126 132 - #define QUINARY_MI2S_RX 127 133 - #define QUINARY_MI2S_TX 128 5 + /* This file exists due to backward compatibility reasons, Please do not DELETE! */ 134 6 135 - #define LPASS_CLK_ID_PRI_MI2S_IBIT 1 136 - #define LPASS_CLK_ID_PRI_MI2S_EBIT 2 137 - #define LPASS_CLK_ID_SEC_MI2S_IBIT 3 138 - #define LPASS_CLK_ID_SEC_MI2S_EBIT 4 139 - #define LPASS_CLK_ID_TER_MI2S_IBIT 5 140 - #define LPASS_CLK_ID_TER_MI2S_EBIT 6 141 - #define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 142 - #define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 143 - #define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 144 - #define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 145 - #define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 146 - #define LPASS_CLK_ID_QUI_MI2S_IBIT 12 147 - #define LPASS_CLK_ID_QUI_MI2S_EBIT 13 148 - #define LPASS_CLK_ID_SEN_MI2S_IBIT 14 149 - #define LPASS_CLK_ID_SEN_MI2S_EBIT 15 150 - #define LPASS_CLK_ID_INT0_MI2S_IBIT 16 151 - #define LPASS_CLK_ID_INT1_MI2S_IBIT 17 152 - #define LPASS_CLK_ID_INT2_MI2S_IBIT 18 153 - #define LPASS_CLK_ID_INT3_MI2S_IBIT 19 154 - #define LPASS_CLK_ID_INT4_MI2S_IBIT 20 155 - #define LPASS_CLK_ID_INT5_MI2S_IBIT 21 156 - #define LPASS_CLK_ID_INT6_MI2S_IBIT 22 157 - #define LPASS_CLK_ID_QUI_MI2S_OSR 23 158 - #define LPASS_CLK_ID_PRI_PCM_IBIT 24 159 - #define LPASS_CLK_ID_PRI_PCM_EBIT 25 160 - #define LPASS_CLK_ID_SEC_PCM_IBIT 26 161 - #define LPASS_CLK_ID_SEC_PCM_EBIT 27 162 - #define LPASS_CLK_ID_TER_PCM_IBIT 28 163 - #define LPASS_CLK_ID_TER_PCM_EBIT 29 164 - #define LPASS_CLK_ID_QUAD_PCM_IBIT 30 165 - #define LPASS_CLK_ID_QUAD_PCM_EBIT 31 166 - #define LPASS_CLK_ID_QUIN_PCM_IBIT 32 167 - #define LPASS_CLK_ID_QUIN_PCM_EBIT 33 168 - #define LPASS_CLK_ID_QUI_PCM_OSR 34 169 - #define LPASS_CLK_ID_PRI_TDM_IBIT 35 170 - #define LPASS_CLK_ID_PRI_TDM_EBIT 36 171 - #define LPASS_CLK_ID_SEC_TDM_IBIT 37 172 - #define LPASS_CLK_ID_SEC_TDM_EBIT 38 173 - #define LPASS_CLK_ID_TER_TDM_IBIT 39 174 - #define LPASS_CLK_ID_TER_TDM_EBIT 40 175 - #define LPASS_CLK_ID_QUAD_TDM_IBIT 41 176 - #define LPASS_CLK_ID_QUAD_TDM_EBIT 42 177 - #define LPASS_CLK_ID_QUIN_TDM_IBIT 43 178 - #define LPASS_CLK_ID_QUIN_TDM_EBIT 44 179 - #define LPASS_CLK_ID_QUIN_TDM_OSR 45 180 - #define LPASS_CLK_ID_MCLK_1 46 181 - #define LPASS_CLK_ID_MCLK_2 47 182 - #define LPASS_CLK_ID_MCLK_3 48 183 - #define LPASS_CLK_ID_MCLK_4 49 184 - #define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 185 - #define LPASS_CLK_ID_INT_MCLK_0 51 186 - #define LPASS_CLK_ID_INT_MCLK_1 52 187 - #define LPASS_CLK_ID_MCLK_5 53 188 - #define LPASS_CLK_ID_WSA_CORE_MCLK 54 189 - #define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 190 - #define LPASS_CLK_ID_VA_CORE_MCLK 56 191 - #define LPASS_CLK_ID_TX_CORE_MCLK 57 192 - #define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 193 - #define LPASS_CLK_ID_RX_CORE_MCLK 59 194 - #define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 195 - #define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 196 - 197 - #define LPASS_HW_AVTIMER_VOTE 101 198 - #define LPASS_HW_MACRO_VOTE 102 199 - #define LPASS_HW_DCODEC_VOTE 103 200 - 201 - #define Q6AFE_MAX_CLK_ID 104 202 - 203 - #define LPASS_CLK_ATTRIBUTE_INVALID 0x0 204 - #define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 205 - #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 206 - #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 7 + #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 207 8 208 9 #endif /* __DT_BINDINGS_Q6_AFE_H__ */

+208

include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + #ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ 3 + #define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ 4 + 5 + /* LPASS Audio virtual ports IDs */ 6 + #define HDMI_RX 1 7 + #define SLIMBUS_0_RX 2 8 + #define SLIMBUS_0_TX 3 9 + #define SLIMBUS_1_RX 4 10 + #define SLIMBUS_1_TX 5 11 + #define SLIMBUS_2_RX 6 12 + #define SLIMBUS_2_TX 7 13 + #define SLIMBUS_3_RX 8 14 + #define SLIMBUS_3_TX 9 15 + #define SLIMBUS_4_RX 10 16 + #define SLIMBUS_4_TX 11 17 + #define SLIMBUS_5_RX 12 18 + #define SLIMBUS_5_TX 13 19 + #define SLIMBUS_6_RX 14 20 + #define SLIMBUS_6_TX 15 21 + #define PRIMARY_MI2S_RX 16 22 + #define PRIMARY_MI2S_TX 17 23 + #define SECONDARY_MI2S_RX 18 24 + #define SECONDARY_MI2S_TX 19 25 + #define TERTIARY_MI2S_RX 20 26 + #define TERTIARY_MI2S_TX 21 27 + #define QUATERNARY_MI2S_RX 22 28 + #define QUATERNARY_MI2S_TX 23 29 + #define PRIMARY_TDM_RX_0 24 30 + #define PRIMARY_TDM_TX_0 25 31 + #define PRIMARY_TDM_RX_1 26 32 + #define PRIMARY_TDM_TX_1 27 33 + #define PRIMARY_TDM_RX_2 28 34 + #define PRIMARY_TDM_TX_2 29 35 + #define PRIMARY_TDM_RX_3 30 36 + #define PRIMARY_TDM_TX_3 31 37 + #define PRIMARY_TDM_RX_4 32 38 + #define PRIMARY_TDM_TX_4 33 39 + #define PRIMARY_TDM_RX_5 34 40 + #define PRIMARY_TDM_TX_5 35 41 + #define PRIMARY_TDM_RX_6 36 42 + #define PRIMARY_TDM_TX_6 37 43 + #define PRIMARY_TDM_RX_7 38 44 + #define PRIMARY_TDM_TX_7 39 45 + #define SECONDARY_TDM_RX_0 40 46 + #define SECONDARY_TDM_TX_0 41 47 + #define SECONDARY_TDM_RX_1 42 48 + #define SECONDARY_TDM_TX_1 43 49 + #define SECONDARY_TDM_RX_2 44 50 + #define SECONDARY_TDM_TX_2 45 51 + #define SECONDARY_TDM_RX_3 46 52 + #define SECONDARY_TDM_TX_3 47 53 + #define SECONDARY_TDM_RX_4 48 54 + #define SECONDARY_TDM_TX_4 49 55 + #define SECONDARY_TDM_RX_5 50 56 + #define SECONDARY_TDM_TX_5 51 57 + #define SECONDARY_TDM_RX_6 52 58 + #define SECONDARY_TDM_TX_6 53 59 + #define SECONDARY_TDM_RX_7 54 60 + #define SECONDARY_TDM_TX_7 55 61 + #define TERTIARY_TDM_RX_0 56 62 + #define TERTIARY_TDM_TX_0 57 63 + #define TERTIARY_TDM_RX_1 58 64 + #define TERTIARY_TDM_TX_1 59 65 + #define TERTIARY_TDM_RX_2 60 66 + #define TERTIARY_TDM_TX_2 61 67 + #define TERTIARY_TDM_RX_3 62 68 + #define TERTIARY_TDM_TX_3 63 69 + #define TERTIARY_TDM_RX_4 64 70 + #define TERTIARY_TDM_TX_4 65 71 + #define TERTIARY_TDM_RX_5 66 72 + #define TERTIARY_TDM_TX_5 67 73 + #define TERTIARY_TDM_RX_6 68 74 + #define TERTIARY_TDM_TX_6 69 75 + #define TERTIARY_TDM_RX_7 70 76 + #define TERTIARY_TDM_TX_7 71 77 + #define QUATERNARY_TDM_RX_0 72 78 + #define QUATERNARY_TDM_TX_0 73 79 + #define QUATERNARY_TDM_RX_1 74 80 + #define QUATERNARY_TDM_TX_1 75 81 + #define QUATERNARY_TDM_RX_2 76 82 + #define QUATERNARY_TDM_TX_2 77 83 + #define QUATERNARY_TDM_RX_3 78 84 + #define QUATERNARY_TDM_TX_3 79 85 + #define QUATERNARY_TDM_RX_4 80 86 + #define QUATERNARY_TDM_TX_4 81 87 + #define QUATERNARY_TDM_RX_5 82 88 + #define QUATERNARY_TDM_TX_5 83 89 + #define QUATERNARY_TDM_RX_6 84 90 + #define QUATERNARY_TDM_TX_6 85 91 + #define QUATERNARY_TDM_RX_7 86 92 + #define QUATERNARY_TDM_TX_7 87 93 + #define QUINARY_TDM_RX_0 88 94 + #define QUINARY_TDM_TX_0 89 95 + #define QUINARY_TDM_RX_1 90 96 + #define QUINARY_TDM_TX_1 91 97 + #define QUINARY_TDM_RX_2 92 98 + #define QUINARY_TDM_TX_2 93 99 + #define QUINARY_TDM_RX_3 94 100 + #define QUINARY_TDM_TX_3 95 101 + #define QUINARY_TDM_RX_4 96 102 + #define QUINARY_TDM_TX_4 97 103 + #define QUINARY_TDM_RX_5 98 104 + #define QUINARY_TDM_TX_5 99 105 + #define QUINARY_TDM_RX_6 100 106 + #define QUINARY_TDM_TX_6 101 107 + #define QUINARY_TDM_RX_7 102 108 + #define QUINARY_TDM_TX_7 103 109 + #define DISPLAY_PORT_RX 104 110 + #define WSA_CODEC_DMA_RX_0 105 111 + #define WSA_CODEC_DMA_TX_0 106 112 + #define WSA_CODEC_DMA_RX_1 107 113 + #define WSA_CODEC_DMA_TX_1 108 114 + #define WSA_CODEC_DMA_TX_2 109 115 + #define VA_CODEC_DMA_TX_0 110 116 + #define VA_CODEC_DMA_TX_1 111 117 + #define VA_CODEC_DMA_TX_2 112 118 + #define RX_CODEC_DMA_RX_0 113 119 + #define TX_CODEC_DMA_TX_0 114 120 + #define RX_CODEC_DMA_RX_1 115 121 + #define TX_CODEC_DMA_TX_1 116 122 + #define RX_CODEC_DMA_RX_2 117 123 + #define TX_CODEC_DMA_TX_2 118 124 + #define RX_CODEC_DMA_RX_3 119 125 + #define TX_CODEC_DMA_TX_3 120 126 + #define RX_CODEC_DMA_RX_4 121 127 + #define TX_CODEC_DMA_TX_4 122 128 + #define RX_CODEC_DMA_RX_5 123 129 + #define TX_CODEC_DMA_TX_5 124 130 + #define RX_CODEC_DMA_RX_6 125 131 + #define RX_CODEC_DMA_RX_7 126 132 + #define QUINARY_MI2S_RX 127 133 + #define QUINARY_MI2S_TX 128 134 + 135 + #define LPASS_CLK_ID_PRI_MI2S_IBIT 1 136 + #define LPASS_CLK_ID_PRI_MI2S_EBIT 2 137 + #define LPASS_CLK_ID_SEC_MI2S_IBIT 3 138 + #define LPASS_CLK_ID_SEC_MI2S_EBIT 4 139 + #define LPASS_CLK_ID_TER_MI2S_IBIT 5 140 + #define LPASS_CLK_ID_TER_MI2S_EBIT 6 141 + #define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 142 + #define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 143 + #define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 144 + #define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 145 + #define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 146 + #define LPASS_CLK_ID_QUI_MI2S_IBIT 12 147 + #define LPASS_CLK_ID_QUI_MI2S_EBIT 13 148 + #define LPASS_CLK_ID_SEN_MI2S_IBIT 14 149 + #define LPASS_CLK_ID_SEN_MI2S_EBIT 15 150 + #define LPASS_CLK_ID_INT0_MI2S_IBIT 16 151 + #define LPASS_CLK_ID_INT1_MI2S_IBIT 17 152 + #define LPASS_CLK_ID_INT2_MI2S_IBIT 18 153 + #define LPASS_CLK_ID_INT3_MI2S_IBIT 19 154 + #define LPASS_CLK_ID_INT4_MI2S_IBIT 20 155 + #define LPASS_CLK_ID_INT5_MI2S_IBIT 21 156 + #define LPASS_CLK_ID_INT6_MI2S_IBIT 22 157 + #define LPASS_CLK_ID_QUI_MI2S_OSR 23 158 + #define LPASS_CLK_ID_PRI_PCM_IBIT 24 159 + #define LPASS_CLK_ID_PRI_PCM_EBIT 25 160 + #define LPASS_CLK_ID_SEC_PCM_IBIT 26 161 + #define LPASS_CLK_ID_SEC_PCM_EBIT 27 162 + #define LPASS_CLK_ID_TER_PCM_IBIT 28 163 + #define LPASS_CLK_ID_TER_PCM_EBIT 29 164 + #define LPASS_CLK_ID_QUAD_PCM_IBIT 30 165 + #define LPASS_CLK_ID_QUAD_PCM_EBIT 31 166 + #define LPASS_CLK_ID_QUIN_PCM_IBIT 32 167 + #define LPASS_CLK_ID_QUIN_PCM_EBIT 33 168 + #define LPASS_CLK_ID_QUI_PCM_OSR 34 169 + #define LPASS_CLK_ID_PRI_TDM_IBIT 35 170 + #define LPASS_CLK_ID_PRI_TDM_EBIT 36 171 + #define LPASS_CLK_ID_SEC_TDM_IBIT 37 172 + #define LPASS_CLK_ID_SEC_TDM_EBIT 38 173 + #define LPASS_CLK_ID_TER_TDM_IBIT 39 174 + #define LPASS_CLK_ID_TER_TDM_EBIT 40 175 + #define LPASS_CLK_ID_QUAD_TDM_IBIT 41 176 + #define LPASS_CLK_ID_QUAD_TDM_EBIT 42 177 + #define LPASS_CLK_ID_QUIN_TDM_IBIT 43 178 + #define LPASS_CLK_ID_QUIN_TDM_EBIT 44 179 + #define LPASS_CLK_ID_QUIN_TDM_OSR 45 180 + #define LPASS_CLK_ID_MCLK_1 46 181 + #define LPASS_CLK_ID_MCLK_2 47 182 + #define LPASS_CLK_ID_MCLK_3 48 183 + #define LPASS_CLK_ID_MCLK_4 49 184 + #define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 185 + #define LPASS_CLK_ID_INT_MCLK_0 51 186 + #define LPASS_CLK_ID_INT_MCLK_1 52 187 + #define LPASS_CLK_ID_MCLK_5 53 188 + #define LPASS_CLK_ID_WSA_CORE_MCLK 54 189 + #define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 190 + #define LPASS_CLK_ID_VA_CORE_MCLK 56 191 + #define LPASS_CLK_ID_TX_CORE_MCLK 57 192 + #define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 193 + #define LPASS_CLK_ID_RX_CORE_MCLK 59 194 + #define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 195 + #define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 196 + 197 + #define LPASS_HW_AVTIMER_VOTE 101 198 + #define LPASS_HW_MACRO_VOTE 102 199 + #define LPASS_HW_DCODEC_VOTE 103 200 + 201 + #define Q6AFE_MAX_CLK_ID 104 202 + 203 + #define LPASS_CLK_ATTRIBUTE_INVALID 0x0 204 + #define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 205 + #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 206 + #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 207 + 208 + #endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */