tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

USB: r8a66597-hcd: fixes some problem

This patch incorporates some updates. Updates include:

- Fix the problem that control transfer might fail
- Change from GFP_KERNEL to GFP_ATOMIC
- Clean up some coding style issue

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

authored by

Yoshihiro Shimoda and committed by
Greg Kroah-Hartman e294531d 809a58b8

+96 -101
+54 -56
drivers/usb/host/r8a66597-hcd.c
··· 35 35 #include <linux/interrupt.h> 36 36 #include <linux/usb.h> 37 37 #include <linux/platform_device.h> 38 - 39 - #include <asm/io.h> 40 - #include <asm/irq.h> 41 - #include <asm/system.h> 38 + #include <linux/io.h> 39 + #include <linux/irq.h> 42 40 43 41 #include "../core/hcd.h" 44 42 #include "r8a66597.h" ··· 52 54 /* module parameters */ 53 55 static unsigned short clock = XTAL12; 54 56 module_param(clock, ushort, 0644); 55 - MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0(default=0)"); 57 + MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 " 58 + "(default=0)"); 59 + 56 60 static unsigned short vif = LDRV; 57 61 module_param(vif, ushort, 0644); 58 62 MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)"); 59 - static unsigned short endian = 0; 63 + 64 + static unsigned short endian; 60 65 module_param(endian, ushort, 0644); 61 - MODULE_PARM_DESC(endian, "data endian: big=256, little=0(default=0)"); 66 + MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)"); 67 + 62 68 static unsigned short irq_sense = INTL; 63 69 module_param(irq_sense, ushort, 0644); 64 - MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=32, falling edge=0(default=32)"); 70 + MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=32, falling edge=0 " 71 + "(default=32)"); 65 72 66 73 static void packet_write(struct r8a66597 *r8a66597, u16 pipenum); 67 74 static int r8a66597_get_frame(struct usb_hcd *hcd); ··· 311 308 struct r8a66597_device *dev; 312 309 int usb_address = urb->setup_packet[2]; /* urb->pipe is address 0 */ 313 310 314 - dev = kzalloc(sizeof(struct r8a66597_device), GFP_KERNEL); 311 + dev = kzalloc(sizeof(struct r8a66597_device), GFP_ATOMIC); 315 312 if (dev == NULL) 316 313 return -ENOMEM; 317 314 ··· 614 611 u16 array[R8A66597_MAX_NUM_PIPE], i = 0, min; 615 612 616 613 memset(array, 0, sizeof(array)); 617 - switch(ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { 618 - case USB_ENDPOINT_XFER_BULK: 614 + switch (ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { 615 + case USB_ENDPOINT_XFER_BULK: 619 616 if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) 620 617 array[i++] = 4; 621 618 else { 622 619 array[i++] = 3; 623 620 array[i++] = 5; 624 621 } 625 - break; 626 - case USB_ENDPOINT_XFER_INT: 622 + break; 623 + case USB_ENDPOINT_XFER_INT: 627 624 if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) { 628 625 array[i++] = 6; 629 626 array[i++] = 7; 630 627 array[i++] = 8; 631 628 } else 632 629 array[i++] = 9; 633 - break; 634 - case USB_ENDPOINT_XFER_ISOC: 630 + break; 631 + case USB_ENDPOINT_XFER_ISOC: 635 632 if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) 636 633 array[i++] = 2; 637 634 else 638 635 array[i++] = 1; 639 - break; 640 - default: 641 - err("Illegal type"); 642 - return 0; 643 - } 636 + break; 637 + default: 638 + err("Illegal type"); 639 + return 0; 640 + } 644 641 645 642 i = 1; 646 643 min = array[0]; ··· 657 654 { 658 655 u16 r8a66597_type; 659 656 660 - switch(type) { 657 + switch (type) { 661 658 case USB_ENDPOINT_XFER_BULK: 662 659 r8a66597_type = R8A66597_BULK; 663 660 break; ··· 877 874 { 878 875 r8a66597->root_hub[port].port |= (1 << USB_PORT_FEAT_CONNECTION) 879 876 | (1 << USB_PORT_FEAT_C_CONNECTION); 880 - r8a66597_write(r8a66597, (u16)~DTCH, get_intsts_reg(port)); 877 + r8a66597_write(r8a66597, ~DTCH, get_intsts_reg(port)); 881 878 r8a66597_bset(r8a66597, DTCHE, get_intenb_reg(port)); 882 879 } 883 880 ··· 920 917 921 918 r8a66597_write(r8a66597, make_devsel(td->address) | td->maxpacket, 922 919 DCPMAXP); 923 - r8a66597_write(r8a66597, (u16)~(SIGN | SACK), INTSTS1); 920 + r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1); 924 921 925 922 for (i = 0; i < 4; i++) { 926 923 r8a66597_write(r8a66597, p[i], setup_addr); ··· 951 948 pipe_irq_disable(r8a66597, td->pipenum); 952 949 pipe_setting(r8a66597, td); 953 950 pipe_stop(r8a66597, td->pipe); 954 - r8a66597_write(r8a66597, (u16)~(1 << td->pipenum), 955 - BRDYSTS); 951 + r8a66597_write(r8a66597, ~(1 << td->pipenum), BRDYSTS); 956 952 957 953 if (td->pipe->pipetre) { 958 954 r8a66597_write(r8a66597, TRCLR, 959 - td->pipe->pipetre); 955 + td->pipe->pipetre); 960 956 r8a66597_write(r8a66597, 961 - (urb->transfer_buffer_length 962 - + td->maxpacket - 1) 963 - / td->maxpacket, 964 - td->pipe->pipetrn); 957 + (urb->transfer_buffer_length 958 + + td->maxpacket - 1) 959 + / td->maxpacket, 960 + td->pipe->pipetrn); 965 961 r8a66597_bset(r8a66597, TRENB, 966 - td->pipe->pipetre); 962 + td->pipe->pipetre); 967 963 } 968 964 969 965 pipe_start(r8a66597, td->pipe); ··· 993 991 if (td->pipe->pipetre) 994 992 r8a66597_bclr(r8a66597, TRENB, td->pipe->pipetre); 995 993 } 996 - r8a66597_write(r8a66597, (u16)~(1 << td->pipenum), BRDYSTS); 994 + r8a66597_write(r8a66597, ~(1 << td->pipenum), BRDYSTS); 997 995 998 996 fifo_change_from_pipe(r8a66597, td->pipe); 999 997 tmp = r8a66597_read(r8a66597, td->pipe->fifoctr); ··· 1011 1009 struct urb *urb = td->urb; 1012 1010 1013 1011 r8a66597_pipe_toggle(r8a66597, td->pipe, 1); 1012 + pipe_stop(r8a66597, td->pipe); 1014 1013 1015 1014 if (urb->setup_packet[0] & USB_ENDPOINT_DIR_MASK) { 1016 1015 r8a66597_bset(r8a66597, R8A66597_DIR, DCPCFG); 1017 1016 r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL); 1018 1017 r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); 1019 - r8a66597_write(r8a66597, BVAL | BCLR, CFIFOCTR); 1020 - r8a66597_write(r8a66597, (u16)~BEMP0, BEMPSTS); 1018 + r8a66597_write(r8a66597, ~BEMP0, BEMPSTS); 1019 + r8a66597_write(r8a66597, BCLR, CFIFOCTR); 1020 + r8a66597_write(r8a66597, BVAL, CFIFOCTR); 1021 1021 enable_irq_empty(r8a66597, 0); 1022 1022 } else { 1023 1023 r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG); 1024 1024 r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL); 1025 1025 r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); 1026 1026 r8a66597_write(r8a66597, BCLR, CFIFOCTR); 1027 - r8a66597_write(r8a66597, (u16)~BRDY0, BRDYSTS); 1028 - r8a66597_write(r8a66597, (u16)~BEMP0, BEMPSTS); 1029 1027 enable_irq_ready(r8a66597, 0); 1030 1028 } 1031 1029 enable_irq_nrdy(r8a66597, 0); ··· 1271 1269 1272 1270 /* write fifo */ 1273 1271 if (pipenum > 0) 1274 - r8a66597_write(r8a66597, (u16)~(1 << pipenum), BEMPSTS); 1272 + r8a66597_write(r8a66597, ~(1 << pipenum), BEMPSTS); 1275 1273 if (urb->transfer_buffer) { 1276 1274 r8a66597_write_fifo(r8a66597, td->pipe->fifoaddr, buf, size); 1277 1275 if (!usb_pipebulk(urb->pipe) || td->maxpacket != size) ··· 1364 1362 1365 1363 mask = r8a66597_read(r8a66597, BRDYSTS) 1366 1364 & r8a66597_read(r8a66597, BRDYENB); 1367 - r8a66597_write(r8a66597, (u16)~mask, BRDYSTS); 1365 + r8a66597_write(r8a66597, ~mask, BRDYSTS); 1368 1366 if (mask & BRDY0) { 1369 1367 td = r8a66597_get_td(r8a66597, 0); 1370 1368 if (td && td->type == USB_PID_IN) ··· 1399 1397 1400 1398 mask = r8a66597_read(r8a66597, BEMPSTS) 1401 1399 & r8a66597_read(r8a66597, BEMPENB); 1402 - r8a66597_write(r8a66597, (u16)~mask, BEMPSTS); 1400 + r8a66597_write(r8a66597, ~mask, BEMPSTS); 1403 1401 if (mask & BEMP0) { 1404 1402 cfifo_change(r8a66597, 0); 1405 1403 td = r8a66597_get_td(r8a66597, 0); ··· 1436 1434 1437 1435 mask = r8a66597_read(r8a66597, NRDYSTS) 1438 1436 & r8a66597_read(r8a66597, NRDYENB); 1439 - r8a66597_write(r8a66597, (u16)~mask, NRDYSTS); 1437 + r8a66597_write(r8a66597, ~mask, NRDYSTS); 1440 1438 if (mask & NRDY0) { 1441 1439 cfifo_change(r8a66597, 0); 1442 1440 set_urb_error(r8a66597, 0); ··· 1490 1488 mask0 = intsts0 & intenb0 & (BEMP | NRDY | BRDY); 1491 1489 if (mask2) { 1492 1490 if (mask2 & ATTCH) { 1493 - r8a66597_write(r8a66597, (u16)~ATTCH, INTSTS2); 1491 + r8a66597_write(r8a66597, ~ATTCH, INTSTS2); 1494 1492 r8a66597_bclr(r8a66597, ATTCHE, INTENB2); 1495 1493 1496 1494 /* start usb bus sampling */ 1497 1495 start_root_hub_sampling(r8a66597, 1); 1498 1496 } 1499 1497 if (mask2 & DTCH) { 1500 - r8a66597_write(r8a66597, (u16)~DTCH, INTSTS2); 1498 + r8a66597_write(r8a66597, ~DTCH, INTSTS2); 1501 1499 r8a66597_bclr(r8a66597, DTCHE, INTENB2); 1502 1500 r8a66597_usb_disconnect(r8a66597, 1); 1503 1501 } ··· 1505 1503 1506 1504 if (mask1) { 1507 1505 if (mask1 & ATTCH) { 1508 - r8a66597_write(r8a66597, (u16)~ATTCH, INTSTS1); 1506 + r8a66597_write(r8a66597, ~ATTCH, INTSTS1); 1509 1507 r8a66597_bclr(r8a66597, ATTCHE, INTENB1); 1510 1508 1511 1509 /* start usb bus sampling */ 1512 1510 start_root_hub_sampling(r8a66597, 0); 1513 1511 } 1514 1512 if (mask1 & DTCH) { 1515 - r8a66597_write(r8a66597, (u16)~DTCH, INTSTS1); 1513 + r8a66597_write(r8a66597, ~DTCH, INTSTS1); 1516 1514 r8a66597_bclr(r8a66597, DTCHE, INTENB1); 1517 1515 r8a66597_usb_disconnect(r8a66597, 0); 1518 1516 } 1519 1517 if (mask1 & SIGN) { 1520 - r8a66597_write(r8a66597, (u16)~SIGN, INTSTS1); 1518 + r8a66597_write(r8a66597, ~SIGN, INTSTS1); 1521 1519 set_urb_error(r8a66597, 0); 1522 1520 check_next_phase(r8a66597); 1523 1521 } 1524 1522 if (mask1 & SACK) { 1525 - r8a66597_write(r8a66597, (u16)~SACK, INTSTS1); 1523 + r8a66597_write(r8a66597, ~SACK, INTSTS1); 1526 1524 check_next_phase(r8a66597); 1527 1525 } 1528 1526 } ··· 1665 1663 static int r8a66597_start(struct usb_hcd *hcd) 1666 1664 { 1667 1665 struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd); 1668 - int ret; 1669 1666 1670 1667 hcd->state = HC_STATE_RUNNING; 1671 - if ((ret = enable_controller(r8a66597)) < 0) 1672 - return ret; 1673 - 1674 - return 0; 1668 + return enable_controller(r8a66597); 1675 1669 } 1676 1670 1677 1671 static void r8a66597_stop(struct usb_hcd *hcd) ··· 1694 1696 1695 1697 static struct r8a66597_td *r8a66597_make_td(struct r8a66597 *r8a66597, 1696 1698 struct urb *urb, 1697 - struct usb_host_endpoint *hep, 1698 - gfp_t mem_flags) 1699 + struct usb_host_endpoint *hep) 1699 1700 { 1700 1701 struct r8a66597_td *td; 1701 1702 u16 pipenum; 1702 1703 1703 - td = kzalloc(sizeof(struct r8a66597_td), mem_flags); 1704 + td = kzalloc(sizeof(struct r8a66597_td), GFP_ATOMIC); 1704 1705 if (td == NULL) 1705 1706 return NULL; 1706 1707 ··· 1738 1741 } 1739 1742 1740 1743 if (!hep->hcpriv) { 1741 - hep->hcpriv = kzalloc(sizeof(struct r8a66597_pipe), mem_flags); 1744 + hep->hcpriv = kzalloc(sizeof(struct r8a66597_pipe), 1745 + GFP_ATOMIC); 1742 1746 if (!hep->hcpriv) { 1743 1747 ret = -ENOMEM; 1744 1748 goto error; ··· 1753 1755 init_pipe_config(r8a66597, urb); 1754 1756 1755 1757 set_address_zero(r8a66597, urb); 1756 - td = r8a66597_make_td(r8a66597, urb, hep, mem_flags); 1758 + td = r8a66597_make_td(r8a66597, urb, hep); 1757 1759 if (td == NULL) { 1758 1760 ret = -ENOMEM; 1759 1761 goto error;
+42 -45
drivers/usb/host/r8a66597.h
··· 203 203 #define DTLN 0x0FFF /* b11-0: FIFO received data length */ 204 204 205 205 /* Interrupt Enable Register 0 */ 206 - #define VBSE 0x8000 /* b15: VBUS interrupt */ 207 - #define RSME 0x4000 /* b14: Resume interrupt */ 208 - #define SOFE 0x2000 /* b13: Frame update interrupt */ 209 - #define DVSE 0x1000 /* b12: Device state transition interrupt */ 210 - #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ 211 - #define BEMPE 0x0400 /* b10: Buffer empty interrupt */ 212 - #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 213 - #define BRDYE 0x0100 /* b8: Buffer ready interrupt */ 206 + #define VBSE 0x8000 /* b15: VBUS interrupt */ 207 + #define RSME 0x4000 /* b14: Resume interrupt */ 208 + #define SOFE 0x2000 /* b13: Frame update interrupt */ 209 + #define DVSE 0x1000 /* b12: Device state transition interrupt */ 210 + #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ 211 + #define BEMPE 0x0400 /* b10: Buffer empty interrupt */ 212 + #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 213 + #define BRDYE 0x0100 /* b8: Buffer ready interrupt */ 214 214 215 215 /* Interrupt Enable Register 1 */ 216 216 #define OVRCRE 0x8000 /* b15: Over-current interrupt */ ··· 268 268 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */ 269 269 270 270 /* Interrupt Status Register 0 */ 271 - #define VBINT 0x8000 /* b15: VBUS interrupt */ 272 - #define RESM 0x4000 /* b14: Resume interrupt */ 273 - #define SOFR 0x2000 /* b13: SOF frame update interrupt */ 274 - #define DVST 0x1000 /* b12: Device state transition interrupt */ 275 - #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ 276 - #define BEMP 0x0400 /* b10: Buffer empty interrupt */ 277 - #define NRDY 0x0200 /* b9: Buffer not ready interrupt */ 278 - #define BRDY 0x0100 /* b8: Buffer ready interrupt */ 279 - #define VBSTS 0x0080 /* b7: VBUS input port */ 280 - #define DVSQ 0x0070 /* b6-4: Device state */ 271 + #define VBINT 0x8000 /* b15: VBUS interrupt */ 272 + #define RESM 0x4000 /* b14: Resume interrupt */ 273 + #define SOFR 0x2000 /* b13: SOF frame update interrupt */ 274 + #define DVST 0x1000 /* b12: Device state transition interrupt */ 275 + #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ 276 + #define BEMP 0x0400 /* b10: Buffer empty interrupt */ 277 + #define NRDY 0x0200 /* b9: Buffer not ready interrupt */ 278 + #define BRDY 0x0100 /* b8: Buffer ready interrupt */ 279 + #define VBSTS 0x0080 /* b7: VBUS input port */ 280 + #define DVSQ 0x0070 /* b6-4: Device state */ 281 281 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */ 282 282 #define DS_SPD_ADDR 0x0060 /* Suspend Address */ 283 283 #define DS_SPD_DFLT 0x0050 /* Suspend Default */ ··· 315 315 /* Micro Frame Number Register */ 316 316 #define UFRNM 0x0007 /* b2-0: Micro frame number */ 317 317 318 - /* USB Address / Low Power Status Recovery Register */ 319 - //#define USBADDR 0x007F /* b6-0: USB address */ 320 - 321 318 /* Default Control Pipe Maxpacket Size Register */ 322 319 /* Pipe Maxpacket Size Register */ 323 - #define DEVSEL 0xF000 /* b15-14: Device address select */ 324 - #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ 320 + #define DEVSEL 0xF000 /* b15-14: Device address select */ 321 + #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ 325 322 326 323 /* Default Control Pipe Control Register */ 327 324 #define BSTS 0x8000 /* b15: Buffer status */ ··· 363 366 #define MXPS 0x07FF /* b10-0: Maxpacket size */ 364 367 365 368 /* Pipe Cycle Configuration Register */ 366 - #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ 367 - #define IITV 0x0007 /* b2-0: Isochronous interval */ 369 + #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ 370 + #define IITV 0x0007 /* b2-0: Isochronous interval */ 368 371 369 372 /* Pipex Control Register */ 370 - #define BSTS 0x8000 /* b15: Buffer status */ 371 - #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ 372 - #define CSCLR 0x2000 /* b13: complete-split status clear */ 373 - #define CSSTS 0x1000 /* b12: complete-split status */ 374 - #define ATREPM 0x0400 /* b10: Auto repeat mode */ 375 - #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 376 - #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 377 - #define SQSET 0x0080 /* b7: Sequence toggle bit set */ 378 - #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 379 - #define PBUSY 0x0020 /* b5: pipe busy */ 380 - #define PID 0x0003 /* b1-0: Response PID */ 373 + #define BSTS 0x8000 /* b15: Buffer status */ 374 + #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ 375 + #define CSCLR 0x2000 /* b13: complete-split status clear */ 376 + #define CSSTS 0x1000 /* b12: complete-split status */ 377 + #define ATREPM 0x0400 /* b10: Auto repeat mode */ 378 + #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 379 + #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 380 + #define SQSET 0x0080 /* b7: Sequence toggle bit set */ 381 + #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 382 + #define PBUSY 0x0020 /* b5: pipe busy */ 383 + #define PID 0x0003 /* b1-0: Response PID */ 381 384 382 385 /* PIPExTRE */ 383 386 #define TRENB 0x0200 /* b9: Transaction counter enable */ ··· 404 407 #define make_devsel(addr) (addr << 12) 405 408 406 409 struct r8a66597_pipe_info { 407 - u16 pipenum; 408 - u16 address; /* R8A66597 HCD usb addres */ 409 - u16 epnum; 410 - u16 maxpacket; 411 - u16 type; 412 - u16 bufnum; 413 - u16 buf_bsize; 414 - u16 interval; 415 - u16 dir_in; 410 + u16 pipenum; 411 + u16 address; /* R8A66597 HCD usb addres */ 412 + u16 epnum; 413 + u16 maxpacket; 414 + u16 type; 415 + u16 bufnum; 416 + u16 buf_bsize; 417 + u16 interval; 418 + u16 dir_in; 416 419 }; 417 420 418 421 struct r8a66597_pipe {