tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net/mlx5: Kconfig, Better organize compilation flags
Always contain all acceleration functions declarations in
'accel' files, independent to the flags setting.
For this, introduce new flags CONFIG_FPGA_{IPSEC/TLS} and use stubs
where needed.
This obsoletes the need for stubs in 'fpga' files. Remove them.
Also use the new flags in Makefile, to decide whether to compile
TLS-specific or IPSEC-specific objects, or not.
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
authored by
Tariq Toukan
and committed by
David S. Miller
e2869fb2
c778dd31
+47
-93
+33
-10
drivers/net/ethernet/mellanox/mlx5/core/Kconfig
+33
-10
drivers/net/ethernet/mellanox/mlx5/core/Kconfig
···
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---help---
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MLX5 IPoIB offloads & acceleration support.
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config MLX5_FPGA_IPSEC
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bool "Mellanox Technologies IPsec Innova support"
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depends on MLX5_CORE
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depends on MLX5_FPGA
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default n
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help
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Build IPsec support for the Innova family of network cards by Mellanox
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+
Technologies. Innova network cards are comprised of a ConnectX chip
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and an FPGA chip on one board. If you select this option, the
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mlx5_core driver will include the Innova FPGA core and allow building
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sandbox-specific client drivers.
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+
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config MLX5_EN_IPSEC
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bool "IPSec XFRM cryptography-offload accelaration"
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-
depends on MLX5_ACCEL
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depends on MLX5_CORE_EN
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depends on XFRM_OFFLOAD
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depends on INET_ESP_OFFLOAD || INET6_ESP_OFFLOAD
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depends on MLX5_FPGA_IPSEC
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default n
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-
---help---
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help
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Build support for IPsec cryptography-offload accelaration in the NIC.
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Note: Support for hardware with this capability needs to be selected
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for this option to become available.
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config MLX5_FPGA_TLS
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bool "Mellanox Technologies TLS Innova support"
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depends on TLS_DEVICE
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depends on TLS=y || MLX5_CORE=m
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depends on MLX5_FPGA
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default n
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help
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Build TLS support for the Innova family of network cards by Mellanox
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+
Technologies. Innova network cards are comprised of a ConnectX chip
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and an FPGA chip on one board. If you select this option, the
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mlx5_core driver will include the Innova FPGA core and allow building
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sandbox-specific client drivers.
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config MLX5_EN_TLS
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bool "TLS cryptography-offload accelaration"
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depends on MLX5_CORE_EN
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-
depends on TLS_DEVICE
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-
depends on TLS=y || MLX5_CORE=m
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-
depends on MLX5_ACCEL
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-
default n
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---help---
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Build support for TLS cryptography-offload accelaration in the NIC.
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Note: Support for hardware with this capability needs to be selected
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-
for this option to become available.
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depends on MLX5_FPGA_TLS
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default y
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help
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Build support for TLS cryptography-offload accelaration in the NIC.
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Note: Support for hardware with this capability needs to be selected
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+
for this option to become available.
+4
-3
drivers/net/ethernet/mellanox/mlx5/core/Makefile
+4
-3
drivers/net/ethernet/mellanox/mlx5/core/Makefile
···
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#
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# Accelerations & FPGA
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#
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-
mlx5_core-$(CONFIG_MLX5_ACCEL) += accel/ipsec.o accel/tls.o
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mlx5_core-$(CONFIG_MLX5_FPGA_IPSEC) += fpga/ipsec.o
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mlx5_core-$(CONFIG_MLX5_FPGA_TLS) += fpga/tls.o
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mlx5_core-$(CONFIG_MLX5_ACCEL) += accel/tls.o accel/ipsec.o
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mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o fpga/sdk.o \
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fpga/ipsec.o fpga/tls.o
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mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o fpga/sdk.o
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mlx5_core-$(CONFIG_MLX5_EN_IPSEC) += en_accel/ipsec.o en_accel/ipsec_rxtx.o \
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en_accel/ipsec_stats.o
+4
drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c
+4
drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h
+3
drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c
+3
drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c
+1
-3
drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h
+1
-3
drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h
···
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#include <linux/mlx5/driver.h>
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#include <linux/tls.h>
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-
#ifdef CONFIG_MLX5_ACCEL
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-
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#ifdef CONFIG_MLX5_FPGA_TLS
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enum {
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MLX5_ACCEL_TLS_TX = BIT(0),
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MLX5_ACCEL_TLS_RX = BIT(1),
···
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static inline u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev) { return 0; }
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static inline int mlx5_accel_tls_init(struct mlx5_core_dev *mdev) { return 0; }
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static inline void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev) { }
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#endif
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#endif /* __MLX5_ACCEL_TLS_H__ */
-75
drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h
-75
drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h
···
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#include "accel/ipsec.h"
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#include "fs_cmd.h"
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#ifdef CONFIG_MLX5_FPGA
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u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev);
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unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev);
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int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
···
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const struct mlx5_flow_cmds *
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mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type);
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#else
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static inline u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
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{
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return 0;
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}
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static inline unsigned int
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mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev)
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{
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return 0;
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}
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static inline int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev,
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u64 *counters)
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{
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return 0;
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}
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static inline void *
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mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev,
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struct mlx5_accel_esp_xfrm *accel_xfrm,
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const __be32 saddr[4],
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const __be32 daddr[4],
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const __be32 spi, bool is_ipv6)
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{
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return NULL;
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}
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static inline void mlx5_fpga_ipsec_delete_sa_ctx(void *context)
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{
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}
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static inline int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev)
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{
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return 0;
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}
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static inline void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev)
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{
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}
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static inline void mlx5_fpga_ipsec_build_fs_cmds(void)
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{
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}
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static inline struct mlx5_accel_esp_xfrm *
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mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev,
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const struct mlx5_accel_esp_xfrm_attrs *attrs,
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u32 flags)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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static inline void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm)
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{
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}
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static inline int
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mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
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const struct mlx5_accel_esp_xfrm_attrs *attrs)
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{
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return -EOPNOTSUPP;
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}
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static inline const struct mlx5_flow_cmds *
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mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type)
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{
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return mlx5_fs_cmd_get_default(type);
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}
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#endif /* CONFIG_MLX5_FPGA */
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#endif /* __MLX5_FPGA_SADB_H__ */