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kernel
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linux
xen/PMU: Describe vendor-specific PMU registers
AMD and Intel PMU register initialization and helpers that determine
whether a register belongs to PMU.
This and some of subsequent PMU emulation code is somewhat similar to
Xen's PMU implementation.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: David Vrabel <david.vrabel@citrix.com>
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
authored by
Boris Ostrovsky
and committed by
David Vrabel
e27b72df
65d0cf0b
+152
-1
+152
-1
arch/x86/xen/pmu.c
+152
-1
arch/x86/xen/pmu.c
···
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static DEFINE_PER_CPU(struct xen_pmu_data *, xenpmu_shared);
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#define get_xenpmu_data() per_cpu(xenpmu_shared, smp_processor_id())
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/* AMD PMU */
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#define F15H_NUM_COUNTERS 6
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#define F10H_NUM_COUNTERS 4
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static __read_mostly uint32_t amd_counters_base;
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static __read_mostly uint32_t amd_ctrls_base;
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static __read_mostly int amd_msr_step;
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static __read_mostly int k7_counters_mirrored;
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static __read_mostly int amd_num_counters;
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/* Intel PMU */
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#define MSR_TYPE_COUNTER 0
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#define MSR_TYPE_CTRL 1
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#define MSR_TYPE_GLOBAL 2
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#define MSR_TYPE_ARCH_COUNTER 3
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#define MSR_TYPE_ARCH_CTRL 4
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/* Number of general pmu registers (CPUID.EAX[0xa].EAX[8..15]) */
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#define PMU_GENERAL_NR_SHIFT 8
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#define PMU_GENERAL_NR_BITS 8
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#define PMU_GENERAL_NR_MASK (((1 << PMU_GENERAL_NR_BITS) - 1) \
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<< PMU_GENERAL_NR_SHIFT)
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/* Number of fixed pmu registers (CPUID.EDX[0xa].EDX[0..4]) */
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#define PMU_FIXED_NR_SHIFT 0
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#define PMU_FIXED_NR_BITS 5
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#define PMU_FIXED_NR_MASK (((1 << PMU_FIXED_NR_BITS) - 1) \
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<< PMU_FIXED_NR_SHIFT)
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/* Alias registers (0x4c1) for full-width writes to PMCs */
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#define MSR_PMC_ALIAS_MASK (~(MSR_IA32_PERFCTR0 ^ MSR_IA32_PMC0))
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static __read_mostly int intel_num_arch_counters, intel_num_fixed_counters;
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static void xen_pmu_arch_init(void)
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{
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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switch (boot_cpu_data.x86) {
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case 0x15:
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amd_num_counters = F15H_NUM_COUNTERS;
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amd_counters_base = MSR_F15H_PERF_CTR;
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amd_ctrls_base = MSR_F15H_PERF_CTL;
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amd_msr_step = 2;
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k7_counters_mirrored = 1;
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break;
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case 0x10:
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case 0x12:
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case 0x14:
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case 0x16:
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default:
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amd_num_counters = F10H_NUM_COUNTERS;
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amd_counters_base = MSR_K7_PERFCTR0;
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amd_ctrls_base = MSR_K7_EVNTSEL0;
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amd_msr_step = 1;
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k7_counters_mirrored = 0;
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break;
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}
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} else {
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uint32_t eax, ebx, ecx, edx;
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cpuid(0xa, &eax, &ebx, &ecx, &edx);
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intel_num_arch_counters = (eax & PMU_GENERAL_NR_MASK) >>
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PMU_GENERAL_NR_SHIFT;
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intel_num_fixed_counters = (edx & PMU_FIXED_NR_MASK) >>
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PMU_FIXED_NR_SHIFT;
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}
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}
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static inline uint32_t get_fam15h_addr(u32 addr)
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{
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switch (addr) {
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case MSR_K7_PERFCTR0:
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case MSR_K7_PERFCTR1:
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case MSR_K7_PERFCTR2:
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case MSR_K7_PERFCTR3:
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return MSR_F15H_PERF_CTR + (addr - MSR_K7_PERFCTR0);
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case MSR_K7_EVNTSEL0:
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case MSR_K7_EVNTSEL1:
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case MSR_K7_EVNTSEL2:
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case MSR_K7_EVNTSEL3:
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return MSR_F15H_PERF_CTL + (addr - MSR_K7_EVNTSEL0);
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default:
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break;
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}
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return addr;
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}
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static inline bool is_amd_pmu_msr(unsigned int msr)
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{
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if ((msr >= MSR_F15H_PERF_CTL &&
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msr < MSR_F15H_PERF_CTR + (amd_num_counters * 2)) ||
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(msr >= MSR_K7_EVNTSEL0 &&
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msr < MSR_K7_PERFCTR0 + amd_num_counters))
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return true;
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return false;
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}
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static int is_intel_pmu_msr(u32 msr_index, int *type, int *index)
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{
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u32 msr_index_pmc;
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switch (msr_index) {
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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case MSR_IA32_DS_AREA:
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case MSR_IA32_PEBS_ENABLE:
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*type = MSR_TYPE_CTRL;
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return true;
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case MSR_CORE_PERF_GLOBAL_CTRL:
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case MSR_CORE_PERF_GLOBAL_STATUS:
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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*type = MSR_TYPE_GLOBAL;
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return true;
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default:
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if ((msr_index >= MSR_CORE_PERF_FIXED_CTR0) &&
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(msr_index < MSR_CORE_PERF_FIXED_CTR0 +
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intel_num_fixed_counters)) {
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*index = msr_index - MSR_CORE_PERF_FIXED_CTR0;
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*type = MSR_TYPE_COUNTER;
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return true;
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}
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if ((msr_index >= MSR_P6_EVNTSEL0) &&
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(msr_index < MSR_P6_EVNTSEL0 + intel_num_arch_counters)) {
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*index = msr_index - MSR_P6_EVNTSEL0;
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*type = MSR_TYPE_ARCH_CTRL;
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return true;
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}
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msr_index_pmc = msr_index & MSR_PMC_ALIAS_MASK;
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if ((msr_index_pmc >= MSR_IA32_PERFCTR0) &&
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(msr_index_pmc < MSR_IA32_PERFCTR0 +
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intel_num_arch_counters)) {
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*type = MSR_TYPE_ARCH_COUNTER;
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*index = msr_index_pmc - MSR_IA32_PERFCTR0;
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return true;
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}
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return false;
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}
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}
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/* perf callbacks */
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static int xen_is_in_guest(void)
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{
···
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per_cpu(xenpmu_shared, cpu) = xenpmu_data;
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-
if (cpu == 0)
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if (cpu == 0) {
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perf_register_guest_info_callbacks(&xen_guest_cbs);
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xen_pmu_arch_init();
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}
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return;
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