Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu/discovery: move all table parsing into amdgpu_discovery.c

This data has no dependencies, so encapsulate it all within
amdgpu_discovery.c.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

+14 -38
+1 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 1926 1926 adev->firmware.gpu_info_fw = NULL; 1927 1927 1928 1928 if (adev->mman.discovery_bin) { 1929 - amdgpu_discovery_get_gfx_info(adev); 1930 - 1931 1929 /* 1932 1930 * FIXME: The bounding box is still needed by Navi12, so 1933 - * temporarily read it from gpu_info firmware. Should be droped 1931 + * temporarily read it from gpu_info firmware. Should be dropped 1934 1932 * when DAL no longer needs it. 1935 1933 */ 1936 1934 if (adev->asic_type != CHIP_NAVI12)
+13 -16
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
··· 1046 1046 1047 1047 /* ================================================== */ 1048 1048 1049 - int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1049 + static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1050 1050 { 1051 1051 struct binary_header *bhdr; 1052 1052 struct ip_discovery_header *ihdr; ··· 1212 1212 return -EINVAL; 1213 1213 } 1214 1214 1215 - void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1215 + static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1216 1216 { 1217 1217 int vcn_harvest_count = 0; 1218 1218 int umc_harvest_count = 0; ··· 1257 1257 struct gc_info_v2_0 v2; 1258 1258 }; 1259 1259 1260 - int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1260 + static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1261 1261 { 1262 1262 struct binary_header *bhdr; 1263 1263 union gc_info *gc_info; ··· 1271 1271 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1272 1272 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1273 1273 1274 - if (!offset) { 1275 - dev_err(adev->dev, "invalid GC table offset\n"); 1276 - return -EINVAL; 1277 - } 1274 + if (!offset) 1275 + return 0; 1278 1276 1279 1277 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1280 1278 ··· 1361 1363 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1362 1364 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1363 1365 1364 - if (!offset) { 1365 - dev_err(adev->dev, "invalid mall table offset\n"); 1366 - return -EINVAL; 1367 - } 1366 + if (!offset) 1367 + return 0; 1368 1368 1369 1369 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1370 1370 ··· 1396 1400 struct vcn_info_v1_0 v1; 1397 1401 }; 1398 1402 1399 - int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1403 + static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1400 1404 { 1401 1405 struct binary_header *bhdr; 1402 1406 union vcn_info *vcn_info; ··· 1416 1420 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1417 1421 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1418 1422 1419 - if (!offset) { 1420 - dev_err(adev->dev, "invalid vcn table offset\n"); 1421 - return -EINVAL; 1422 - } 1423 + if (!offset) 1424 + return 0; 1423 1425 1424 1426 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1425 1427 ··· 2031 2037 return -EINVAL; 2032 2038 2033 2039 amdgpu_discovery_harvest_ip(adev); 2040 + amdgpu_discovery_get_gfx_info(adev); 2041 + amdgpu_discovery_get_mall_info(adev); 2042 + amdgpu_discovery_get_vcn_info(adev); 2034 2043 break; 2035 2044 } 2036 2045
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
··· 28 28 #define DISCOVERY_TMR_OFFSET (64 << 10) 29 29 30 30 void amdgpu_discovery_fini(struct amdgpu_device *adev); 31 - int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev); 32 - void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev); 33 31 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 34 32 int *major, int *minor, int *revision); 35 - 36 - int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev); 37 - int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev); 38 - int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev); 39 33 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev); 40 34 41 35 #endif /* __AMDGPU_DISCOVERY__ */
-13
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 701 701 702 702 static void soc15_reg_base_init(struct amdgpu_device *adev) 703 703 { 704 - int r; 705 - 706 704 /* Set IP register base before any HW register access */ 707 705 switch (adev->asic_type) { 708 706 case CHIP_VEGA10: 709 707 case CHIP_VEGA12: 710 708 case CHIP_RAVEN: 711 - vega10_reg_base_init(adev); 712 - break; 713 709 case CHIP_RENOIR: 714 - /* It's safe to do ip discovery here for Renoir, 715 - * it doesn't support SRIOV. */ 716 - if (amdgpu_discovery) { 717 - r = amdgpu_discovery_reg_base_init(adev); 718 - if (r == 0) 719 - break; 720 - DRM_WARN("failed to init reg base from ip discovery table, " 721 - "fallback to legacy init method\n"); 722 - } 723 710 vega10_reg_base_init(adev); 724 711 break; 725 712 case CHIP_VEGA20: