tjh.dev / kernel
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sh: Kill off MAX_DMA_ADDRESS leftovers.

We don't support the ISA DMA API, so this is only ever misused. The
dma-sh case inadvertently broke the dreamcast case by testing the wrong
variable for the total number of channels, so this fixes that up too.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Paul Mundt e24cca19 2ff9f317

+9 -36
-17
arch/sh/drivers/dma/Kconfig
··· 40 40 DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the 41 41 SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6. 42 42 43 - config NR_DMA_CHANNELS_BOOL 44 - depends on SH_DMA 45 - bool "Override default number of maximum DMA channels" 46 - help 47 - This allows you to forcibly update the maximum number of supported 48 - DMA channels for a given board. If this is unset, this will default 49 - to the number of channels that the on-chip DMAC has. 50 - 51 - config NR_DMA_CHANNELS 52 - int "Maximum number of DMA channels" 53 - depends on SH_DMA && NR_DMA_CHANNELS_BOOL 54 - default NR_ONCHIP_DMA_CHANNELS 55 - help 56 - This allows you to specify the maximum number of DMA channels to 57 - support. Setting this to a higher value allows for cascading DMACs 58 - with additional channels. 59 - 60 43 config SH_DMABRG 61 44 bool "SH7760 DMABRG support" 62 45 depends on CPU_SUBTYPE_SH7760
+1 -1
arch/sh/drivers/dma/dma-sysfs.c
··· 29 29 ssize_t len = 0; 30 30 int i; 31 31 32 - for (i = 0; i < MAX_DMA_CHANNELS; i++) { 32 + for (i = 0; i < 16; i++) { 33 33 struct dma_info *info = get_dma_info(i); 34 34 struct dma_channel *channel = get_dma_channel(i); 35 35
+8 -8
arch/sh/include/asm/dma-sh.h
··· 32 32 #endif 33 33 34 34 static int dmte_irq_map[] __maybe_unused = { 35 - #if (MAX_DMA_CHANNELS >= 4) 35 + #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4) 36 36 DMTE0_IRQ, 37 37 DMTE0_IRQ + 1, 38 38 DMTE0_IRQ + 2, 39 39 DMTE0_IRQ + 3, 40 40 #endif 41 - #if (MAX_DMA_CHANNELS >= 6) 41 + #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6) 42 42 DMTE4_IRQ, 43 43 DMTE4_IRQ + 1, 44 44 #endif 45 - #if (MAX_DMA_CHANNELS >= 8) 45 + #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8) 46 46 DMTE6_IRQ, 47 47 DMTE6_IRQ + 1, 48 48 #endif 49 - #if (MAX_DMA_CHANNELS >= 12) 49 + #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12) 50 50 DMTE8_IRQ, 51 51 DMTE9_IRQ, 52 52 DMTE10_IRQ, ··· 62 62 63 63 /* DMA base address */ 64 64 static u32 dma_base_addr[] __maybe_unused = { 65 - #if (MAX_DMA_CHANNELS >= 4) 65 + #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4) 66 66 SH_DMAC_BASE0 + 0x00, /* channel 0 */ 67 67 SH_DMAC_BASE0 + 0x10, 68 68 SH_DMAC_BASE0 + 0x20, 69 69 SH_DMAC_BASE0 + 0x30, 70 70 #endif 71 - #if (MAX_DMA_CHANNELS >= 6) 71 + #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6) 72 72 SH_DMAC_BASE0 + 0x50, 73 73 SH_DMAC_BASE0 + 0x60, 74 74 #endif 75 - #if (MAX_DMA_CHANNELS >= 8) 75 + #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8) 76 76 SH_DMAC_BASE1 + 0x00, 77 77 SH_DMAC_BASE1 + 0x10, 78 78 #endif 79 - #if (MAX_DMA_CHANNELS >= 12) 79 + #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12) 80 80 SH_DMAC_BASE1 + 0x20, 81 81 SH_DMAC_BASE1 + 0x30, 82 82 SH_DMAC_BASE1 + 0x50,
-8
arch/sh/include/asm/dma.h
··· 17 17 #include <linux/device.h> 18 18 #include <asm-generic/dma.h> 19 19 20 - #ifdef CONFIG_NR_DMA_CHANNELS 21 - # define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) 22 - #elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS) 23 - # define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) 24 - #else 25 - # define MAX_DMA_CHANNELS 0 26 - #endif 27 - 28 20 /* 29 21 * Read and write modes can mean drastically different things depending on the 30 22 * channel configuration. Consult your DMAC documentation and module
-2
arch/sh/include/mach-dreamcast/mach/dma.h
··· 11 11 #define __ASM_SH_DREAMCAST_DMA_H 12 12 13 13 /* Number of DMA channels */ 14 - #define ONCHIP_NR_DMA_CHANNELS 4 15 14 #define G2_NR_DMA_CHANNELS 4 16 - #define PVR2_NR_DMA_CHANNELS 1 17 15 18 16 /* Channels for cascading */ 19 17 #define PVR2_CASCADE_CHAN 2