Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'samsung-dt-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Pull "Samsung DTS ARM changes for v4.17" from Krzysztof Kozłowski:

1. Add WiFi to Artik 5 board.
2. Remove unused samsung_k3pe0e000b memory DTSI.
3. Add few remaining SPDX license identifiers.
4. Refactor Exynos4 by using labels for overriding/extending nodes and
moving respective nodes under the 'soc' node.
5. Add three new Exynos4412-based boards: GT-I9300 (Samsung Galaxy S3),
GT-I9305 (Samsung Galaxy S3 LTE) and GT-N7100/N7105 (Samsung Note 2).
They are based heavily on existing Trats2 board.
6. Fix PMIC interrupts on Trats board.
7. Fix IOMMU for GScaler devices on Exynos5250.
8. Minor fixes in unit addresses pointed by DTC.
9. Minor cleanups from unused properties and duplicated code.

* tag 'samsung-dt-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (29 commits)
ARM: dts: exynos: Fix IOMMU support for GScaler devices on Exynos5250
ARM: dts: exynos: Remove unused bypass-smu property from Xyref5260
ARM: dts: exynos: Add missing interrupts property to PMIC on Trats board
ARM: dts: exynos: Fix unit addresses of PDMA nodes in Exynos5410
ARM: dts: exynos: Fix address of PPMU ACP on Exynos4210
ARM: dts: exynos: Cleanup power domain nodes in exynos3250.dtsi
ARM: dts: exynos: Add touchscreen node to Exynos4412 N710x
ARM: dts: exynos: Add Samsung's Exynos4412-based Midas boards
ARM: dts: exynos: Split Trats2 DTS in preparation for Midas boards
ARM: dts: exynos: Remove "cooling-{min|max}-level" for CPU nodes
dt-bindings: samsung: Document bindings for Midas family boards
ARM: dts: exynos: Add soc node to exynos4412
ARM: dts: exynos: Add soc node to exynos4210
ARM: dts: exynos: Add soc node to exynos4
ARM: dts: exynos: Add soc node to exynos5440
ARM: dts: exynos: Use pmu label in exynos4412
ARM: dts: exynos: Remove duplicated inclusion of syscon restart nodes on Exynos5410
ARM: dts: exynos: Use label instead of full path in exynos4412-itop-elite
ARM: dts: exynos: Use labels instead of full paths in exynos4412-trats2
ARM: dts: exynos: Use label instead of full path in exynos4412-odroid-common
...

+5523 -5388
+4
Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
··· 9 9 - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board. 10 10 - "samsung,trats" - for Exynos4210-based Tizen Reference board. 11 11 - "samsung,universal_c210" - for Exynos4210-based Samsung board. 12 + - "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board. 13 + - "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board. 14 + - "samsung,midas" - for Exynos4412-based Samsung Midas board. 12 15 - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board. 16 + - "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board. 13 17 - "samsung,trats2" - for Exynos4412-based Tizen Reference board. 14 18 - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board. 15 19 - "samsung,xyref5260" - for Exynos5260-based Samsung board.
-1
MAINTAINERS
··· 1863 1863 S: Maintained 1864 1864 F: arch/arm/boot/dts/s3c* 1865 1865 F: arch/arm/boot/dts/s5p* 1866 - F: arch/arm/boot/dts/samsung* 1867 1866 F: arch/arm/boot/dts/exynos* 1868 1867 F: arch/arm64/boot/dts/exynos/ 1869 1868 F: arch/arm/plat-samsung/
+3
arch/arm/boot/dts/Makefile
··· 163 163 exynos4210-smdkv310.dtb \ 164 164 exynos4210-trats.dtb \ 165 165 exynos4210-universal_c210.dtb \ 166 + exynos4412-i9300.dtb \ 167 + exynos4412-i9305.dtb \ 166 168 exynos4412-itop-elite.dtb \ 169 + exynos4412-n710x.dtb \ 167 170 exynos4412-odroidu3.dtb \ 168 171 exynos4412-odroidx.dtb \ 169 172 exynos4412-odroidx2.dtb \
+1 -4
arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition. 3 4 * 4 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd 5 - * 6 - * This program is free software; you can redistribute it and/or modify 7 - * it under the terms of the GNU General Public License version 2 as 8 - * published by the Free Software Foundation. 9 6 */ 10 7 11 8 / {
+1 -4
arch/arm/boot/dts/exynos-syscon-restart.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition. 3 - * 4 - * This program is free software; you can redistribute it and/or modify 5 - * it under the terms of the GNU General Public License version 2 as 6 - * published by the Free Software Foundation. 7 4 */ 8 5 9 6 / {
+36
arch/arm/boot/dts/exynos3250-artik5.dtsi
··· 245 245 regulator-name = "VLDO23_1.8V"; 246 246 regulator-min-microvolt = <1800000>; 247 247 regulator-max-microvolt = <1800000>; 248 + regulator-always-on; 248 249 }; 249 250 250 251 ldo24_reg: LDO24 { ··· 315 314 pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; 316 315 bus-width = <8>; 317 316 status = "okay"; 317 + }; 318 + 319 + &mshc_1 { 320 + cap-sd-highspeed; 321 + cap-sdio-irq; 322 + disable-wp; 323 + non-removable; 324 + keep-power-in-suspend; 325 + fifo-depth = <0x40>; 326 + vqmmc-supply = <&ldo11_reg>; 327 + /* 328 + * Voltage negotiation is broken for the SDIO periph so we 329 + * can't actually set the voltage here. 330 + * vmmc-supply = <&ldo23_reg>; 331 + */ 332 + card-detect-delay = <500>; 333 + clock-frequency = <100000000>; 334 + max-frequency = <100000000>; 335 + samsung,dw-mshc-ciu-div = <3>; 336 + samsung,dw-mshc-sdr-timing = <0 1>; 337 + samsung,dw-mshc-ddr-timing = <1 2>; 338 + pinctrl-names = "default"; 339 + pinctrl-0 = <&sd1_cmd &sd1_clk &sd1_bus1 &sd1_bus4 &wlanen>; 340 + bus-width = <4>; 341 + status = "okay"; 342 + }; 343 + 344 + &pinctrl_1 { 345 + wlanen: wlanen { 346 + samsung,pins = "gpx2-3"; 347 + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; 348 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 349 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV3>; 350 + samsung,pin-val = <1>; 351 + }; 318 352 }; 319 353 320 354 &rtc {
+10 -5
arch/arm/boot/dts/exynos3250.dtsi
··· 161 161 syscon = <&pmu_system_controller>; 162 162 }; 163 163 164 - pd_cam: cam-power-domain@10023c00 { 164 + pd_cam: power-domain@10023c00 { 165 165 compatible = "samsung,exynos4210-pd"; 166 166 reg = <0x10023C00 0x20>; 167 167 #power-domain-cells = <0>; 168 + label = "CAM"; 168 169 }; 169 170 170 - pd_mfc: mfc-power-domain@10023c40 { 171 + pd_mfc: power-domain@10023c40 { 171 172 compatible = "samsung,exynos4210-pd"; 172 173 reg = <0x10023C40 0x20>; 173 174 #power-domain-cells = <0>; 175 + label = "MFC"; 174 176 }; 175 177 176 - pd_g3d: g3d-power-domain@10023c60 { 178 + pd_g3d: power-domain@10023c60 { 177 179 compatible = "samsung,exynos4210-pd"; 178 180 reg = <0x10023C60 0x20>; 179 181 #power-domain-cells = <0>; 182 + label = "G3D"; 180 183 }; 181 184 182 - pd_lcd0: lcd0-power-domain@10023c80 { 185 + pd_lcd0: power-domain@10023c80 { 183 186 compatible = "samsung,exynos4210-pd"; 184 187 reg = <0x10023C80 0x20>; 185 188 #power-domain-cells = <0>; 189 + label = "LCD0"; 186 190 }; 187 191 188 - pd_isp: isp-power-domain@10023ca0 { 192 + pd_isp: power-domain@10023ca0 { 189 193 compatible = "samsung,exynos4210-pd"; 190 194 reg = <0x10023CA0 0x20>; 191 195 #power-domain-cells = <0>; 196 + label = "ISP"; 192 197 }; 193 198 194 199 cmu: clock-controller@10030000 {
+930 -915
arch/arm/boot/dts/exynos4.dtsi
··· 52 52 serial3 = &serial_3; 53 53 }; 54 54 55 - clock_audss: clock-controller@3810000 { 56 - compatible = "samsung,exynos4210-audss-clock"; 57 - reg = <0x03810000 0x0C>; 58 - #clock-cells = <1>; 59 - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 60 - <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>; 61 - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 62 - }; 63 - 64 - i2s0: i2s@3830000 { 65 - compatible = "samsung,s5pv210-i2s"; 66 - reg = <0x03830000 0x100>; 67 - clocks = <&clock_audss EXYNOS_I2S_BUS>, 68 - <&clock_audss EXYNOS_DOUT_AUD_BUS>, 69 - <&clock_audss EXYNOS_SCLK_I2S>; 70 - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 71 - #clock-cells = <1>; 72 - clock-output-names = "i2s_cdclk0"; 73 - dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; 74 - dma-names = "tx", "rx", "tx-sec"; 75 - samsung,idma-addr = <0x03000000>; 76 - #sound-dai-cells = <1>; 77 - status = "disabled"; 78 - }; 79 - 80 - chipid@10000000 { 81 - compatible = "samsung,exynos4210-chipid"; 82 - reg = <0x10000000 0x100>; 83 - }; 84 - 85 - scu: snoop-control-unit@10500000 { 86 - compatible = "arm,cortex-a9-scu"; 87 - reg = <0x10500000 0x2000>; 88 - }; 89 - 90 - memory-controller@12570000 { 91 - compatible = "samsung,exynos4210-srom"; 92 - reg = <0x12570000 0x14>; 93 - }; 94 - 95 - mipi_phy: video-phy { 96 - compatible = "samsung,s5pv210-mipi-video-phy"; 97 - #phy-cells = <1>; 98 - syscon = <&pmu_system_controller>; 99 - }; 100 - 101 - pd_mfc: mfc-power-domain@10023c40 { 102 - compatible = "samsung,exynos4210-pd"; 103 - reg = <0x10023C40 0x20>; 104 - #power-domain-cells = <0>; 105 - label = "MFC"; 106 - }; 107 - 108 - pd_g3d: g3d-power-domain@10023c60 { 109 - compatible = "samsung,exynos4210-pd"; 110 - reg = <0x10023C60 0x20>; 111 - #power-domain-cells = <0>; 112 - label = "G3D"; 113 - }; 114 - 115 - pd_lcd0: lcd0-power-domain@10023c80 { 116 - compatible = "samsung,exynos4210-pd"; 117 - reg = <0x10023C80 0x20>; 118 - #power-domain-cells = <0>; 119 - label = "LCD0"; 120 - }; 121 - 122 - pd_tv: tv-power-domain@10023c20 { 123 - compatible = "samsung,exynos4210-pd"; 124 - reg = <0x10023C20 0x20>; 125 - #power-domain-cells = <0>; 126 - power-domains = <&pd_lcd0>; 127 - label = "TV"; 128 - }; 129 - 130 - pd_cam: cam-power-domain@10023c00 { 131 - compatible = "samsung,exynos4210-pd"; 132 - reg = <0x10023C00 0x20>; 133 - #power-domain-cells = <0>; 134 - label = "CAM"; 135 - }; 136 - 137 - pd_gps: gps-power-domain@10023ce0 { 138 - compatible = "samsung,exynos4210-pd"; 139 - reg = <0x10023CE0 0x20>; 140 - #power-domain-cells = <0>; 141 - label = "GPS"; 142 - }; 143 - 144 - pd_gps_alive: gps-alive-power-domain@10023d00 { 145 - compatible = "samsung,exynos4210-pd"; 146 - reg = <0x10023D00 0x20>; 147 - #power-domain-cells = <0>; 148 - label = "GPS alive"; 149 - }; 150 - 151 - gic: interrupt-controller@10490000 { 152 - compatible = "arm,cortex-a9-gic"; 153 - #interrupt-cells = <3>; 154 - interrupt-controller; 155 - reg = <0x10490000 0x10000>, <0x10480000 0x10000>; 156 - }; 157 - 158 - combiner: interrupt-controller@10440000 { 159 - compatible = "samsung,exynos4210-combiner"; 160 - #interrupt-cells = <2>; 161 - interrupt-controller; 162 - reg = <0x10440000 0x1000>; 163 - }; 164 - 165 - pmu { 166 - compatible = "arm,cortex-a9-pmu"; 167 - interrupt-parent = <&combiner>; 168 - interrupts = <2 2>, <3 2>; 169 - }; 170 - 171 - sys_reg: syscon@10010000 { 172 - compatible = "samsung,exynos4-sysreg", "syscon"; 173 - reg = <0x10010000 0x400>; 174 - }; 175 - 176 - pmu_system_controller: system-controller@10020000 { 177 - compatible = "samsung,exynos4210-pmu", "syscon"; 178 - reg = <0x10020000 0x4000>; 179 - interrupt-controller; 180 - #interrupt-cells = <3>; 181 - interrupt-parent = <&gic>; 182 - }; 183 - 184 - dsi_0: dsi@11c80000 { 185 - compatible = "samsung,exynos4210-mipi-dsi"; 186 - reg = <0x11C80000 0x10000>; 187 - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 188 - power-domains = <&pd_lcd0>; 189 - phys = <&mipi_phy 1>; 190 - phy-names = "dsim"; 191 - clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; 192 - clock-names = "bus_clk", "sclk_mipi"; 193 - status = "disabled"; 194 - #address-cells = <1>; 195 - #size-cells = <0>; 196 - }; 197 - 198 - camera { 199 - compatible = "samsung,fimc", "simple-bus"; 200 - status = "disabled"; 201 - #address-cells = <1>; 202 - #size-cells = <1>; 203 - #clock-cells = <1>; 204 - clock-output-names = "cam_a_clkout", "cam_b_clkout"; 205 - ranges; 206 - 207 - fimc_0: fimc@11800000 { 208 - compatible = "samsung,exynos4210-fimc"; 209 - reg = <0x11800000 0x1000>; 210 - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 211 - clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; 212 - clock-names = "fimc", "sclk_fimc"; 213 - power-domains = <&pd_cam>; 214 - samsung,sysreg = <&sys_reg>; 215 - iommus = <&sysmmu_fimc0>; 216 - status = "disabled"; 217 - }; 218 - 219 - fimc_1: fimc@11810000 { 220 - compatible = "samsung,exynos4210-fimc"; 221 - reg = <0x11810000 0x1000>; 222 - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 223 - clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; 224 - clock-names = "fimc", "sclk_fimc"; 225 - power-domains = <&pd_cam>; 226 - samsung,sysreg = <&sys_reg>; 227 - iommus = <&sysmmu_fimc1>; 228 - status = "disabled"; 229 - }; 230 - 231 - fimc_2: fimc@11820000 { 232 - compatible = "samsung,exynos4210-fimc"; 233 - reg = <0x11820000 0x1000>; 234 - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 235 - clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; 236 - clock-names = "fimc", "sclk_fimc"; 237 - power-domains = <&pd_cam>; 238 - samsung,sysreg = <&sys_reg>; 239 - iommus = <&sysmmu_fimc2>; 240 - status = "disabled"; 241 - }; 242 - 243 - fimc_3: fimc@11830000 { 244 - compatible = "samsung,exynos4210-fimc"; 245 - reg = <0x11830000 0x1000>; 246 - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 247 - clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; 248 - clock-names = "fimc", "sclk_fimc"; 249 - power-domains = <&pd_cam>; 250 - samsung,sysreg = <&sys_reg>; 251 - iommus = <&sysmmu_fimc3>; 252 - status = "disabled"; 253 - }; 254 - 255 - csis_0: csis@11880000 { 256 - compatible = "samsung,exynos4210-csis"; 257 - reg = <0x11880000 0x4000>; 258 - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 259 - clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; 260 - clock-names = "csis", "sclk_csis"; 261 - bus-width = <4>; 262 - power-domains = <&pd_cam>; 263 - phys = <&mipi_phy 0>; 264 - phy-names = "csis"; 265 - status = "disabled"; 266 - #address-cells = <1>; 267 - #size-cells = <0>; 268 - }; 269 - 270 - csis_1: csis@11890000 { 271 - compatible = "samsung,exynos4210-csis"; 272 - reg = <0x11890000 0x4000>; 273 - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 274 - clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; 275 - clock-names = "csis", "sclk_csis"; 276 - bus-width = <2>; 277 - power-domains = <&pd_cam>; 278 - phys = <&mipi_phy 2>; 279 - phy-names = "csis"; 280 - status = "disabled"; 281 - #address-cells = <1>; 282 - #size-cells = <0>; 283 - }; 284 - }; 285 - 286 - rtc: rtc@10070000 { 287 - compatible = "samsung,s3c6410-rtc"; 288 - reg = <0x10070000 0x100>; 289 - interrupt-parent = <&pmu_system_controller>; 290 - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 291 - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 292 - clocks = <&clock CLK_RTC>; 293 - clock-names = "rtc"; 294 - status = "disabled"; 295 - }; 296 - 297 - keypad: keypad@100a0000 { 298 - compatible = "samsung,s5pv210-keypad"; 299 - reg = <0x100A0000 0x100>; 300 - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 301 - clocks = <&clock CLK_KEYIF>; 302 - clock-names = "keypad"; 303 - status = "disabled"; 304 - }; 305 - 306 - sdhci_0: sdhci@12510000 { 307 - compatible = "samsung,exynos4210-sdhci"; 308 - reg = <0x12510000 0x100>; 309 - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 310 - clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 311 - clock-names = "hsmmc", "mmc_busclk.2"; 312 - status = "disabled"; 313 - }; 314 - 315 - sdhci_1: sdhci@12520000 { 316 - compatible = "samsung,exynos4210-sdhci"; 317 - reg = <0x12520000 0x100>; 318 - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 319 - clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 320 - clock-names = "hsmmc", "mmc_busclk.2"; 321 - status = "disabled"; 322 - }; 323 - 324 - sdhci_2: sdhci@12530000 { 325 - compatible = "samsung,exynos4210-sdhci"; 326 - reg = <0x12530000 0x100>; 327 - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 328 - clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 329 - clock-names = "hsmmc", "mmc_busclk.2"; 330 - status = "disabled"; 331 - }; 332 - 333 - sdhci_3: sdhci@12540000 { 334 - compatible = "samsung,exynos4210-sdhci"; 335 - reg = <0x12540000 0x100>; 336 - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 337 - clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 338 - clock-names = "hsmmc", "mmc_busclk.2"; 339 - status = "disabled"; 340 - }; 341 - 342 - exynos_usbphy: exynos-usbphy@125b0000 { 343 - compatible = "samsung,exynos4210-usb2-phy"; 344 - reg = <0x125B0000 0x100>; 345 - samsung,pmureg-phandle = <&pmu_system_controller>; 346 - clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; 347 - clock-names = "phy", "ref"; 348 - #phy-cells = <1>; 349 - status = "disabled"; 350 - }; 351 - 352 - hsotg: hsotg@12480000 { 353 - compatible = "samsung,s3c6400-hsotg"; 354 - reg = <0x12480000 0x20000>; 355 - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 356 - clocks = <&clock CLK_USB_DEVICE>; 357 - clock-names = "otg"; 358 - phys = <&exynos_usbphy 0>; 359 - phy-names = "usb2-phy"; 360 - status = "disabled"; 361 - }; 362 - 363 - ehci: ehci@12580000 { 364 - compatible = "samsung,exynos4210-ehci"; 365 - reg = <0x12580000 0x100>; 366 - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 367 - clocks = <&clock CLK_USB_HOST>; 368 - clock-names = "usbhost"; 369 - status = "disabled"; 370 - #address-cells = <1>; 371 - #size-cells = <0>; 372 - port@0 { 373 - reg = <0>; 374 - phys = <&exynos_usbphy 1>; 375 - status = "disabled"; 376 - }; 377 - port@1 { 378 - reg = <1>; 379 - phys = <&exynos_usbphy 2>; 380 - status = "disabled"; 381 - }; 382 - port@2 { 383 - reg = <2>; 384 - phys = <&exynos_usbphy 3>; 385 - status = "disabled"; 386 - }; 387 - }; 388 - 389 - ohci: ohci@12590000 { 390 - compatible = "samsung,exynos4210-ohci"; 391 - reg = <0x12590000 0x100>; 392 - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 393 - clocks = <&clock CLK_USB_HOST>; 394 - clock-names = "usbhost"; 395 - status = "disabled"; 396 - #address-cells = <1>; 397 - #size-cells = <0>; 398 - port@0 { 399 - reg = <0>; 400 - phys = <&exynos_usbphy 1>; 401 - status = "disabled"; 402 - }; 403 - }; 404 - 405 - i2s1: i2s@13960000 { 406 - compatible = "samsung,s3c6410-i2s"; 407 - reg = <0x13960000 0x100>; 408 - clocks = <&clock CLK_I2S1>; 409 - clock-names = "iis"; 410 - #clock-cells = <1>; 411 - clock-output-names = "i2s_cdclk1"; 412 - dmas = <&pdma1 12>, <&pdma1 11>; 413 - dma-names = "tx", "rx"; 414 - #sound-dai-cells = <1>; 415 - status = "disabled"; 416 - }; 417 - 418 - i2s2: i2s@13970000 { 419 - compatible = "samsung,s3c6410-i2s"; 420 - reg = <0x13970000 0x100>; 421 - clocks = <&clock CLK_I2S2>; 422 - clock-names = "iis"; 423 - #clock-cells = <1>; 424 - clock-output-names = "i2s_cdclk2"; 425 - dmas = <&pdma0 14>, <&pdma0 13>; 426 - dma-names = "tx", "rx"; 427 - #sound-dai-cells = <1>; 428 - status = "disabled"; 429 - }; 430 - 431 - mfc: codec@13400000 { 432 - compatible = "samsung,mfc-v5"; 433 - reg = <0x13400000 0x10000>; 434 - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 435 - power-domains = <&pd_mfc>; 436 - clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; 437 - clock-names = "mfc", "sclk_mfc"; 438 - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 439 - iommu-names = "left", "right"; 440 - }; 441 - 442 - serial_0: serial@13800000 { 443 - compatible = "samsung,exynos4210-uart"; 444 - reg = <0x13800000 0x100>; 445 - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 446 - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 447 - clock-names = "uart", "clk_uart_baud0"; 448 - dmas = <&pdma0 15>, <&pdma0 16>; 449 - dma-names = "rx", "tx"; 450 - status = "disabled"; 451 - }; 452 - 453 - serial_1: serial@13810000 { 454 - compatible = "samsung,exynos4210-uart"; 455 - reg = <0x13810000 0x100>; 456 - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 457 - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 458 - clock-names = "uart", "clk_uart_baud0"; 459 - dmas = <&pdma1 15>, <&pdma1 16>; 460 - dma-names = "rx", "tx"; 461 - status = "disabled"; 462 - }; 463 - 464 - serial_2: serial@13820000 { 465 - compatible = "samsung,exynos4210-uart"; 466 - reg = <0x13820000 0x100>; 467 - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 468 - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 469 - clock-names = "uart", "clk_uart_baud0"; 470 - dmas = <&pdma0 17>, <&pdma0 18>; 471 - dma-names = "rx", "tx"; 472 - status = "disabled"; 473 - }; 474 - 475 - serial_3: serial@13830000 { 476 - compatible = "samsung,exynos4210-uart"; 477 - reg = <0x13830000 0x100>; 478 - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 479 - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 480 - clock-names = "uart", "clk_uart_baud0"; 481 - dmas = <&pdma1 17>, <&pdma1 18>; 482 - dma-names = "rx", "tx"; 483 - status = "disabled"; 484 - }; 485 - 486 - i2c_0: i2c@13860000 { 487 - #address-cells = <1>; 488 - #size-cells = <0>; 489 - compatible = "samsung,s3c2440-i2c"; 490 - reg = <0x13860000 0x100>; 491 - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 492 - clocks = <&clock CLK_I2C0>; 493 - clock-names = "i2c"; 494 - pinctrl-names = "default"; 495 - pinctrl-0 = <&i2c0_bus>; 496 - status = "disabled"; 497 - }; 498 - 499 - i2c_1: i2c@13870000 { 500 - #address-cells = <1>; 501 - #size-cells = <0>; 502 - compatible = "samsung,s3c2440-i2c"; 503 - reg = <0x13870000 0x100>; 504 - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 505 - clocks = <&clock CLK_I2C1>; 506 - clock-names = "i2c"; 507 - pinctrl-names = "default"; 508 - pinctrl-0 = <&i2c1_bus>; 509 - status = "disabled"; 510 - }; 511 - 512 - i2c_2: i2c@13880000 { 513 - #address-cells = <1>; 514 - #size-cells = <0>; 515 - compatible = "samsung,s3c2440-i2c"; 516 - reg = <0x13880000 0x100>; 517 - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 518 - clocks = <&clock CLK_I2C2>; 519 - clock-names = "i2c"; 520 - pinctrl-names = "default"; 521 - pinctrl-0 = <&i2c2_bus>; 522 - status = "disabled"; 523 - }; 524 - 525 - i2c_3: i2c@13890000 { 526 - #address-cells = <1>; 527 - #size-cells = <0>; 528 - compatible = "samsung,s3c2440-i2c"; 529 - reg = <0x13890000 0x100>; 530 - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 531 - clocks = <&clock CLK_I2C3>; 532 - clock-names = "i2c"; 533 - pinctrl-names = "default"; 534 - pinctrl-0 = <&i2c3_bus>; 535 - status = "disabled"; 536 - }; 537 - 538 - i2c_4: i2c@138a0000 { 539 - #address-cells = <1>; 540 - #size-cells = <0>; 541 - compatible = "samsung,s3c2440-i2c"; 542 - reg = <0x138A0000 0x100>; 543 - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 544 - clocks = <&clock CLK_I2C4>; 545 - clock-names = "i2c"; 546 - pinctrl-names = "default"; 547 - pinctrl-0 = <&i2c4_bus>; 548 - status = "disabled"; 549 - }; 550 - 551 - i2c_5: i2c@138b0000 { 552 - #address-cells = <1>; 553 - #size-cells = <0>; 554 - compatible = "samsung,s3c2440-i2c"; 555 - reg = <0x138B0000 0x100>; 556 - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 557 - clocks = <&clock CLK_I2C5>; 558 - clock-names = "i2c"; 559 - pinctrl-names = "default"; 560 - pinctrl-0 = <&i2c5_bus>; 561 - status = "disabled"; 562 - }; 563 - 564 - i2c_6: i2c@138c0000 { 565 - #address-cells = <1>; 566 - #size-cells = <0>; 567 - compatible = "samsung,s3c2440-i2c"; 568 - reg = <0x138C0000 0x100>; 569 - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 570 - clocks = <&clock CLK_I2C6>; 571 - clock-names = "i2c"; 572 - pinctrl-names = "default"; 573 - pinctrl-0 = <&i2c6_bus>; 574 - status = "disabled"; 575 - }; 576 - 577 - i2c_7: i2c@138d0000 { 578 - #address-cells = <1>; 579 - #size-cells = <0>; 580 - compatible = "samsung,s3c2440-i2c"; 581 - reg = <0x138D0000 0x100>; 582 - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 583 - clocks = <&clock CLK_I2C7>; 584 - clock-names = "i2c"; 585 - pinctrl-names = "default"; 586 - pinctrl-0 = <&i2c7_bus>; 587 - status = "disabled"; 588 - }; 589 - 590 - i2c_8: i2c@138e0000 { 591 - #address-cells = <1>; 592 - #size-cells = <0>; 593 - compatible = "samsung,s3c2440-hdmiphy-i2c"; 594 - reg = <0x138E0000 0x100>; 595 - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 596 - clocks = <&clock CLK_I2C_HDMI>; 597 - clock-names = "i2c"; 598 - status = "disabled"; 599 - 600 - hdmi_i2c_phy: hdmiphy@38 { 601 - compatible = "exynos4210-hdmiphy"; 602 - reg = <0x38>; 603 - }; 604 - }; 605 - 606 - spi_0: spi@13920000 { 607 - compatible = "samsung,exynos4210-spi"; 608 - reg = <0x13920000 0x100>; 609 - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 610 - dmas = <&pdma0 7>, <&pdma0 6>; 611 - dma-names = "tx", "rx"; 612 - #address-cells = <1>; 613 - #size-cells = <0>; 614 - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 615 - clock-names = "spi", "spi_busclk0"; 616 - pinctrl-names = "default"; 617 - pinctrl-0 = <&spi0_bus>; 618 - status = "disabled"; 619 - }; 620 - 621 - spi_1: spi@13930000 { 622 - compatible = "samsung,exynos4210-spi"; 623 - reg = <0x13930000 0x100>; 624 - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 625 - dmas = <&pdma1 7>, <&pdma1 6>; 626 - dma-names = "tx", "rx"; 627 - #address-cells = <1>; 628 - #size-cells = <0>; 629 - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 630 - clock-names = "spi", "spi_busclk0"; 631 - pinctrl-names = "default"; 632 - pinctrl-0 = <&spi1_bus>; 633 - status = "disabled"; 634 - }; 635 - 636 - spi_2: spi@13940000 { 637 - compatible = "samsung,exynos4210-spi"; 638 - reg = <0x13940000 0x100>; 639 - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 640 - dmas = <&pdma0 9>, <&pdma0 8>; 641 - dma-names = "tx", "rx"; 642 - #address-cells = <1>; 643 - #size-cells = <0>; 644 - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 645 - clock-names = "spi", "spi_busclk0"; 646 - pinctrl-names = "default"; 647 - pinctrl-0 = <&spi2_bus>; 648 - status = "disabled"; 649 - }; 650 - 651 - pwm: pwm@139d0000 { 652 - compatible = "samsung,exynos4210-pwm"; 653 - reg = <0x139D0000 0x1000>; 654 - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 655 - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 656 - <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 657 - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 658 - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 659 - clocks = <&clock CLK_PWM>; 660 - clock-names = "timers"; 661 - #pwm-cells = <3>; 662 - status = "disabled"; 663 - }; 664 - 665 - amba { 666 - #address-cells = <1>; 667 - #size-cells = <1>; 55 + soc: soc { 668 56 compatible = "simple-bus"; 669 - interrupt-parent = <&gic>; 57 + #address-cells = <1>; 58 + #size-cells = <1>; 670 59 ranges; 671 60 672 - pdma0: pdma@12680000 { 673 - compatible = "arm,pl330", "arm,primecell"; 674 - reg = <0x12680000 0x1000>; 675 - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 676 - clocks = <&clock CLK_PDMA0>; 677 - clock-names = "apb_pclk"; 678 - #dma-cells = <1>; 679 - #dma-channels = <8>; 680 - #dma-requests = <32>; 61 + clock_audss: clock-controller@3810000 { 62 + compatible = "samsung,exynos4210-audss-clock"; 63 + reg = <0x03810000 0x0C>; 64 + #clock-cells = <1>; 65 + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 66 + <&clock CLK_SCLK_AUDIO0>, 67 + <&clock CLK_SCLK_AUDIO0>; 68 + clock-names = "pll_ref", "pll_in", "sclk_audio", 69 + "sclk_pcm_in"; 681 70 }; 682 71 683 - pdma1: pdma@12690000 { 684 - compatible = "arm,pl330", "arm,primecell"; 685 - reg = <0x12690000 0x1000>; 686 - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 687 - clocks = <&clock CLK_PDMA1>; 688 - clock-names = "apb_pclk"; 689 - #dma-cells = <1>; 690 - #dma-channels = <8>; 691 - #dma-requests = <32>; 72 + i2s0: i2s@3830000 { 73 + compatible = "samsung,s5pv210-i2s"; 74 + reg = <0x03830000 0x100>; 75 + clocks = <&clock_audss EXYNOS_I2S_BUS>, 76 + <&clock_audss EXYNOS_DOUT_AUD_BUS>, 77 + <&clock_audss EXYNOS_SCLK_I2S>; 78 + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 79 + #clock-cells = <1>; 80 + clock-output-names = "i2s_cdclk0"; 81 + dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; 82 + dma-names = "tx", "rx", "tx-sec"; 83 + samsung,idma-addr = <0x03000000>; 84 + #sound-dai-cells = <1>; 85 + status = "disabled"; 692 86 }; 693 87 694 - mdma1: mdma@12850000 { 695 - compatible = "arm,pl330", "arm,primecell"; 696 - reg = <0x12850000 0x1000>; 697 - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 698 - clocks = <&clock CLK_MDMA>; 699 - clock-names = "apb_pclk"; 700 - #dma-cells = <1>; 701 - #dma-channels = <8>; 702 - #dma-requests = <1>; 88 + chipid@10000000 { 89 + compatible = "samsung,exynos4210-chipid"; 90 + reg = <0x10000000 0x100>; 703 91 }; 704 - }; 705 92 706 - fimd: fimd@11c00000 { 707 - compatible = "samsung,exynos4210-fimd"; 708 - interrupt-parent = <&combiner>; 709 - reg = <0x11c00000 0x20000>; 710 - interrupt-names = "fifo", "vsync", "lcd_sys"; 711 - interrupts = <11 0>, <11 1>, <11 2>; 712 - clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; 713 - clock-names = "sclk_fimd", "fimd"; 714 - power-domains = <&pd_lcd0>; 715 - iommus = <&sysmmu_fimd0>; 716 - samsung,sysreg = <&sys_reg>; 717 - status = "disabled"; 718 - }; 93 + scu: snoop-control-unit@10500000 { 94 + compatible = "arm,cortex-a9-scu"; 95 + reg = <0x10500000 0x2000>; 96 + }; 719 97 720 - tmu: tmu@100c0000 { 721 - #include "exynos4412-tmu-sensor-conf.dtsi" 722 - }; 98 + memory-controller@12570000 { 99 + compatible = "samsung,exynos4210-srom"; 100 + reg = <0x12570000 0x14>; 101 + }; 723 102 724 - jpeg_codec: jpeg-codec@11840000 { 725 - compatible = "samsung,exynos4210-jpeg"; 726 - reg = <0x11840000 0x1000>; 727 - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 728 - clocks = <&clock CLK_JPEG>; 729 - clock-names = "jpeg"; 730 - power-domains = <&pd_cam>; 731 - iommus = <&sysmmu_jpeg>; 732 - }; 103 + mipi_phy: video-phy { 104 + compatible = "samsung,s5pv210-mipi-video-phy"; 105 + #phy-cells = <1>; 106 + syscon = <&pmu_system_controller>; 107 + }; 733 108 734 - rotator: rotator@12810000 { 735 - compatible = "samsung,exynos4210-rotator"; 736 - reg = <0x12810000 0x64>; 737 - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 738 - clocks = <&clock CLK_ROTATOR>; 739 - clock-names = "rotator"; 740 - iommus = <&sysmmu_rotator>; 741 - }; 109 + pd_mfc: mfc-power-domain@10023c40 { 110 + compatible = "samsung,exynos4210-pd"; 111 + reg = <0x10023C40 0x20>; 112 + #power-domain-cells = <0>; 113 + label = "MFC"; 114 + }; 742 115 743 - hdmi: hdmi@12d00000 { 744 - compatible = "samsung,exynos4210-hdmi"; 745 - reg = <0x12D00000 0x70000>; 746 - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 747 - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", 748 - "mout_hdmi"; 749 - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 750 - <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 751 - <&clock CLK_MOUT_HDMI>; 752 - phy = <&hdmi_i2c_phy>; 753 - power-domains = <&pd_tv>; 754 - samsung,syscon-phandle = <&pmu_system_controller>; 755 - #sound-dai-cells = <0>; 756 - status = "disabled"; 757 - }; 116 + pd_g3d: g3d-power-domain@10023c60 { 117 + compatible = "samsung,exynos4210-pd"; 118 + reg = <0x10023C60 0x20>; 119 + #power-domain-cells = <0>; 120 + label = "G3D"; 121 + }; 758 122 759 - hdmicec: cec@100b0000 { 760 - compatible = "samsung,s5p-cec"; 761 - reg = <0x100B0000 0x200>; 762 - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 763 - clocks = <&clock CLK_HDMI_CEC>; 764 - clock-names = "hdmicec"; 765 - samsung,syscon-phandle = <&pmu_system_controller>; 766 - hdmi-phandle = <&hdmi>; 767 - pinctrl-names = "default"; 768 - pinctrl-0 = <&hdmi_cec>; 769 - status = "disabled"; 770 - }; 123 + pd_lcd0: lcd0-power-domain@10023c80 { 124 + compatible = "samsung,exynos4210-pd"; 125 + reg = <0x10023C80 0x20>; 126 + #power-domain-cells = <0>; 127 + label = "LCD0"; 128 + }; 771 129 772 - mixer: mixer@12c10000 { 773 - compatible = "samsung,exynos4210-mixer"; 774 - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 775 - reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; 776 - power-domains = <&pd_tv>; 777 - iommus = <&sysmmu_tv>; 778 - status = "disabled"; 779 - }; 130 + pd_tv: tv-power-domain@10023c20 { 131 + compatible = "samsung,exynos4210-pd"; 132 + reg = <0x10023C20 0x20>; 133 + #power-domain-cells = <0>; 134 + power-domains = <&pd_lcd0>; 135 + label = "TV"; 136 + }; 780 137 781 - ppmu_dmc0: ppmu_dmc0@106a0000 { 782 - compatible = "samsung,exynos-ppmu"; 783 - reg = <0x106a0000 0x2000>; 784 - clocks = <&clock CLK_PPMUDMC0>; 785 - clock-names = "ppmu"; 786 - status = "disabled"; 787 - }; 138 + pd_cam: cam-power-domain@10023c00 { 139 + compatible = "samsung,exynos4210-pd"; 140 + reg = <0x10023C00 0x20>; 141 + #power-domain-cells = <0>; 142 + label = "CAM"; 143 + }; 788 144 789 - ppmu_dmc1: ppmu_dmc1@106b0000 { 790 - compatible = "samsung,exynos-ppmu"; 791 - reg = <0x106b0000 0x2000>; 792 - clocks = <&clock CLK_PPMUDMC1>; 793 - clock-names = "ppmu"; 794 - status = "disabled"; 795 - }; 145 + pd_gps: gps-power-domain@10023ce0 { 146 + compatible = "samsung,exynos4210-pd"; 147 + reg = <0x10023CE0 0x20>; 148 + #power-domain-cells = <0>; 149 + label = "GPS"; 150 + }; 796 151 797 - ppmu_cpu: ppmu_cpu@106c0000 { 798 - compatible = "samsung,exynos-ppmu"; 799 - reg = <0x106c0000 0x2000>; 800 - clocks = <&clock CLK_PPMUCPU>; 801 - clock-names = "ppmu"; 802 - status = "disabled"; 803 - }; 152 + pd_gps_alive: gps-alive-power-domain@10023d00 { 153 + compatible = "samsung,exynos4210-pd"; 154 + reg = <0x10023D00 0x20>; 155 + #power-domain-cells = <0>; 156 + label = "GPS alive"; 157 + }; 804 158 805 - ppmu_acp: ppmu_acp@10ae0000 { 806 - compatible = "samsung,exynos-ppmu"; 807 - reg = <0x106e0000 0x2000>; 808 - status = "disabled"; 809 - }; 159 + gic: interrupt-controller@10490000 { 160 + compatible = "arm,cortex-a9-gic"; 161 + #interrupt-cells = <3>; 162 + interrupt-controller; 163 + reg = <0x10490000 0x10000>, <0x10480000 0x10000>; 164 + }; 810 165 811 - ppmu_rightbus: ppmu_rightbus@112a0000 { 812 - compatible = "samsung,exynos-ppmu"; 813 - reg = <0x112a0000 0x2000>; 814 - clocks = <&clock CLK_PPMURIGHT>; 815 - clock-names = "ppmu"; 816 - status = "disabled"; 817 - }; 166 + combiner: interrupt-controller@10440000 { 167 + compatible = "samsung,exynos4210-combiner"; 168 + #interrupt-cells = <2>; 169 + interrupt-controller; 170 + reg = <0x10440000 0x1000>; 171 + }; 818 172 819 - ppmu_leftbus: ppmu_leftbus0@116a0000 { 820 - compatible = "samsung,exynos-ppmu"; 821 - reg = <0x116a0000 0x2000>; 822 - clocks = <&clock CLK_PPMULEFT>; 823 - clock-names = "ppmu"; 824 - status = "disabled"; 825 - }; 173 + pmu: pmu { 174 + compatible = "arm,cortex-a9-pmu"; 175 + interrupt-parent = <&combiner>; 176 + interrupts = <2 2>, <3 2>; 177 + }; 826 178 827 - ppmu_camif: ppmu_camif@11ac0000 { 828 - compatible = "samsung,exynos-ppmu"; 829 - reg = <0x11ac0000 0x2000>; 830 - clocks = <&clock CLK_PPMUCAMIF>; 831 - clock-names = "ppmu"; 832 - status = "disabled"; 833 - }; 179 + sys_reg: syscon@10010000 { 180 + compatible = "samsung,exynos4-sysreg", "syscon"; 181 + reg = <0x10010000 0x400>; 182 + }; 834 183 835 - ppmu_lcd0: ppmu_lcd0@11e40000 { 836 - compatible = "samsung,exynos-ppmu"; 837 - reg = <0x11e40000 0x2000>; 838 - clocks = <&clock CLK_PPMULCD0>; 839 - clock-names = "ppmu"; 840 - status = "disabled"; 841 - }; 184 + pmu_system_controller: system-controller@10020000 { 185 + compatible = "samsung,exynos4210-pmu", "syscon"; 186 + reg = <0x10020000 0x4000>; 187 + interrupt-controller; 188 + #interrupt-cells = <3>; 189 + interrupt-parent = <&gic>; 190 + }; 842 191 843 - ppmu_fsys: ppmu_g3d@12630000 { 844 - compatible = "samsung,exynos-ppmu"; 845 - reg = <0x12630000 0x2000>; 846 - status = "disabled"; 847 - }; 192 + dsi_0: dsi@11c80000 { 193 + compatible = "samsung,exynos4210-mipi-dsi"; 194 + reg = <0x11C80000 0x10000>; 195 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 196 + power-domains = <&pd_lcd0>; 197 + phys = <&mipi_phy 1>; 198 + phy-names = "dsim"; 199 + clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; 200 + clock-names = "bus_clk", "sclk_mipi"; 201 + status = "disabled"; 202 + #address-cells = <1>; 203 + #size-cells = <0>; 204 + }; 848 205 849 - ppmu_image: ppmu_image@12aa0000 { 850 - compatible = "samsung,exynos-ppmu"; 851 - reg = <0x12aa0000 0x2000>; 852 - clocks = <&clock CLK_PPMUIMAGE>; 853 - clock-names = "ppmu"; 854 - status = "disabled"; 855 - }; 206 + camera: camera { 207 + compatible = "samsung,fimc", "simple-bus"; 208 + status = "disabled"; 209 + #address-cells = <1>; 210 + #size-cells = <1>; 211 + #clock-cells = <1>; 212 + clock-output-names = "cam_a_clkout", "cam_b_clkout"; 213 + ranges; 856 214 857 - ppmu_tv: ppmu_tv@12e40000 { 858 - compatible = "samsung,exynos-ppmu"; 859 - reg = <0x12e40000 0x2000>; 860 - clocks = <&clock CLK_PPMUTV>; 861 - clock-names = "ppmu"; 862 - status = "disabled"; 863 - }; 215 + fimc_0: fimc@11800000 { 216 + compatible = "samsung,exynos4210-fimc"; 217 + reg = <0x11800000 0x1000>; 218 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 219 + clocks = <&clock CLK_FIMC0>, 220 + <&clock CLK_SCLK_FIMC0>; 221 + clock-names = "fimc", "sclk_fimc"; 222 + power-domains = <&pd_cam>; 223 + samsung,sysreg = <&sys_reg>; 224 + iommus = <&sysmmu_fimc0>; 225 + status = "disabled"; 226 + }; 864 227 865 - ppmu_g3d: ppmu_g3d@13220000 { 866 - compatible = "samsung,exynos-ppmu"; 867 - reg = <0x13220000 0x2000>; 868 - clocks = <&clock CLK_PPMUG3D>; 869 - clock-names = "ppmu"; 870 - status = "disabled"; 871 - }; 228 + fimc_1: fimc@11810000 { 229 + compatible = "samsung,exynos4210-fimc"; 230 + reg = <0x11810000 0x1000>; 231 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 232 + clocks = <&clock CLK_FIMC1>, 233 + <&clock CLK_SCLK_FIMC1>; 234 + clock-names = "fimc", "sclk_fimc"; 235 + power-domains = <&pd_cam>; 236 + samsung,sysreg = <&sys_reg>; 237 + iommus = <&sysmmu_fimc1>; 238 + status = "disabled"; 239 + }; 872 240 873 - ppmu_mfc_left: ppmu_mfc_left@13660000 { 874 - compatible = "samsung,exynos-ppmu"; 875 - reg = <0x13660000 0x2000>; 876 - clocks = <&clock CLK_PPMUMFC_L>; 877 - clock-names = "ppmu"; 878 - status = "disabled"; 879 - }; 241 + fimc_2: fimc@11820000 { 242 + compatible = "samsung,exynos4210-fimc"; 243 + reg = <0x11820000 0x1000>; 244 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 245 + clocks = <&clock CLK_FIMC2>, 246 + <&clock CLK_SCLK_FIMC2>; 247 + clock-names = "fimc", "sclk_fimc"; 248 + power-domains = <&pd_cam>; 249 + samsung,sysreg = <&sys_reg>; 250 + iommus = <&sysmmu_fimc2>; 251 + status = "disabled"; 252 + }; 880 253 881 - ppmu_mfc_right: ppmu_mfc_right@13670000 { 882 - compatible = "samsung,exynos-ppmu"; 883 - reg = <0x13670000 0x2000>; 884 - clocks = <&clock CLK_PPMUMFC_R>; 885 - clock-names = "ppmu"; 886 - status = "disabled"; 887 - }; 254 + fimc_3: fimc@11830000 { 255 + compatible = "samsung,exynos4210-fimc"; 256 + reg = <0x11830000 0x1000>; 257 + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 258 + clocks = <&clock CLK_FIMC3>, 259 + <&clock CLK_SCLK_FIMC3>; 260 + clock-names = "fimc", "sclk_fimc"; 261 + power-domains = <&pd_cam>; 262 + samsung,sysreg = <&sys_reg>; 263 + iommus = <&sysmmu_fimc3>; 264 + status = "disabled"; 265 + }; 888 266 889 - sysmmu_mfc_l: sysmmu@13620000 { 890 - compatible = "samsung,exynos-sysmmu"; 891 - reg = <0x13620000 0x1000>; 892 - interrupt-parent = <&combiner>; 893 - interrupts = <5 5>; 894 - clock-names = "sysmmu", "master"; 895 - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 896 - power-domains = <&pd_mfc>; 897 - #iommu-cells = <0>; 898 - }; 267 + csis_0: csis@11880000 { 268 + compatible = "samsung,exynos4210-csis"; 269 + reg = <0x11880000 0x4000>; 270 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 271 + clocks = <&clock CLK_CSIS0>, 272 + <&clock CLK_SCLK_CSIS0>; 273 + clock-names = "csis", "sclk_csis"; 274 + bus-width = <4>; 275 + power-domains = <&pd_cam>; 276 + phys = <&mipi_phy 0>; 277 + phy-names = "csis"; 278 + status = "disabled"; 279 + #address-cells = <1>; 280 + #size-cells = <0>; 281 + }; 899 282 900 - sysmmu_mfc_r: sysmmu@13630000 { 901 - compatible = "samsung,exynos-sysmmu"; 902 - reg = <0x13630000 0x1000>; 903 - interrupt-parent = <&combiner>; 904 - interrupts = <5 6>; 905 - clock-names = "sysmmu", "master"; 906 - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 907 - power-domains = <&pd_mfc>; 908 - #iommu-cells = <0>; 909 - }; 283 + csis_1: csis@11890000 { 284 + compatible = "samsung,exynos4210-csis"; 285 + reg = <0x11890000 0x4000>; 286 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 287 + clocks = <&clock CLK_CSIS1>, 288 + <&clock CLK_SCLK_CSIS1>; 289 + clock-names = "csis", "sclk_csis"; 290 + bus-width = <2>; 291 + power-domains = <&pd_cam>; 292 + phys = <&mipi_phy 2>; 293 + phy-names = "csis"; 294 + status = "disabled"; 295 + #address-cells = <1>; 296 + #size-cells = <0>; 297 + }; 298 + }; 910 299 911 - sysmmu_tv: sysmmu@12e20000 { 912 - compatible = "samsung,exynos-sysmmu"; 913 - reg = <0x12E20000 0x1000>; 914 - interrupt-parent = <&combiner>; 915 - interrupts = <5 4>; 916 - clock-names = "sysmmu", "master"; 917 - clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; 918 - power-domains = <&pd_tv>; 919 - #iommu-cells = <0>; 920 - }; 300 + rtc: rtc@10070000 { 301 + compatible = "samsung,s3c6410-rtc"; 302 + reg = <0x10070000 0x100>; 303 + interrupt-parent = <&pmu_system_controller>; 304 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 305 + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 306 + clocks = <&clock CLK_RTC>; 307 + clock-names = "rtc"; 308 + status = "disabled"; 309 + }; 921 310 922 - sysmmu_fimc0: sysmmu@11a20000 { 923 - compatible = "samsung,exynos-sysmmu"; 924 - reg = <0x11A20000 0x1000>; 925 - interrupt-parent = <&combiner>; 926 - interrupts = <4 2>; 927 - clock-names = "sysmmu", "master"; 928 - clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; 929 - power-domains = <&pd_cam>; 930 - #iommu-cells = <0>; 931 - }; 311 + keypad: keypad@100a0000 { 312 + compatible = "samsung,s5pv210-keypad"; 313 + reg = <0x100A0000 0x100>; 314 + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 315 + clocks = <&clock CLK_KEYIF>; 316 + clock-names = "keypad"; 317 + status = "disabled"; 318 + }; 932 319 933 - sysmmu_fimc1: sysmmu@11a30000 { 934 - compatible = "samsung,exynos-sysmmu"; 935 - reg = <0x11A30000 0x1000>; 936 - interrupt-parent = <&combiner>; 937 - interrupts = <4 3>; 938 - clock-names = "sysmmu", "master"; 939 - clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; 940 - power-domains = <&pd_cam>; 941 - #iommu-cells = <0>; 942 - }; 320 + sdhci_0: sdhci@12510000 { 321 + compatible = "samsung,exynos4210-sdhci"; 322 + reg = <0x12510000 0x100>; 323 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 324 + clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 325 + clock-names = "hsmmc", "mmc_busclk.2"; 326 + status = "disabled"; 327 + }; 943 328 944 - sysmmu_fimc2: sysmmu@11a40000 { 945 - compatible = "samsung,exynos-sysmmu"; 946 - reg = <0x11A40000 0x1000>; 947 - interrupt-parent = <&combiner>; 948 - interrupts = <4 4>; 949 - clock-names = "sysmmu", "master"; 950 - clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; 951 - power-domains = <&pd_cam>; 952 - #iommu-cells = <0>; 953 - }; 329 + sdhci_1: sdhci@12520000 { 330 + compatible = "samsung,exynos4210-sdhci"; 331 + reg = <0x12520000 0x100>; 332 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 333 + clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 334 + clock-names = "hsmmc", "mmc_busclk.2"; 335 + status = "disabled"; 336 + }; 954 337 955 - sysmmu_fimc3: sysmmu@11a50000 { 956 - compatible = "samsung,exynos-sysmmu"; 957 - reg = <0x11A50000 0x1000>; 958 - interrupt-parent = <&combiner>; 959 - interrupts = <4 5>; 960 - clock-names = "sysmmu", "master"; 961 - clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; 962 - power-domains = <&pd_cam>; 963 - #iommu-cells = <0>; 964 - }; 338 + sdhci_2: sdhci@12530000 { 339 + compatible = "samsung,exynos4210-sdhci"; 340 + reg = <0x12530000 0x100>; 341 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 342 + clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 343 + clock-names = "hsmmc", "mmc_busclk.2"; 344 + status = "disabled"; 345 + }; 965 346 966 - sysmmu_jpeg: sysmmu@11a60000 { 967 - compatible = "samsung,exynos-sysmmu"; 968 - reg = <0x11A60000 0x1000>; 969 - interrupt-parent = <&combiner>; 970 - interrupts = <4 6>; 971 - clock-names = "sysmmu", "master"; 972 - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 973 - power-domains = <&pd_cam>; 974 - #iommu-cells = <0>; 975 - }; 347 + sdhci_3: sdhci@12540000 { 348 + compatible = "samsung,exynos4210-sdhci"; 349 + reg = <0x12540000 0x100>; 350 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 351 + clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 352 + clock-names = "hsmmc", "mmc_busclk.2"; 353 + status = "disabled"; 354 + }; 976 355 977 - sysmmu_rotator: sysmmu@12a30000 { 978 - compatible = "samsung,exynos-sysmmu"; 979 - reg = <0x12A30000 0x1000>; 980 - interrupt-parent = <&combiner>; 981 - interrupts = <5 0>; 982 - clock-names = "sysmmu", "master"; 983 - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 984 - #iommu-cells = <0>; 985 - }; 356 + exynos_usbphy: exynos-usbphy@125b0000 { 357 + compatible = "samsung,exynos4210-usb2-phy"; 358 + reg = <0x125B0000 0x100>; 359 + samsung,pmureg-phandle = <&pmu_system_controller>; 360 + clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; 361 + clock-names = "phy", "ref"; 362 + #phy-cells = <1>; 363 + status = "disabled"; 364 + }; 986 365 987 - sysmmu_fimd0: sysmmu@11e20000 { 988 - compatible = "samsung,exynos-sysmmu"; 989 - reg = <0x11E20000 0x1000>; 990 - interrupt-parent = <&combiner>; 991 - interrupts = <5 2>; 992 - clock-names = "sysmmu", "master"; 993 - clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; 994 - power-domains = <&pd_lcd0>; 995 - #iommu-cells = <0>; 996 - }; 366 + hsotg: hsotg@12480000 { 367 + compatible = "samsung,s3c6400-hsotg"; 368 + reg = <0x12480000 0x20000>; 369 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 370 + clocks = <&clock CLK_USB_DEVICE>; 371 + clock-names = "otg"; 372 + phys = <&exynos_usbphy 0>; 373 + phy-names = "usb2-phy"; 374 + status = "disabled"; 375 + }; 997 376 998 - sss: sss@10830000 { 999 - compatible = "samsung,exynos4210-secss"; 1000 - reg = <0x10830000 0x300>; 1001 - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1002 - clocks = <&clock CLK_SSS>; 1003 - clock-names = "secss"; 1004 - }; 377 + ehci: ehci@12580000 { 378 + compatible = "samsung,exynos4210-ehci"; 379 + reg = <0x12580000 0x100>; 380 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 381 + clocks = <&clock CLK_USB_HOST>; 382 + clock-names = "usbhost"; 383 + status = "disabled"; 384 + #address-cells = <1>; 385 + #size-cells = <0>; 386 + port@0 { 387 + reg = <0>; 388 + phys = <&exynos_usbphy 1>; 389 + status = "disabled"; 390 + }; 391 + port@1 { 392 + reg = <1>; 393 + phys = <&exynos_usbphy 2>; 394 + status = "disabled"; 395 + }; 396 + port@2 { 397 + reg = <2>; 398 + phys = <&exynos_usbphy 3>; 399 + status = "disabled"; 400 + }; 401 + }; 1005 402 1006 - prng: rng@10830400 { 1007 - compatible = "samsung,exynos4-rng"; 1008 - reg = <0x10830400 0x200>; 1009 - clocks = <&clock CLK_SSS>; 1010 - clock-names = "secss"; 403 + ohci: ohci@12590000 { 404 + compatible = "samsung,exynos4210-ohci"; 405 + reg = <0x12590000 0x100>; 406 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 407 + clocks = <&clock CLK_USB_HOST>; 408 + clock-names = "usbhost"; 409 + status = "disabled"; 410 + #address-cells = <1>; 411 + #size-cells = <0>; 412 + port@0 { 413 + reg = <0>; 414 + phys = <&exynos_usbphy 1>; 415 + status = "disabled"; 416 + }; 417 + }; 418 + 419 + i2s1: i2s@13960000 { 420 + compatible = "samsung,s3c6410-i2s"; 421 + reg = <0x13960000 0x100>; 422 + clocks = <&clock CLK_I2S1>; 423 + clock-names = "iis"; 424 + #clock-cells = <1>; 425 + clock-output-names = "i2s_cdclk1"; 426 + dmas = <&pdma1 12>, <&pdma1 11>; 427 + dma-names = "tx", "rx"; 428 + #sound-dai-cells = <1>; 429 + status = "disabled"; 430 + }; 431 + 432 + i2s2: i2s@13970000 { 433 + compatible = "samsung,s3c6410-i2s"; 434 + reg = <0x13970000 0x100>; 435 + clocks = <&clock CLK_I2S2>; 436 + clock-names = "iis"; 437 + #clock-cells = <1>; 438 + clock-output-names = "i2s_cdclk2"; 439 + dmas = <&pdma0 14>, <&pdma0 13>; 440 + dma-names = "tx", "rx"; 441 + #sound-dai-cells = <1>; 442 + status = "disabled"; 443 + }; 444 + 445 + mfc: codec@13400000 { 446 + compatible = "samsung,mfc-v5"; 447 + reg = <0x13400000 0x10000>; 448 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 449 + power-domains = <&pd_mfc>; 450 + clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; 451 + clock-names = "mfc", "sclk_mfc"; 452 + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 453 + iommu-names = "left", "right"; 454 + }; 455 + 456 + serial_0: serial@13800000 { 457 + compatible = "samsung,exynos4210-uart"; 458 + reg = <0x13800000 0x100>; 459 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 460 + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 461 + clock-names = "uart", "clk_uart_baud0"; 462 + dmas = <&pdma0 15>, <&pdma0 16>; 463 + dma-names = "rx", "tx"; 464 + status = "disabled"; 465 + }; 466 + 467 + serial_1: serial@13810000 { 468 + compatible = "samsung,exynos4210-uart"; 469 + reg = <0x13810000 0x100>; 470 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 471 + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 472 + clock-names = "uart", "clk_uart_baud0"; 473 + dmas = <&pdma1 15>, <&pdma1 16>; 474 + dma-names = "rx", "tx"; 475 + status = "disabled"; 476 + }; 477 + 478 + serial_2: serial@13820000 { 479 + compatible = "samsung,exynos4210-uart"; 480 + reg = <0x13820000 0x100>; 481 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 482 + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 483 + clock-names = "uart", "clk_uart_baud0"; 484 + dmas = <&pdma0 17>, <&pdma0 18>; 485 + dma-names = "rx", "tx"; 486 + status = "disabled"; 487 + }; 488 + 489 + serial_3: serial@13830000 { 490 + compatible = "samsung,exynos4210-uart"; 491 + reg = <0x13830000 0x100>; 492 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 493 + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 494 + clock-names = "uart", "clk_uart_baud0"; 495 + dmas = <&pdma1 17>, <&pdma1 18>; 496 + dma-names = "rx", "tx"; 497 + status = "disabled"; 498 + }; 499 + 500 + i2c_0: i2c@13860000 { 501 + #address-cells = <1>; 502 + #size-cells = <0>; 503 + compatible = "samsung,s3c2440-i2c"; 504 + reg = <0x13860000 0x100>; 505 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 506 + clocks = <&clock CLK_I2C0>; 507 + clock-names = "i2c"; 508 + pinctrl-names = "default"; 509 + pinctrl-0 = <&i2c0_bus>; 510 + status = "disabled"; 511 + }; 512 + 513 + i2c_1: i2c@13870000 { 514 + #address-cells = <1>; 515 + #size-cells = <0>; 516 + compatible = "samsung,s3c2440-i2c"; 517 + reg = <0x13870000 0x100>; 518 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 519 + clocks = <&clock CLK_I2C1>; 520 + clock-names = "i2c"; 521 + pinctrl-names = "default"; 522 + pinctrl-0 = <&i2c1_bus>; 523 + status = "disabled"; 524 + }; 525 + 526 + i2c_2: i2c@13880000 { 527 + #address-cells = <1>; 528 + #size-cells = <0>; 529 + compatible = "samsung,s3c2440-i2c"; 530 + reg = <0x13880000 0x100>; 531 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 532 + clocks = <&clock CLK_I2C2>; 533 + clock-names = "i2c"; 534 + pinctrl-names = "default"; 535 + pinctrl-0 = <&i2c2_bus>; 536 + status = "disabled"; 537 + }; 538 + 539 + i2c_3: i2c@13890000 { 540 + #address-cells = <1>; 541 + #size-cells = <0>; 542 + compatible = "samsung,s3c2440-i2c"; 543 + reg = <0x13890000 0x100>; 544 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 545 + clocks = <&clock CLK_I2C3>; 546 + clock-names = "i2c"; 547 + pinctrl-names = "default"; 548 + pinctrl-0 = <&i2c3_bus>; 549 + status = "disabled"; 550 + }; 551 + 552 + i2c_4: i2c@138a0000 { 553 + #address-cells = <1>; 554 + #size-cells = <0>; 555 + compatible = "samsung,s3c2440-i2c"; 556 + reg = <0x138A0000 0x100>; 557 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 558 + clocks = <&clock CLK_I2C4>; 559 + clock-names = "i2c"; 560 + pinctrl-names = "default"; 561 + pinctrl-0 = <&i2c4_bus>; 562 + status = "disabled"; 563 + }; 564 + 565 + i2c_5: i2c@138b0000 { 566 + #address-cells = <1>; 567 + #size-cells = <0>; 568 + compatible = "samsung,s3c2440-i2c"; 569 + reg = <0x138B0000 0x100>; 570 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 571 + clocks = <&clock CLK_I2C5>; 572 + clock-names = "i2c"; 573 + pinctrl-names = "default"; 574 + pinctrl-0 = <&i2c5_bus>; 575 + status = "disabled"; 576 + }; 577 + 578 + i2c_6: i2c@138c0000 { 579 + #address-cells = <1>; 580 + #size-cells = <0>; 581 + compatible = "samsung,s3c2440-i2c"; 582 + reg = <0x138C0000 0x100>; 583 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 584 + clocks = <&clock CLK_I2C6>; 585 + clock-names = "i2c"; 586 + pinctrl-names = "default"; 587 + pinctrl-0 = <&i2c6_bus>; 588 + status = "disabled"; 589 + }; 590 + 591 + i2c_7: i2c@138d0000 { 592 + #address-cells = <1>; 593 + #size-cells = <0>; 594 + compatible = "samsung,s3c2440-i2c"; 595 + reg = <0x138D0000 0x100>; 596 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 597 + clocks = <&clock CLK_I2C7>; 598 + clock-names = "i2c"; 599 + pinctrl-names = "default"; 600 + pinctrl-0 = <&i2c7_bus>; 601 + status = "disabled"; 602 + }; 603 + 604 + i2c_8: i2c@138e0000 { 605 + #address-cells = <1>; 606 + #size-cells = <0>; 607 + compatible = "samsung,s3c2440-hdmiphy-i2c"; 608 + reg = <0x138E0000 0x100>; 609 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 610 + clocks = <&clock CLK_I2C_HDMI>; 611 + clock-names = "i2c"; 612 + status = "disabled"; 613 + 614 + hdmi_i2c_phy: hdmiphy@38 { 615 + compatible = "exynos4210-hdmiphy"; 616 + reg = <0x38>; 617 + }; 618 + }; 619 + 620 + spi_0: spi@13920000 { 621 + compatible = "samsung,exynos4210-spi"; 622 + reg = <0x13920000 0x100>; 623 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 624 + dmas = <&pdma0 7>, <&pdma0 6>; 625 + dma-names = "tx", "rx"; 626 + #address-cells = <1>; 627 + #size-cells = <0>; 628 + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 629 + clock-names = "spi", "spi_busclk0"; 630 + pinctrl-names = "default"; 631 + pinctrl-0 = <&spi0_bus>; 632 + status = "disabled"; 633 + }; 634 + 635 + spi_1: spi@13930000 { 636 + compatible = "samsung,exynos4210-spi"; 637 + reg = <0x13930000 0x100>; 638 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 639 + dmas = <&pdma1 7>, <&pdma1 6>; 640 + dma-names = "tx", "rx"; 641 + #address-cells = <1>; 642 + #size-cells = <0>; 643 + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 644 + clock-names = "spi", "spi_busclk0"; 645 + pinctrl-names = "default"; 646 + pinctrl-0 = <&spi1_bus>; 647 + status = "disabled"; 648 + }; 649 + 650 + spi_2: spi@13940000 { 651 + compatible = "samsung,exynos4210-spi"; 652 + reg = <0x13940000 0x100>; 653 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 654 + dmas = <&pdma0 9>, <&pdma0 8>; 655 + dma-names = "tx", "rx"; 656 + #address-cells = <1>; 657 + #size-cells = <0>; 658 + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 659 + clock-names = "spi", "spi_busclk0"; 660 + pinctrl-names = "default"; 661 + pinctrl-0 = <&spi2_bus>; 662 + status = "disabled"; 663 + }; 664 + 665 + pwm: pwm@139d0000 { 666 + compatible = "samsung,exynos4210-pwm"; 667 + reg = <0x139D0000 0x1000>; 668 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 669 + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 670 + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 671 + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 672 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 673 + clocks = <&clock CLK_PWM>; 674 + clock-names = "timers"; 675 + #pwm-cells = <3>; 676 + status = "disabled"; 677 + }; 678 + 679 + amba { 680 + #address-cells = <1>; 681 + #size-cells = <1>; 682 + compatible = "simple-bus"; 683 + interrupt-parent = <&gic>; 684 + ranges; 685 + 686 + pdma0: pdma@12680000 { 687 + compatible = "arm,pl330", "arm,primecell"; 688 + reg = <0x12680000 0x1000>; 689 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 690 + clocks = <&clock CLK_PDMA0>; 691 + clock-names = "apb_pclk"; 692 + #dma-cells = <1>; 693 + #dma-channels = <8>; 694 + #dma-requests = <32>; 695 + }; 696 + 697 + pdma1: pdma@12690000 { 698 + compatible = "arm,pl330", "arm,primecell"; 699 + reg = <0x12690000 0x1000>; 700 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 701 + clocks = <&clock CLK_PDMA1>; 702 + clock-names = "apb_pclk"; 703 + #dma-cells = <1>; 704 + #dma-channels = <8>; 705 + #dma-requests = <32>; 706 + }; 707 + 708 + mdma1: mdma@12850000 { 709 + compatible = "arm,pl330", "arm,primecell"; 710 + reg = <0x12850000 0x1000>; 711 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 712 + clocks = <&clock CLK_MDMA>; 713 + clock-names = "apb_pclk"; 714 + #dma-cells = <1>; 715 + #dma-channels = <8>; 716 + #dma-requests = <1>; 717 + }; 718 + }; 719 + 720 + fimd: fimd@11c00000 { 721 + compatible = "samsung,exynos4210-fimd"; 722 + interrupt-parent = <&combiner>; 723 + reg = <0x11c00000 0x20000>; 724 + interrupt-names = "fifo", "vsync", "lcd_sys"; 725 + interrupts = <11 0>, <11 1>, <11 2>; 726 + clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; 727 + clock-names = "sclk_fimd", "fimd"; 728 + power-domains = <&pd_lcd0>; 729 + iommus = <&sysmmu_fimd0>; 730 + samsung,sysreg = <&sys_reg>; 731 + status = "disabled"; 732 + }; 733 + 734 + tmu: tmu@100c0000 { 735 + interrupt-parent = <&combiner>; 736 + reg = <0x100C0000 0x100>; 737 + interrupts = <2 4>; 738 + status = "disabled"; 739 + #include "exynos4412-tmu-sensor-conf.dtsi" 740 + }; 741 + 742 + jpeg_codec: jpeg-codec@11840000 { 743 + compatible = "samsung,exynos4210-jpeg"; 744 + reg = <0x11840000 0x1000>; 745 + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 746 + clocks = <&clock CLK_JPEG>; 747 + clock-names = "jpeg"; 748 + power-domains = <&pd_cam>; 749 + iommus = <&sysmmu_jpeg>; 750 + }; 751 + 752 + rotator: rotator@12810000 { 753 + compatible = "samsung,exynos4210-rotator"; 754 + reg = <0x12810000 0x64>; 755 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 756 + clocks = <&clock CLK_ROTATOR>; 757 + clock-names = "rotator"; 758 + iommus = <&sysmmu_rotator>; 759 + }; 760 + 761 + hdmi: hdmi@12d00000 { 762 + compatible = "samsung,exynos4210-hdmi"; 763 + reg = <0x12D00000 0x70000>; 764 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 765 + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 766 + "sclk_hdmiphy", "mout_hdmi"; 767 + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 768 + <&clock CLK_SCLK_PIXEL>, 769 + <&clock CLK_SCLK_HDMIPHY>, 770 + <&clock CLK_MOUT_HDMI>; 771 + phy = <&hdmi_i2c_phy>; 772 + power-domains = <&pd_tv>; 773 + samsung,syscon-phandle = <&pmu_system_controller>; 774 + #sound-dai-cells = <0>; 775 + status = "disabled"; 776 + }; 777 + 778 + hdmicec: cec@100b0000 { 779 + compatible = "samsung,s5p-cec"; 780 + reg = <0x100B0000 0x200>; 781 + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 782 + clocks = <&clock CLK_HDMI_CEC>; 783 + clock-names = "hdmicec"; 784 + samsung,syscon-phandle = <&pmu_system_controller>; 785 + hdmi-phandle = <&hdmi>; 786 + pinctrl-names = "default"; 787 + pinctrl-0 = <&hdmi_cec>; 788 + status = "disabled"; 789 + }; 790 + 791 + mixer: mixer@12c10000 { 792 + compatible = "samsung,exynos4210-mixer"; 793 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 794 + reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; 795 + power-domains = <&pd_tv>; 796 + iommus = <&sysmmu_tv>; 797 + status = "disabled"; 798 + }; 799 + 800 + ppmu_dmc0: ppmu_dmc0@106a0000 { 801 + compatible = "samsung,exynos-ppmu"; 802 + reg = <0x106a0000 0x2000>; 803 + clocks = <&clock CLK_PPMUDMC0>; 804 + clock-names = "ppmu"; 805 + status = "disabled"; 806 + }; 807 + 808 + ppmu_dmc1: ppmu_dmc1@106b0000 { 809 + compatible = "samsung,exynos-ppmu"; 810 + reg = <0x106b0000 0x2000>; 811 + clocks = <&clock CLK_PPMUDMC1>; 812 + clock-names = "ppmu"; 813 + status = "disabled"; 814 + }; 815 + 816 + ppmu_cpu: ppmu_cpu@106c0000 { 817 + compatible = "samsung,exynos-ppmu"; 818 + reg = <0x106c0000 0x2000>; 819 + clocks = <&clock CLK_PPMUCPU>; 820 + clock-names = "ppmu"; 821 + status = "disabled"; 822 + }; 823 + 824 + ppmu_rightbus: ppmu_rightbus@112a0000 { 825 + compatible = "samsung,exynos-ppmu"; 826 + reg = <0x112a0000 0x2000>; 827 + clocks = <&clock CLK_PPMURIGHT>; 828 + clock-names = "ppmu"; 829 + status = "disabled"; 830 + }; 831 + 832 + ppmu_leftbus: ppmu_leftbus0@116a0000 { 833 + compatible = "samsung,exynos-ppmu"; 834 + reg = <0x116a0000 0x2000>; 835 + clocks = <&clock CLK_PPMULEFT>; 836 + clock-names = "ppmu"; 837 + status = "disabled"; 838 + }; 839 + 840 + ppmu_camif: ppmu_camif@11ac0000 { 841 + compatible = "samsung,exynos-ppmu"; 842 + reg = <0x11ac0000 0x2000>; 843 + clocks = <&clock CLK_PPMUCAMIF>; 844 + clock-names = "ppmu"; 845 + status = "disabled"; 846 + }; 847 + 848 + ppmu_lcd0: ppmu_lcd0@11e40000 { 849 + compatible = "samsung,exynos-ppmu"; 850 + reg = <0x11e40000 0x2000>; 851 + clocks = <&clock CLK_PPMULCD0>; 852 + clock-names = "ppmu"; 853 + status = "disabled"; 854 + }; 855 + 856 + ppmu_fsys: ppmu_g3d@12630000 { 857 + compatible = "samsung,exynos-ppmu"; 858 + reg = <0x12630000 0x2000>; 859 + status = "disabled"; 860 + }; 861 + 862 + ppmu_image: ppmu_image@12aa0000 { 863 + compatible = "samsung,exynos-ppmu"; 864 + reg = <0x12aa0000 0x2000>; 865 + clocks = <&clock CLK_PPMUIMAGE>; 866 + clock-names = "ppmu"; 867 + status = "disabled"; 868 + }; 869 + 870 + ppmu_tv: ppmu_tv@12e40000 { 871 + compatible = "samsung,exynos-ppmu"; 872 + reg = <0x12e40000 0x2000>; 873 + clocks = <&clock CLK_PPMUTV>; 874 + clock-names = "ppmu"; 875 + status = "disabled"; 876 + }; 877 + 878 + ppmu_g3d: ppmu_g3d@13220000 { 879 + compatible = "samsung,exynos-ppmu"; 880 + reg = <0x13220000 0x2000>; 881 + clocks = <&clock CLK_PPMUG3D>; 882 + clock-names = "ppmu"; 883 + status = "disabled"; 884 + }; 885 + 886 + ppmu_mfc_left: ppmu_mfc_left@13660000 { 887 + compatible = "samsung,exynos-ppmu"; 888 + reg = <0x13660000 0x2000>; 889 + clocks = <&clock CLK_PPMUMFC_L>; 890 + clock-names = "ppmu"; 891 + status = "disabled"; 892 + }; 893 + 894 + ppmu_mfc_right: ppmu_mfc_right@13670000 { 895 + compatible = "samsung,exynos-ppmu"; 896 + reg = <0x13670000 0x2000>; 897 + clocks = <&clock CLK_PPMUMFC_R>; 898 + clock-names = "ppmu"; 899 + status = "disabled"; 900 + }; 901 + 902 + sysmmu_mfc_l: sysmmu@13620000 { 903 + compatible = "samsung,exynos-sysmmu"; 904 + reg = <0x13620000 0x1000>; 905 + interrupt-parent = <&combiner>; 906 + interrupts = <5 5>; 907 + clock-names = "sysmmu", "master"; 908 + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 909 + power-domains = <&pd_mfc>; 910 + #iommu-cells = <0>; 911 + }; 912 + 913 + sysmmu_mfc_r: sysmmu@13630000 { 914 + compatible = "samsung,exynos-sysmmu"; 915 + reg = <0x13630000 0x1000>; 916 + interrupt-parent = <&combiner>; 917 + interrupts = <5 6>; 918 + clock-names = "sysmmu", "master"; 919 + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 920 + power-domains = <&pd_mfc>; 921 + #iommu-cells = <0>; 922 + }; 923 + 924 + sysmmu_tv: sysmmu@12e20000 { 925 + compatible = "samsung,exynos-sysmmu"; 926 + reg = <0x12E20000 0x1000>; 927 + interrupt-parent = <&combiner>; 928 + interrupts = <5 4>; 929 + clock-names = "sysmmu", "master"; 930 + clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; 931 + power-domains = <&pd_tv>; 932 + #iommu-cells = <0>; 933 + }; 934 + 935 + sysmmu_fimc0: sysmmu@11a20000 { 936 + compatible = "samsung,exynos-sysmmu"; 937 + reg = <0x11A20000 0x1000>; 938 + interrupt-parent = <&combiner>; 939 + interrupts = <4 2>; 940 + clock-names = "sysmmu", "master"; 941 + clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; 942 + power-domains = <&pd_cam>; 943 + #iommu-cells = <0>; 944 + }; 945 + 946 + sysmmu_fimc1: sysmmu@11a30000 { 947 + compatible = "samsung,exynos-sysmmu"; 948 + reg = <0x11A30000 0x1000>; 949 + interrupt-parent = <&combiner>; 950 + interrupts = <4 3>; 951 + clock-names = "sysmmu", "master"; 952 + clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; 953 + power-domains = <&pd_cam>; 954 + #iommu-cells = <0>; 955 + }; 956 + 957 + sysmmu_fimc2: sysmmu@11a40000 { 958 + compatible = "samsung,exynos-sysmmu"; 959 + reg = <0x11A40000 0x1000>; 960 + interrupt-parent = <&combiner>; 961 + interrupts = <4 4>; 962 + clock-names = "sysmmu", "master"; 963 + clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; 964 + power-domains = <&pd_cam>; 965 + #iommu-cells = <0>; 966 + }; 967 + 968 + sysmmu_fimc3: sysmmu@11a50000 { 969 + compatible = "samsung,exynos-sysmmu"; 970 + reg = <0x11A50000 0x1000>; 971 + interrupt-parent = <&combiner>; 972 + interrupts = <4 5>; 973 + clock-names = "sysmmu", "master"; 974 + clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; 975 + power-domains = <&pd_cam>; 976 + #iommu-cells = <0>; 977 + }; 978 + 979 + sysmmu_jpeg: sysmmu@11a60000 { 980 + compatible = "samsung,exynos-sysmmu"; 981 + reg = <0x11A60000 0x1000>; 982 + interrupt-parent = <&combiner>; 983 + interrupts = <4 6>; 984 + clock-names = "sysmmu", "master"; 985 + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 986 + power-domains = <&pd_cam>; 987 + #iommu-cells = <0>; 988 + }; 989 + 990 + sysmmu_rotator: sysmmu@12a30000 { 991 + compatible = "samsung,exynos-sysmmu"; 992 + reg = <0x12A30000 0x1000>; 993 + interrupt-parent = <&combiner>; 994 + interrupts = <5 0>; 995 + clock-names = "sysmmu", "master"; 996 + clocks = <&clock CLK_SMMU_ROTATOR>, 997 + <&clock CLK_ROTATOR>; 998 + #iommu-cells = <0>; 999 + }; 1000 + 1001 + sysmmu_fimd0: sysmmu@11e20000 { 1002 + compatible = "samsung,exynos-sysmmu"; 1003 + reg = <0x11E20000 0x1000>; 1004 + interrupt-parent = <&combiner>; 1005 + interrupts = <5 2>; 1006 + clock-names = "sysmmu", "master"; 1007 + clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; 1008 + power-domains = <&pd_lcd0>; 1009 + #iommu-cells = <0>; 1010 + }; 1011 + 1012 + sss: sss@10830000 { 1013 + compatible = "samsung,exynos4210-secss"; 1014 + reg = <0x10830000 0x300>; 1015 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1016 + clocks = <&clock CLK_SSS>; 1017 + clock-names = "secss"; 1018 + }; 1019 + 1020 + prng: rng@10830400 { 1021 + compatible = "samsung,exynos4-rng"; 1022 + reg = <0x10830400 0x200>; 1023 + clocks = <&clock CLK_SSS>; 1024 + clock-names = "secss"; 1025 + }; 1011 1026 }; 1012 1027 };
+840 -842
arch/arm/boot/dts/exynos4210-pinctrl.dtsi
··· 13 13 14 14 #include <dt-bindings/pinctrl/samsung.h> 15 15 16 - / { 17 - pinctrl@11400000 { 18 - gpa0: gpa0 { 19 - gpio-controller; 20 - #gpio-cells = <2>; 21 - 22 - interrupt-controller; 23 - #interrupt-cells = <2>; 24 - }; 25 - 26 - gpa1: gpa1 { 27 - gpio-controller; 28 - #gpio-cells = <2>; 29 - 30 - interrupt-controller; 31 - #interrupt-cells = <2>; 32 - }; 33 - 34 - gpb: gpb { 35 - gpio-controller; 36 - #gpio-cells = <2>; 37 - 38 - interrupt-controller; 39 - #interrupt-cells = <2>; 40 - }; 41 - 42 - gpc0: gpc0 { 43 - gpio-controller; 44 - #gpio-cells = <2>; 45 - 46 - interrupt-controller; 47 - #interrupt-cells = <2>; 48 - }; 49 - 50 - gpc1: gpc1 { 51 - gpio-controller; 52 - #gpio-cells = <2>; 53 - 54 - interrupt-controller; 55 - #interrupt-cells = <2>; 56 - }; 57 - 58 - gpd0: gpd0 { 59 - gpio-controller; 60 - #gpio-cells = <2>; 61 - 62 - interrupt-controller; 63 - #interrupt-cells = <2>; 64 - }; 65 - 66 - gpd1: gpd1 { 67 - gpio-controller; 68 - #gpio-cells = <2>; 69 - 70 - interrupt-controller; 71 - #interrupt-cells = <2>; 72 - }; 73 - 74 - gpe0: gpe0 { 75 - gpio-controller; 76 - #gpio-cells = <2>; 77 - 78 - interrupt-controller; 79 - #interrupt-cells = <2>; 80 - }; 81 - 82 - gpe1: gpe1 { 83 - gpio-controller; 84 - #gpio-cells = <2>; 85 - 86 - interrupt-controller; 87 - #interrupt-cells = <2>; 88 - }; 89 - 90 - gpe2: gpe2 { 91 - gpio-controller; 92 - #gpio-cells = <2>; 93 - 94 - interrupt-controller; 95 - #interrupt-cells = <2>; 96 - }; 97 - 98 - gpe3: gpe3 { 99 - gpio-controller; 100 - #gpio-cells = <2>; 101 - 102 - interrupt-controller; 103 - #interrupt-cells = <2>; 104 - }; 105 - 106 - gpe4: gpe4 { 107 - gpio-controller; 108 - #gpio-cells = <2>; 109 - 110 - interrupt-controller; 111 - #interrupt-cells = <2>; 112 - }; 113 - 114 - gpf0: gpf0 { 115 - gpio-controller; 116 - #gpio-cells = <2>; 117 - 118 - interrupt-controller; 119 - #interrupt-cells = <2>; 120 - }; 121 - 122 - gpf1: gpf1 { 123 - gpio-controller; 124 - #gpio-cells = <2>; 125 - 126 - interrupt-controller; 127 - #interrupt-cells = <2>; 128 - }; 129 - 130 - gpf2: gpf2 { 131 - gpio-controller; 132 - #gpio-cells = <2>; 133 - 134 - interrupt-controller; 135 - #interrupt-cells = <2>; 136 - }; 137 - 138 - gpf3: gpf3 { 139 - gpio-controller; 140 - #gpio-cells = <2>; 141 - 142 - interrupt-controller; 143 - #interrupt-cells = <2>; 144 - }; 145 - 146 - uart0_data: uart0-data { 147 - samsung,pins = "gpa0-0", "gpa0-1"; 148 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 149 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 150 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 151 - }; 152 - 153 - uart0_fctl: uart0-fctl { 154 - samsung,pins = "gpa0-2", "gpa0-3"; 155 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 156 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 157 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 158 - }; 159 - 160 - uart1_data: uart1-data { 161 - samsung,pins = "gpa0-4", "gpa0-5"; 162 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 163 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 164 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 165 - }; 166 - 167 - uart1_fctl: uart1-fctl { 168 - samsung,pins = "gpa0-6", "gpa0-7"; 169 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 170 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 171 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 172 - }; 173 - 174 - i2c2_bus: i2c2-bus { 175 - samsung,pins = "gpa0-6", "gpa0-7"; 176 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 177 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 178 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 179 - }; 180 - 181 - uart2_data: uart2-data { 182 - samsung,pins = "gpa1-0", "gpa1-1"; 183 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 184 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 185 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 186 - }; 187 - 188 - uart2_fctl: uart2-fctl { 189 - samsung,pins = "gpa1-2", "gpa1-3"; 190 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 191 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 192 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 193 - }; 194 - 195 - uart_audio_a: uart-audio-a { 196 - samsung,pins = "gpa1-0", "gpa1-1"; 197 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 198 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 199 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 200 - }; 201 - 202 - i2c3_bus: i2c3-bus { 203 - samsung,pins = "gpa1-2", "gpa1-3"; 204 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 205 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 206 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 207 - }; 208 - 209 - uart3_data: uart3-data { 210 - samsung,pins = "gpa1-4", "gpa1-5"; 211 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 212 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 213 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 214 - }; 215 - 216 - uart_audio_b: uart-audio-b { 217 - samsung,pins = "gpa1-4", "gpa1-5"; 218 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 219 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 220 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 221 - }; 222 - 223 - spi0_bus: spi0-bus { 224 - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; 225 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 226 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 227 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 228 - }; 229 - 230 - i2c4_bus: i2c4-bus { 231 - samsung,pins = "gpb-2", "gpb-3"; 232 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 233 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 234 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 235 - }; 236 - 237 - spi1_bus: spi1-bus { 238 - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; 239 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 240 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 241 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 242 - }; 243 - 244 - i2c5_bus: i2c5-bus { 245 - samsung,pins = "gpb-6", "gpb-7"; 246 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 247 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 248 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 249 - }; 250 - 251 - i2s1_bus: i2s1-bus { 252 - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 253 - "gpc0-4"; 254 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 255 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 256 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 257 - }; 258 - 259 - pcm1_bus: pcm1-bus { 260 - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 261 - "gpc0-4"; 262 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 263 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 264 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 265 - }; 266 - 267 - ac97_bus: ac97-bus { 268 - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 269 - "gpc0-4"; 270 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 271 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 272 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 273 - }; 274 - 275 - i2s2_bus: i2s2-bus { 276 - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", 277 - "gpc1-4"; 278 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 279 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 280 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 281 - }; 282 - 283 - pcm2_bus: pcm2-bus { 284 - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", 285 - "gpc1-4"; 286 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 287 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 288 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 289 - }; 290 - 291 - spdif_bus: spdif-bus { 292 - samsung,pins = "gpc1-0", "gpc1-1"; 293 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 294 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 295 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 296 - }; 297 - 298 - i2c6_bus: i2c6-bus { 299 - samsung,pins = "gpc1-3", "gpc1-4"; 300 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 301 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 302 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 303 - }; 304 - 305 - spi2_bus: spi2-bus { 306 - samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; 307 - samsung,pin-function = <EXYNOS_PIN_FUNC_5>; 308 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 309 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 310 - }; 311 - 312 - i2c7_bus: i2c7-bus { 313 - samsung,pins = "gpd0-2", "gpd0-3"; 314 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 315 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 316 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 317 - }; 318 - 319 - i2c0_bus: i2c0-bus { 320 - samsung,pins = "gpd1-0", "gpd1-1"; 321 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 322 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 323 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 324 - }; 325 - 326 - i2c1_bus: i2c1-bus { 327 - samsung,pins = "gpd1-2", "gpd1-3"; 328 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 329 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 330 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 331 - }; 332 - 333 - pwm0_out: pwm0-out { 334 - samsung,pins = "gpd0-0"; 335 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 336 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 337 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 338 - }; 339 - 340 - pwm1_out: pwm1-out { 341 - samsung,pins = "gpd0-1"; 342 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 343 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 344 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 345 - }; 346 - 347 - pwm2_out: pwm2-out { 348 - samsung,pins = "gpd0-2"; 349 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 350 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 351 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 352 - }; 353 - 354 - pwm3_out: pwm3-out { 355 - samsung,pins = "gpd0-3"; 356 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 357 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 358 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 359 - }; 360 - 361 - lcd_ctrl: lcd-ctrl { 362 - samsung,pins = "gpd0-0", "gpd0-1"; 363 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 364 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 365 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 366 - }; 367 - 368 - lcd_sync: lcd-sync { 369 - samsung,pins = "gpf0-0", "gpf0-1"; 370 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 371 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 372 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 373 - }; 374 - 375 - lcd_en: lcd-en { 376 - samsung,pins = "gpe3-4"; 377 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 378 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 379 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 380 - }; 381 - 382 - lcd_clk: lcd-clk { 383 - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; 384 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 385 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 386 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 387 - }; 388 - 389 - lcd_data16: lcd-data-width16 { 390 - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", 391 - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", 392 - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", 393 - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; 394 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 395 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 396 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 397 - }; 398 - 399 - lcd_data18: lcd-data-width18 { 400 - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", 401 - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", 402 - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", 403 - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", 404 - "gpf3-2", "gpf3-3"; 405 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 406 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 407 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 408 - }; 409 - 410 - lcd_data24: lcd-data-width24 { 411 - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", 412 - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", 413 - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", 414 - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", 415 - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", 416 - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; 417 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 418 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 419 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 420 - }; 16 + &pinctrl_0 { 17 + gpa0: gpa0 { 18 + gpio-controller; 19 + #gpio-cells = <2>; 20 + 21 + interrupt-controller; 22 + #interrupt-cells = <2>; 421 23 }; 422 24 423 - pinctrl@11000000 { 424 - gpj0: gpj0 { 425 - gpio-controller; 426 - #gpio-cells = <2>; 427 - 428 - interrupt-controller; 429 - #interrupt-cells = <2>; 430 - }; 431 - 432 - gpj1: gpj1 { 433 - gpio-controller; 434 - #gpio-cells = <2>; 435 - 436 - interrupt-controller; 437 - #interrupt-cells = <2>; 438 - }; 439 - 440 - gpk0: gpk0 { 441 - gpio-controller; 442 - #gpio-cells = <2>; 443 - 444 - interrupt-controller; 445 - #interrupt-cells = <2>; 446 - }; 447 - 448 - gpk1: gpk1 { 449 - gpio-controller; 450 - #gpio-cells = <2>; 451 - 452 - interrupt-controller; 453 - #interrupt-cells = <2>; 454 - }; 455 - 456 - gpk2: gpk2 { 457 - gpio-controller; 458 - #gpio-cells = <2>; 459 - 460 - interrupt-controller; 461 - #interrupt-cells = <2>; 462 - }; 463 - 464 - gpk3: gpk3 { 465 - gpio-controller; 466 - #gpio-cells = <2>; 467 - 468 - interrupt-controller; 469 - #interrupt-cells = <2>; 470 - }; 471 - 472 - gpl0: gpl0 { 473 - gpio-controller; 474 - #gpio-cells = <2>; 475 - 476 - interrupt-controller; 477 - #interrupt-cells = <2>; 478 - }; 479 - 480 - gpl1: gpl1 { 481 - gpio-controller; 482 - #gpio-cells = <2>; 483 - 484 - interrupt-controller; 485 - #interrupt-cells = <2>; 486 - }; 487 - 488 - gpl2: gpl2 { 489 - gpio-controller; 490 - #gpio-cells = <2>; 491 - 492 - interrupt-controller; 493 - #interrupt-cells = <2>; 494 - }; 495 - 496 - gpy0: gpy0 { 497 - gpio-controller; 498 - #gpio-cells = <2>; 499 - }; 500 - 501 - gpy1: gpy1 { 502 - gpio-controller; 503 - #gpio-cells = <2>; 504 - }; 505 - 506 - gpy2: gpy2 { 507 - gpio-controller; 508 - #gpio-cells = <2>; 509 - }; 510 - 511 - gpy3: gpy3 { 512 - gpio-controller; 513 - #gpio-cells = <2>; 514 - }; 515 - 516 - gpy4: gpy4 { 517 - gpio-controller; 518 - #gpio-cells = <2>; 519 - }; 520 - 521 - gpy5: gpy5 { 522 - gpio-controller; 523 - #gpio-cells = <2>; 524 - }; 525 - 526 - gpy6: gpy6 { 527 - gpio-controller; 528 - #gpio-cells = <2>; 529 - }; 530 - 531 - gpx0: gpx0 { 532 - gpio-controller; 533 - #gpio-cells = <2>; 534 - 535 - interrupt-controller; 536 - interrupt-parent = <&gic>; 537 - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 538 - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 539 - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 540 - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 541 - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 542 - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 543 - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 544 - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 545 - #interrupt-cells = <2>; 546 - }; 547 - 548 - gpx1: gpx1 { 549 - gpio-controller; 550 - #gpio-cells = <2>; 551 - 552 - interrupt-controller; 553 - interrupt-parent = <&gic>; 554 - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 555 - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 556 - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 557 - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 558 - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 559 - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 560 - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 561 - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 562 - #interrupt-cells = <2>; 563 - }; 564 - 565 - gpx2: gpx2 { 566 - gpio-controller; 567 - #gpio-cells = <2>; 568 - 569 - interrupt-controller; 570 - #interrupt-cells = <2>; 571 - }; 572 - 573 - gpx3: gpx3 { 574 - gpio-controller; 575 - #gpio-cells = <2>; 576 - 577 - interrupt-controller; 578 - #interrupt-cells = <2>; 579 - }; 580 - 581 - sd0_clk: sd0-clk { 582 - samsung,pins = "gpk0-0"; 583 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 584 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 585 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 586 - }; 587 - 588 - sd0_cmd: sd0-cmd { 589 - samsung,pins = "gpk0-1"; 590 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 591 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 592 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 593 - }; 594 - 595 - sd0_cd: sd0-cd { 596 - samsung,pins = "gpk0-2"; 597 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 598 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 599 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 600 - }; 601 - 602 - sd0_bus1: sd0-bus-width1 { 603 - samsung,pins = "gpk0-3"; 604 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 605 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 606 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 607 - }; 608 - 609 - sd0_bus4: sd0-bus-width4 { 610 - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 611 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 612 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 613 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 614 - }; 615 - 616 - sd0_bus8: sd0-bus-width8 { 617 - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 618 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 619 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 620 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 621 - }; 622 - 623 - sd4_clk: sd4-clk { 624 - samsung,pins = "gpk0-0"; 625 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 626 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 627 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 628 - }; 629 - 630 - sd4_cmd: sd4-cmd { 631 - samsung,pins = "gpk0-1"; 632 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 633 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 634 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 635 - }; 636 - 637 - sd4_cd: sd4-cd { 638 - samsung,pins = "gpk0-2"; 639 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 640 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 641 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 642 - }; 643 - 644 - sd4_bus1: sd4-bus-width1 { 645 - samsung,pins = "gpk0-3"; 646 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 647 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 648 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 649 - }; 650 - 651 - sd4_bus4: sd4-bus-width4 { 652 - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 653 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 654 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 655 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 656 - }; 657 - 658 - sd4_bus8: sd4-bus-width8 { 659 - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 660 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 661 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 662 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 663 - }; 664 - 665 - sd1_clk: sd1-clk { 666 - samsung,pins = "gpk1-0"; 667 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 668 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 669 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 670 - }; 671 - 672 - sd1_cmd: sd1-cmd { 673 - samsung,pins = "gpk1-1"; 674 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 675 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 676 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 677 - }; 678 - 679 - sd1_cd: sd1-cd { 680 - samsung,pins = "gpk1-2"; 681 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 682 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 683 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 684 - }; 685 - 686 - sd1_bus1: sd1-bus-width1 { 687 - samsung,pins = "gpk1-3"; 688 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 689 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 690 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 691 - }; 692 - 693 - sd1_bus4: sd1-bus-width4 { 694 - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 695 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 696 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 697 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 698 - }; 699 - 700 - sd2_clk: sd2-clk { 701 - samsung,pins = "gpk2-0"; 702 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 703 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 704 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 705 - }; 706 - 707 - sd2_cmd: sd2-cmd { 708 - samsung,pins = "gpk2-1"; 709 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 710 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 711 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 712 - }; 713 - 714 - sd2_cd: sd2-cd { 715 - samsung,pins = "gpk2-2"; 716 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 717 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 718 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 719 - }; 720 - 721 - sd2_bus1: sd2-bus-width1 { 722 - samsung,pins = "gpk2-3"; 723 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 724 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 725 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 726 - }; 727 - 728 - sd2_bus4: sd2-bus-width4 { 729 - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; 730 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 731 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 732 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 733 - }; 734 - 735 - sd2_bus8: sd2-bus-width8 { 736 - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 737 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 738 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 739 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 740 - }; 741 - 742 - sd3_clk: sd3-clk { 743 - samsung,pins = "gpk3-0"; 744 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 745 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 746 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 747 - }; 748 - 749 - sd3_cmd: sd3-cmd { 750 - samsung,pins = "gpk3-1"; 751 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 752 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 753 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 754 - }; 755 - 756 - sd3_cd: sd3-cd { 757 - samsung,pins = "gpk3-2"; 758 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 759 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 760 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 761 - }; 762 - 763 - sd3_bus1: sd3-bus-width1 { 764 - samsung,pins = "gpk3-3"; 765 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 766 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 767 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 768 - }; 769 - 770 - sd3_bus4: sd3-bus-width4 { 771 - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 772 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 773 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 774 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 775 - }; 776 - 777 - eint0: ext-int0 { 778 - samsung,pins = "gpx0-0"; 779 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 780 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 781 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 782 - }; 783 - 784 - eint8: ext-int8 { 785 - samsung,pins = "gpx1-0"; 786 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 787 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 788 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 789 - }; 790 - 791 - eint15: ext-int15 { 792 - samsung,pins = "gpx1-7"; 793 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 794 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 795 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 796 - }; 797 - 798 - eint16: ext-int16 { 799 - samsung,pins = "gpx2-0"; 800 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 801 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 802 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 803 - }; 804 - 805 - eint31: ext-int31 { 806 - samsung,pins = "gpx3-7"; 807 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 808 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 809 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 810 - }; 811 - 812 - cam_port_a_io: cam-port-a-io { 813 - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", 814 - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", 815 - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; 816 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 817 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 818 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 819 - }; 820 - 821 - cam_port_a_clk_active: cam-port-a-clk-active { 822 - samsung,pins = "gpj1-3"; 823 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 824 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 825 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 826 - }; 827 - 828 - cam_port_a_clk_idle: cam-port-a-clk-idle { 829 - samsung,pins = "gpj1-3"; 830 - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 831 - samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 832 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 833 - }; 834 - 835 - hdmi_cec: hdmi-cec { 836 - samsung,pins = "gpx3-6"; 837 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 838 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 839 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 840 - }; 25 + gpa1: gpa1 { 26 + gpio-controller; 27 + #gpio-cells = <2>; 28 + 29 + interrupt-controller; 30 + #interrupt-cells = <2>; 841 31 }; 842 32 843 - pinctrl@3860000 { 844 - gpz: gpz { 845 - gpio-controller; 846 - #gpio-cells = <2>; 847 - }; 33 + gpb: gpb { 34 + gpio-controller; 35 + #gpio-cells = <2>; 848 36 849 - i2s0_bus: i2s0-bus { 850 - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", 851 - "gpz-4", "gpz-5", "gpz-6"; 852 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 853 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 854 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 855 - }; 37 + interrupt-controller; 38 + #interrupt-cells = <2>; 39 + }; 856 40 857 - pcm0_bus: pcm0-bus { 858 - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", 859 - "gpz-4"; 860 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 861 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 862 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 863 - }; 41 + gpc0: gpc0 { 42 + gpio-controller; 43 + #gpio-cells = <2>; 44 + 45 + interrupt-controller; 46 + #interrupt-cells = <2>; 47 + }; 48 + 49 + gpc1: gpc1 { 50 + gpio-controller; 51 + #gpio-cells = <2>; 52 + 53 + interrupt-controller; 54 + #interrupt-cells = <2>; 55 + }; 56 + 57 + gpd0: gpd0 { 58 + gpio-controller; 59 + #gpio-cells = <2>; 60 + 61 + interrupt-controller; 62 + #interrupt-cells = <2>; 63 + }; 64 + 65 + gpd1: gpd1 { 66 + gpio-controller; 67 + #gpio-cells = <2>; 68 + 69 + interrupt-controller; 70 + #interrupt-cells = <2>; 71 + }; 72 + 73 + gpe0: gpe0 { 74 + gpio-controller; 75 + #gpio-cells = <2>; 76 + 77 + interrupt-controller; 78 + #interrupt-cells = <2>; 79 + }; 80 + 81 + gpe1: gpe1 { 82 + gpio-controller; 83 + #gpio-cells = <2>; 84 + 85 + interrupt-controller; 86 + #interrupt-cells = <2>; 87 + }; 88 + 89 + gpe2: gpe2 { 90 + gpio-controller; 91 + #gpio-cells = <2>; 92 + 93 + interrupt-controller; 94 + #interrupt-cells = <2>; 95 + }; 96 + 97 + gpe3: gpe3 { 98 + gpio-controller; 99 + #gpio-cells = <2>; 100 + 101 + interrupt-controller; 102 + #interrupt-cells = <2>; 103 + }; 104 + 105 + gpe4: gpe4 { 106 + gpio-controller; 107 + #gpio-cells = <2>; 108 + 109 + interrupt-controller; 110 + #interrupt-cells = <2>; 111 + }; 112 + 113 + gpf0: gpf0 { 114 + gpio-controller; 115 + #gpio-cells = <2>; 116 + 117 + interrupt-controller; 118 + #interrupt-cells = <2>; 119 + }; 120 + 121 + gpf1: gpf1 { 122 + gpio-controller; 123 + #gpio-cells = <2>; 124 + 125 + interrupt-controller; 126 + #interrupt-cells = <2>; 127 + }; 128 + 129 + gpf2: gpf2 { 130 + gpio-controller; 131 + #gpio-cells = <2>; 132 + 133 + interrupt-controller; 134 + #interrupt-cells = <2>; 135 + }; 136 + 137 + gpf3: gpf3 { 138 + gpio-controller; 139 + #gpio-cells = <2>; 140 + 141 + interrupt-controller; 142 + #interrupt-cells = <2>; 143 + }; 144 + 145 + uart0_data: uart0-data { 146 + samsung,pins = "gpa0-0", "gpa0-1"; 147 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 148 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 149 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 150 + }; 151 + 152 + uart0_fctl: uart0-fctl { 153 + samsung,pins = "gpa0-2", "gpa0-3"; 154 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 155 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 156 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 157 + }; 158 + 159 + uart1_data: uart1-data { 160 + samsung,pins = "gpa0-4", "gpa0-5"; 161 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 162 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 163 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 164 + }; 165 + 166 + uart1_fctl: uart1-fctl { 167 + samsung,pins = "gpa0-6", "gpa0-7"; 168 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 169 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 170 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 171 + }; 172 + 173 + i2c2_bus: i2c2-bus { 174 + samsung,pins = "gpa0-6", "gpa0-7"; 175 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 176 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 177 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 178 + }; 179 + 180 + uart2_data: uart2-data { 181 + samsung,pins = "gpa1-0", "gpa1-1"; 182 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 183 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 184 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 185 + }; 186 + 187 + uart2_fctl: uart2-fctl { 188 + samsung,pins = "gpa1-2", "gpa1-3"; 189 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 190 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 191 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 192 + }; 193 + 194 + uart_audio_a: uart-audio-a { 195 + samsung,pins = "gpa1-0", "gpa1-1"; 196 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 197 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 198 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 199 + }; 200 + 201 + i2c3_bus: i2c3-bus { 202 + samsung,pins = "gpa1-2", "gpa1-3"; 203 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 204 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 205 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 206 + }; 207 + 208 + uart3_data: uart3-data { 209 + samsung,pins = "gpa1-4", "gpa1-5"; 210 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 211 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 212 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 213 + }; 214 + 215 + uart_audio_b: uart-audio-b { 216 + samsung,pins = "gpa1-4", "gpa1-5"; 217 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 218 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 219 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 220 + }; 221 + 222 + spi0_bus: spi0-bus { 223 + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; 224 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 225 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 226 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 227 + }; 228 + 229 + i2c4_bus: i2c4-bus { 230 + samsung,pins = "gpb-2", "gpb-3"; 231 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 232 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 233 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 234 + }; 235 + 236 + spi1_bus: spi1-bus { 237 + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; 238 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 239 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 240 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 241 + }; 242 + 243 + i2c5_bus: i2c5-bus { 244 + samsung,pins = "gpb-6", "gpb-7"; 245 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 246 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 247 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 248 + }; 249 + 250 + i2s1_bus: i2s1-bus { 251 + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 252 + "gpc0-4"; 253 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 254 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 255 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 256 + }; 257 + 258 + pcm1_bus: pcm1-bus { 259 + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 260 + "gpc0-4"; 261 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 262 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 263 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 264 + }; 265 + 266 + ac97_bus: ac97-bus { 267 + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 268 + "gpc0-4"; 269 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 270 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 271 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 272 + }; 273 + 274 + i2s2_bus: i2s2-bus { 275 + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", 276 + "gpc1-4"; 277 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 278 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 279 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 280 + }; 281 + 282 + pcm2_bus: pcm2-bus { 283 + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", 284 + "gpc1-4"; 285 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 286 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 287 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 288 + }; 289 + 290 + spdif_bus: spdif-bus { 291 + samsung,pins = "gpc1-0", "gpc1-1"; 292 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 293 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 294 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 295 + }; 296 + 297 + i2c6_bus: i2c6-bus { 298 + samsung,pins = "gpc1-3", "gpc1-4"; 299 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 300 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 301 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 302 + }; 303 + 304 + spi2_bus: spi2-bus { 305 + samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; 306 + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; 307 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 308 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 309 + }; 310 + 311 + i2c7_bus: i2c7-bus { 312 + samsung,pins = "gpd0-2", "gpd0-3"; 313 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 314 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 315 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 316 + }; 317 + 318 + i2c0_bus: i2c0-bus { 319 + samsung,pins = "gpd1-0", "gpd1-1"; 320 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 321 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 322 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 323 + }; 324 + 325 + i2c1_bus: i2c1-bus { 326 + samsung,pins = "gpd1-2", "gpd1-3"; 327 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 328 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 329 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 330 + }; 331 + 332 + pwm0_out: pwm0-out { 333 + samsung,pins = "gpd0-0"; 334 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 335 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 336 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 337 + }; 338 + 339 + pwm1_out: pwm1-out { 340 + samsung,pins = "gpd0-1"; 341 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 342 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 343 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 344 + }; 345 + 346 + pwm2_out: pwm2-out { 347 + samsung,pins = "gpd0-2"; 348 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 349 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 350 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 351 + }; 352 + 353 + pwm3_out: pwm3-out { 354 + samsung,pins = "gpd0-3"; 355 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 356 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 357 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 358 + }; 359 + 360 + lcd_ctrl: lcd-ctrl { 361 + samsung,pins = "gpd0-0", "gpd0-1"; 362 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 363 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 364 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 365 + }; 366 + 367 + lcd_sync: lcd-sync { 368 + samsung,pins = "gpf0-0", "gpf0-1"; 369 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 370 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 371 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 372 + }; 373 + 374 + lcd_en: lcd-en { 375 + samsung,pins = "gpe3-4"; 376 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 377 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 378 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 379 + }; 380 + 381 + lcd_clk: lcd-clk { 382 + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; 383 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 384 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 385 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 386 + }; 387 + 388 + lcd_data16: lcd-data-width16 { 389 + samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", 390 + "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", 391 + "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", 392 + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; 393 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 394 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 395 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 396 + }; 397 + 398 + lcd_data18: lcd-data-width18 { 399 + samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", 400 + "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", 401 + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", 402 + "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", 403 + "gpf3-2", "gpf3-3"; 404 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 405 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 406 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 407 + }; 408 + 409 + lcd_data24: lcd-data-width24 { 410 + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", 411 + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", 412 + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", 413 + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", 414 + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", 415 + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; 416 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 417 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 418 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 419 + }; 420 + }; 421 + 422 + &pinctrl_1 { 423 + gpj0: gpj0 { 424 + gpio-controller; 425 + #gpio-cells = <2>; 426 + 427 + interrupt-controller; 428 + #interrupt-cells = <2>; 429 + }; 430 + 431 + gpj1: gpj1 { 432 + gpio-controller; 433 + #gpio-cells = <2>; 434 + 435 + interrupt-controller; 436 + #interrupt-cells = <2>; 437 + }; 438 + 439 + gpk0: gpk0 { 440 + gpio-controller; 441 + #gpio-cells = <2>; 442 + 443 + interrupt-controller; 444 + #interrupt-cells = <2>; 445 + }; 446 + 447 + gpk1: gpk1 { 448 + gpio-controller; 449 + #gpio-cells = <2>; 450 + 451 + interrupt-controller; 452 + #interrupt-cells = <2>; 453 + }; 454 + 455 + gpk2: gpk2 { 456 + gpio-controller; 457 + #gpio-cells = <2>; 458 + 459 + interrupt-controller; 460 + #interrupt-cells = <2>; 461 + }; 462 + 463 + gpk3: gpk3 { 464 + gpio-controller; 465 + #gpio-cells = <2>; 466 + 467 + interrupt-controller; 468 + #interrupt-cells = <2>; 469 + }; 470 + 471 + gpl0: gpl0 { 472 + gpio-controller; 473 + #gpio-cells = <2>; 474 + 475 + interrupt-controller; 476 + #interrupt-cells = <2>; 477 + }; 478 + 479 + gpl1: gpl1 { 480 + gpio-controller; 481 + #gpio-cells = <2>; 482 + 483 + interrupt-controller; 484 + #interrupt-cells = <2>; 485 + }; 486 + 487 + gpl2: gpl2 { 488 + gpio-controller; 489 + #gpio-cells = <2>; 490 + 491 + interrupt-controller; 492 + #interrupt-cells = <2>; 493 + }; 494 + 495 + gpy0: gpy0 { 496 + gpio-controller; 497 + #gpio-cells = <2>; 498 + }; 499 + 500 + gpy1: gpy1 { 501 + gpio-controller; 502 + #gpio-cells = <2>; 503 + }; 504 + 505 + gpy2: gpy2 { 506 + gpio-controller; 507 + #gpio-cells = <2>; 508 + }; 509 + 510 + gpy3: gpy3 { 511 + gpio-controller; 512 + #gpio-cells = <2>; 513 + }; 514 + 515 + gpy4: gpy4 { 516 + gpio-controller; 517 + #gpio-cells = <2>; 518 + }; 519 + 520 + gpy5: gpy5 { 521 + gpio-controller; 522 + #gpio-cells = <2>; 523 + }; 524 + 525 + gpy6: gpy6 { 526 + gpio-controller; 527 + #gpio-cells = <2>; 528 + }; 529 + 530 + gpx0: gpx0 { 531 + gpio-controller; 532 + #gpio-cells = <2>; 533 + 534 + interrupt-controller; 535 + interrupt-parent = <&gic>; 536 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 537 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 538 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 539 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 540 + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 541 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 542 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 543 + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 544 + #interrupt-cells = <2>; 545 + }; 546 + 547 + gpx1: gpx1 { 548 + gpio-controller; 549 + #gpio-cells = <2>; 550 + 551 + interrupt-controller; 552 + interrupt-parent = <&gic>; 553 + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 554 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 555 + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 556 + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 557 + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 558 + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 559 + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 560 + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 561 + #interrupt-cells = <2>; 562 + }; 563 + 564 + gpx2: gpx2 { 565 + gpio-controller; 566 + #gpio-cells = <2>; 567 + 568 + interrupt-controller; 569 + #interrupt-cells = <2>; 570 + }; 571 + 572 + gpx3: gpx3 { 573 + gpio-controller; 574 + #gpio-cells = <2>; 575 + 576 + interrupt-controller; 577 + #interrupt-cells = <2>; 578 + }; 579 + 580 + sd0_clk: sd0-clk { 581 + samsung,pins = "gpk0-0"; 582 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 583 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 584 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 585 + }; 586 + 587 + sd0_cmd: sd0-cmd { 588 + samsung,pins = "gpk0-1"; 589 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 590 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 591 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 592 + }; 593 + 594 + sd0_cd: sd0-cd { 595 + samsung,pins = "gpk0-2"; 596 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 597 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 598 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 599 + }; 600 + 601 + sd0_bus1: sd0-bus-width1 { 602 + samsung,pins = "gpk0-3"; 603 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 604 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 605 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 606 + }; 607 + 608 + sd0_bus4: sd0-bus-width4 { 609 + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 610 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 611 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 612 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 613 + }; 614 + 615 + sd0_bus8: sd0-bus-width8 { 616 + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 617 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 618 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 619 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 620 + }; 621 + 622 + sd4_clk: sd4-clk { 623 + samsung,pins = "gpk0-0"; 624 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 625 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 626 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 627 + }; 628 + 629 + sd4_cmd: sd4-cmd { 630 + samsung,pins = "gpk0-1"; 631 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 632 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 633 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 634 + }; 635 + 636 + sd4_cd: sd4-cd { 637 + samsung,pins = "gpk0-2"; 638 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 639 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 640 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 641 + }; 642 + 643 + sd4_bus1: sd4-bus-width1 { 644 + samsung,pins = "gpk0-3"; 645 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 646 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 647 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 648 + }; 649 + 650 + sd4_bus4: sd4-bus-width4 { 651 + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 652 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 653 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 654 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 655 + }; 656 + 657 + sd4_bus8: sd4-bus-width8 { 658 + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 659 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 660 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 661 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 662 + }; 663 + 664 + sd1_clk: sd1-clk { 665 + samsung,pins = "gpk1-0"; 666 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 667 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 668 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 669 + }; 670 + 671 + sd1_cmd: sd1-cmd { 672 + samsung,pins = "gpk1-1"; 673 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 674 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 675 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 676 + }; 677 + 678 + sd1_cd: sd1-cd { 679 + samsung,pins = "gpk1-2"; 680 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 681 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 682 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 683 + }; 684 + 685 + sd1_bus1: sd1-bus-width1 { 686 + samsung,pins = "gpk1-3"; 687 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 688 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 689 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 690 + }; 691 + 692 + sd1_bus4: sd1-bus-width4 { 693 + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 694 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 695 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 696 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 697 + }; 698 + 699 + sd2_clk: sd2-clk { 700 + samsung,pins = "gpk2-0"; 701 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 702 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 703 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 704 + }; 705 + 706 + sd2_cmd: sd2-cmd { 707 + samsung,pins = "gpk2-1"; 708 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 709 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 710 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 711 + }; 712 + 713 + sd2_cd: sd2-cd { 714 + samsung,pins = "gpk2-2"; 715 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 716 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 717 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 718 + }; 719 + 720 + sd2_bus1: sd2-bus-width1 { 721 + samsung,pins = "gpk2-3"; 722 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 723 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 724 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 725 + }; 726 + 727 + sd2_bus4: sd2-bus-width4 { 728 + samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; 729 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 730 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 731 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 732 + }; 733 + 734 + sd2_bus8: sd2-bus-width8 { 735 + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 736 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 737 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 738 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 739 + }; 740 + 741 + sd3_clk: sd3-clk { 742 + samsung,pins = "gpk3-0"; 743 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 744 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 745 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 746 + }; 747 + 748 + sd3_cmd: sd3-cmd { 749 + samsung,pins = "gpk3-1"; 750 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 751 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 752 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 753 + }; 754 + 755 + sd3_cd: sd3-cd { 756 + samsung,pins = "gpk3-2"; 757 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 758 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 759 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 760 + }; 761 + 762 + sd3_bus1: sd3-bus-width1 { 763 + samsung,pins = "gpk3-3"; 764 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 765 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 766 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 767 + }; 768 + 769 + sd3_bus4: sd3-bus-width4 { 770 + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 771 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 772 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 773 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 774 + }; 775 + 776 + eint0: ext-int0 { 777 + samsung,pins = "gpx0-0"; 778 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 779 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 780 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 781 + }; 782 + 783 + eint8: ext-int8 { 784 + samsung,pins = "gpx1-0"; 785 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 786 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 787 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 788 + }; 789 + 790 + eint15: ext-int15 { 791 + samsung,pins = "gpx1-7"; 792 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 793 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 794 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 795 + }; 796 + 797 + eint16: ext-int16 { 798 + samsung,pins = "gpx2-0"; 799 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 800 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 801 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 802 + }; 803 + 804 + eint31: ext-int31 { 805 + samsung,pins = "gpx3-7"; 806 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 807 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 808 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 809 + }; 810 + 811 + cam_port_a_io: cam-port-a-io { 812 + samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", 813 + "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", 814 + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; 815 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 816 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 817 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 818 + }; 819 + 820 + cam_port_a_clk_active: cam-port-a-clk-active { 821 + samsung,pins = "gpj1-3"; 822 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 823 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 824 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 825 + }; 826 + 827 + cam_port_a_clk_idle: cam-port-a-clk-idle { 828 + samsung,pins = "gpj1-3"; 829 + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 830 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 831 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 832 + }; 833 + 834 + hdmi_cec: hdmi-cec { 835 + samsung,pins = "gpx3-6"; 836 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 837 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 838 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 839 + }; 840 + }; 841 + 842 + &pinctrl_2 { 843 + gpz: gpz { 844 + gpio-controller; 845 + #gpio-cells = <2>; 846 + }; 847 + 848 + i2s0_bus: i2s0-bus { 849 + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", 850 + "gpz-4", "gpz-5", "gpz-6"; 851 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 852 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 853 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 854 + }; 855 + 856 + pcm0_bus: pcm0-bus { 857 + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", 858 + "gpz-4"; 859 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 860 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 861 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 864 862 }; 865 863 };
+38 -36
arch/arm/boot/dts/exynos4210-trats.dts
··· 148 148 }; 149 149 }; 150 150 151 - camera { 152 - pinctrl-names = "default"; 153 - pinctrl-0 = <>; 154 - status = "okay"; 151 + }; 155 152 156 - fimc_0: fimc@11800000 { 157 - status = "okay"; 158 - assigned-clocks = <&clock CLK_MOUT_FIMC0>, 159 - <&clock CLK_SCLK_FIMC0>; 160 - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 161 - assigned-clock-rates = <0>, <160000000>; 162 - }; 163 - 164 - fimc_1: fimc@11810000 { 165 - status = "okay"; 166 - assigned-clocks = <&clock CLK_MOUT_FIMC1>, 167 - <&clock CLK_SCLK_FIMC1>; 168 - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 169 - assigned-clock-rates = <0>, <160000000>; 170 - }; 171 - 172 - fimc_2: fimc@11820000 { 173 - status = "okay"; 174 - assigned-clocks = <&clock CLK_MOUT_FIMC2>, 175 - <&clock CLK_SCLK_FIMC2>; 176 - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 177 - assigned-clock-rates = <0>, <160000000>; 178 - }; 179 - 180 - fimc_3: fimc@11830000 { 181 - status = "okay"; 182 - assigned-clocks = <&clock CLK_MOUT_FIMC3>, 183 - <&clock CLK_SCLK_FIMC3>; 184 - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 185 - assigned-clock-rates = <0>, <160000000>; 186 - }; 187 - }; 153 + &camera { 154 + pinctrl-names = "default"; 155 + pinctrl-0 = <>; 156 + status = "okay"; 188 157 }; 189 158 190 159 &cpu0 { ··· 203 234 vbus-supply = <&safe1_sreg>; 204 235 }; 205 236 237 + &fimc_0 { 238 + status = "okay"; 239 + assigned-clocks = <&clock CLK_MOUT_FIMC0>, 240 + <&clock CLK_SCLK_FIMC0>; 241 + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 242 + assigned-clock-rates = <0>, <160000000>; 243 + }; 244 + 245 + &fimc_1 { 246 + status = "okay"; 247 + assigned-clocks = <&clock CLK_MOUT_FIMC1>, 248 + <&clock CLK_SCLK_FIMC1>; 249 + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 250 + assigned-clock-rates = <0>, <160000000>; 251 + }; 252 + 253 + &fimc_2 { 254 + status = "okay"; 255 + assigned-clocks = <&clock CLK_MOUT_FIMC2>, 256 + <&clock CLK_SCLK_FIMC2>; 257 + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 258 + assigned-clock-rates = <0>, <160000000>; 259 + }; 260 + 261 + &fimc_3 { 262 + status = "okay"; 263 + assigned-clocks = <&clock CLK_MOUT_FIMC3>, 264 + <&clock CLK_SCLK_FIMC3>; 265 + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 266 + assigned-clock-rates = <0>, <160000000>; 267 + }; 268 + 206 269 &fimd { 207 270 status = "okay"; 208 271 }; ··· 276 275 277 276 max8997_pmic@66 { 278 277 compatible = "maxim,max8997-pmic"; 278 + interrupts-extended = <&gpx0 7 0>, <&gpx2 3 0>; 279 279 280 280 reg = <0x66>; 281 281 interrupt-parent = <&gpx0>;
+58 -57
arch/arm/boot/dts/exynos4210-universal_c210.dts
··· 28 28 stdout-path = &serial_2; 29 29 }; 30 30 31 - sysram@2020000 { 32 - smp-sysram@0 { 33 - status = "disabled"; 34 - }; 35 - 36 - smp-sysram@5000 { 37 - compatible = "samsung,exynos4210-sysram"; 38 - reg = <0x5000 0x1000>; 39 - }; 40 - 41 - smp-sysram@1f000 { 42 - status = "disabled"; 43 - }; 44 - }; 45 - 46 - mct@10050000 { 47 - compatible = "none"; 48 - }; 49 31 50 32 fixed-rate-clocks { 51 33 xxti { ··· 155 173 }; 156 174 }; 157 175 158 - camera { 159 - status = "okay"; 160 - 161 - pinctrl-names = "default"; 162 - pinctrl-0 = <>; 163 - 164 - fimc_0: fimc@11800000 { 165 - status = "okay"; 166 - assigned-clocks = <&clock CLK_MOUT_FIMC0>, 167 - <&clock CLK_SCLK_FIMC0>; 168 - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 169 - assigned-clock-rates = <0>, <160000000>; 170 - }; 171 - 172 - fimc_1: fimc@11810000 { 173 - status = "okay"; 174 - assigned-clocks = <&clock CLK_MOUT_FIMC1>, 175 - <&clock CLK_SCLK_FIMC1>; 176 - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 177 - assigned-clock-rates = <0>, <160000000>; 178 - }; 179 - 180 - fimc_2: fimc@11820000 { 181 - status = "okay"; 182 - assigned-clocks = <&clock CLK_MOUT_FIMC2>, 183 - <&clock CLK_SCLK_FIMC2>; 184 - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 185 - assigned-clock-rates = <0>, <160000000>; 186 - }; 187 - 188 - fimc_3: fimc@11830000 { 189 - status = "okay"; 190 - assigned-clocks = <&clock CLK_MOUT_FIMC3>, 191 - <&clock CLK_SCLK_FIMC3>; 192 - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 193 - assigned-clock-rates = <0>, <160000000>; 194 - }; 195 - }; 196 - 197 176 hdmi_en: voltage-regulator-hdmi-5v { 198 177 compatible = "regulator-fixed"; 199 178 regulator-name = "HDMI_5V"; ··· 177 234 }; 178 235 }; 179 236 237 + &camera { 238 + status = "okay"; 239 + 240 + pinctrl-names = "default"; 241 + pinctrl-0 = <>; 242 + }; 243 + 180 244 &cpu0 { 181 245 cpu0-supply = <&vdd_arm_reg>; 182 246 }; ··· 198 248 &exynos_usbphy { 199 249 status = "okay"; 200 250 vbus-supply = <&safeout1_reg>; 251 + }; 252 + 253 + &fimc_0 { 254 + status = "okay"; 255 + assigned-clocks = <&clock CLK_MOUT_FIMC0>, 256 + <&clock CLK_SCLK_FIMC0>; 257 + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 258 + assigned-clock-rates = <0>, <160000000>; 259 + }; 260 + 261 + &fimc_1 { 262 + status = "okay"; 263 + assigned-clocks = <&clock CLK_MOUT_FIMC1>, 264 + <&clock CLK_SCLK_FIMC1>; 265 + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 266 + assigned-clock-rates = <0>, <160000000>; 267 + }; 268 + 269 + &fimc_2 { 270 + status = "okay"; 271 + assigned-clocks = <&clock CLK_MOUT_FIMC2>, 272 + <&clock CLK_SCLK_FIMC2>; 273 + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 274 + assigned-clock-rates = <0>, <160000000>; 275 + }; 276 + 277 + &fimc_3 { 278 + status = "okay"; 279 + assigned-clocks = <&clock CLK_MOUT_FIMC3>, 280 + <&clock CLK_SCLK_FIMC3>; 281 + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 282 + assigned-clock-rates = <0>, <160000000>; 201 283 }; 202 284 203 285 &fimd { ··· 483 501 status = "okay"; 484 502 }; 485 503 504 + &mct { 505 + compatible = "none"; 506 + }; 507 + 486 508 &mdma1 { 487 509 reg = <0x12840000 0x1000>; 488 510 }; ··· 564 578 status = "okay"; 565 579 /delete-property/dmas; 566 580 /delete-property/dma-names; 581 + }; 582 + 583 + &sysram { 584 + smp-sysram@0 { 585 + status = "disabled"; 586 + }; 587 + 588 + smp-sysram@5000 { 589 + compatible = "samsung,exynos4210-sysram"; 590 + reg = <0x5000 0x1000>; 591 + }; 592 + 593 + smp-sysram@1f000 { 594 + status = "disabled"; 595 + }; 567 596 };
+339 -335
arch/arm/boot/dts/exynos4210.dtsi
··· 17 17 */ 18 18 19 19 #include "exynos4.dtsi" 20 - #include "exynos4210-pinctrl.dtsi" 21 20 #include "exynos4-cpu-thermal.dtsi" 22 21 23 22 / { ··· 48 49 400000 975000 49 50 200000 950000 50 51 >; 51 - cooling-min-level = <4>; 52 - cooling-max-level = <2>; 53 52 #cooling-cells = <2>; /* min followed by max */ 54 53 }; 55 54 ··· 58 61 }; 59 62 }; 60 63 61 - sysram: sysram@2020000 { 62 - compatible = "mmio-sram"; 63 - reg = <0x02020000 0x20000>; 64 - #address-cells = <1>; 65 - #size-cells = <1>; 66 - ranges = <0 0x02020000 0x20000>; 64 + soc: soc { 65 + sysram: sysram@2020000 { 66 + compatible = "mmio-sram"; 67 + reg = <0x02020000 0x20000>; 68 + #address-cells = <1>; 69 + #size-cells = <1>; 70 + ranges = <0 0x02020000 0x20000>; 67 71 68 - smp-sysram@0 { 69 - compatible = "samsung,exynos4210-sysram"; 70 - reg = <0x0 0x1000>; 72 + smp-sysram@0 { 73 + compatible = "samsung,exynos4210-sysram"; 74 + reg = <0x0 0x1000>; 75 + }; 76 + 77 + smp-sysram@1f000 { 78 + compatible = "samsung,exynos4210-sysram-ns"; 79 + reg = <0x1f000 0x1000>; 80 + }; 71 81 }; 72 82 73 - smp-sysram@1f000 { 74 - compatible = "samsung,exynos4210-sysram-ns"; 75 - reg = <0x1f000 0x1000>; 83 + pd_lcd1: lcd1-power-domain@10023ca0 { 84 + compatible = "samsung,exynos4210-pd"; 85 + reg = <0x10023CA0 0x20>; 86 + #power-domain-cells = <0>; 87 + label = "LCD1"; 76 88 }; 77 - }; 78 89 79 - pd_lcd1: lcd1-power-domain@10023ca0 { 80 - compatible = "samsung,exynos4210-pd"; 81 - reg = <0x10023CA0 0x20>; 82 - #power-domain-cells = <0>; 83 - label = "LCD1"; 84 - }; 90 + l2c: l2-cache-controller@10502000 { 91 + compatible = "arm,pl310-cache"; 92 + reg = <0x10502000 0x1000>; 93 + cache-unified; 94 + cache-level = <2>; 95 + arm,tag-latency = <2 2 1>; 96 + arm,data-latency = <2 2 1>; 97 + }; 85 98 86 - l2c: l2-cache-controller@10502000 { 87 - compatible = "arm,pl310-cache"; 88 - reg = <0x10502000 0x1000>; 89 - cache-unified; 90 - cache-level = <2>; 91 - arm,tag-latency = <2 2 1>; 92 - arm,data-latency = <2 2 1>; 93 - }; 99 + mct: mct@10050000 { 100 + compatible = "samsung,exynos4210-mct"; 101 + reg = <0x10050000 0x800>; 102 + interrupt-parent = <&mct_map>; 103 + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 104 + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 105 + clock-names = "fin_pll", "mct"; 94 106 95 - mct: mct@10050000 { 96 - compatible = "samsung,exynos4210-mct"; 97 - reg = <0x10050000 0x800>; 98 - interrupt-parent = <&mct_map>; 99 - interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 100 - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 101 - clock-names = "fin_pll", "mct"; 102 - 103 - mct_map: mct-map { 104 - #interrupt-cells = <1>; 105 - #address-cells = <0>; 106 - #size-cells = <0>; 107 - interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 107 + mct_map: mct-map { 108 + #interrupt-cells = <1>; 109 + #address-cells = <0>; 110 + #size-cells = <0>; 111 + interrupt-map = 112 + <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 108 113 <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, 109 114 <2 &combiner 12 6>, 110 115 <3 &combiner 12 7>, 111 116 <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>, 112 117 <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>; 118 + }; 113 119 }; 114 - }; 115 120 116 - watchdog: watchdog@10060000 { 117 - compatible = "samsung,s3c6410-wdt"; 118 - reg = <0x10060000 0x100>; 119 - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 120 - clocks = <&clock CLK_WDT>; 121 - clock-names = "watchdog"; 122 - }; 123 - 124 - clock: clock-controller@10030000 { 125 - compatible = "samsung,exynos4210-clock"; 126 - reg = <0x10030000 0x20000>; 127 - #clock-cells = <1>; 128 - }; 129 - 130 - pinctrl_0: pinctrl@11400000 { 131 - compatible = "samsung,exynos4210-pinctrl"; 132 - reg = <0x11400000 0x1000>; 133 - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 134 - }; 135 - 136 - pinctrl_1: pinctrl@11000000 { 137 - compatible = "samsung,exynos4210-pinctrl"; 138 - reg = <0x11000000 0x1000>; 139 - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 140 - 141 - wakup_eint: wakeup-interrupt-controller { 142 - compatible = "samsung,exynos4210-wakeup-eint"; 143 - interrupt-parent = <&gic>; 144 - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 121 + watchdog: watchdog@10060000 { 122 + compatible = "samsung,s3c6410-wdt"; 123 + reg = <0x10060000 0x100>; 124 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 125 + clocks = <&clock CLK_WDT>; 126 + clock-names = "watchdog"; 145 127 }; 146 - }; 147 128 148 - pinctrl_2: pinctrl@3860000 { 149 - compatible = "samsung,exynos4210-pinctrl"; 150 - reg = <0x03860000 0x1000>; 151 - }; 129 + clock: clock-controller@10030000 { 130 + compatible = "samsung,exynos4210-clock"; 131 + reg = <0x10030000 0x20000>; 132 + #clock-cells = <1>; 133 + }; 152 134 153 - tmu: tmu@100c0000 { 154 - compatible = "samsung,exynos4210-tmu"; 155 - interrupt-parent = <&combiner>; 156 - reg = <0x100C0000 0x100>; 157 - interrupts = <2 4>; 158 - clocks = <&clock CLK_TMU_APBIF>; 159 - clock-names = "tmu_apbif"; 160 - samsung,tmu_gain = <15>; 161 - samsung,tmu_reference_voltage = <7>; 162 - status = "disabled"; 135 + pinctrl_0: pinctrl@11400000 { 136 + compatible = "samsung,exynos4210-pinctrl"; 137 + reg = <0x11400000 0x1000>; 138 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 139 + }; 140 + 141 + pinctrl_1: pinctrl@11000000 { 142 + compatible = "samsung,exynos4210-pinctrl"; 143 + reg = <0x11000000 0x1000>; 144 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 145 + 146 + wakup_eint: wakeup-interrupt-controller { 147 + compatible = "samsung,exynos4210-wakeup-eint"; 148 + interrupt-parent = <&gic>; 149 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 150 + }; 151 + }; 152 + 153 + pinctrl_2: pinctrl@3860000 { 154 + compatible = "samsung,exynos4210-pinctrl"; 155 + reg = <0x03860000 0x1000>; 156 + }; 157 + 158 + g2d: g2d@12800000 { 159 + compatible = "samsung,s5pv210-g2d"; 160 + reg = <0x12800000 0x1000>; 161 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 162 + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 163 + clock-names = "sclk_fimg2d", "fimg2d"; 164 + power-domains = <&pd_lcd0>; 165 + iommus = <&sysmmu_g2d>; 166 + }; 167 + 168 + ppmu_acp: ppmu_acp@10ae0000 { 169 + compatible = "samsung,exynos-ppmu"; 170 + reg = <0x10ae0000 0x2000>; 171 + status = "disabled"; 172 + }; 173 + 174 + ppmu_lcd1: ppmu_lcd1@12240000 { 175 + compatible = "samsung,exynos-ppmu"; 176 + reg = <0x12240000 0x2000>; 177 + clocks = <&clock CLK_PPMULCD1>; 178 + clock-names = "ppmu"; 179 + status = "disabled"; 180 + }; 181 + 182 + sysmmu_g2d: sysmmu@12a20000 { 183 + compatible = "samsung,exynos-sysmmu"; 184 + reg = <0x12A20000 0x1000>; 185 + interrupt-parent = <&combiner>; 186 + interrupts = <4 7>; 187 + clock-names = "sysmmu", "master"; 188 + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 189 + power-domains = <&pd_lcd0>; 190 + #iommu-cells = <0>; 191 + }; 192 + 193 + sysmmu_fimd1: sysmmu@12220000 { 194 + compatible = "samsung,exynos-sysmmu"; 195 + interrupt-parent = <&combiner>; 196 + reg = <0x12220000 0x1000>; 197 + interrupts = <5 3>; 198 + clock-names = "sysmmu", "master"; 199 + clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 200 + power-domains = <&pd_lcd1>; 201 + #iommu-cells = <0>; 202 + }; 203 + 204 + bus_dmc: bus_dmc { 205 + compatible = "samsung,exynos-bus"; 206 + clocks = <&clock CLK_DIV_DMC>; 207 + clock-names = "bus"; 208 + operating-points-v2 = <&bus_dmc_opp_table>; 209 + status = "disabled"; 210 + }; 211 + 212 + bus_acp: bus_acp { 213 + compatible = "samsung,exynos-bus"; 214 + clocks = <&clock CLK_DIV_ACP>; 215 + clock-names = "bus"; 216 + operating-points-v2 = <&bus_acp_opp_table>; 217 + status = "disabled"; 218 + }; 219 + 220 + bus_peri: bus_peri { 221 + compatible = "samsung,exynos-bus"; 222 + clocks = <&clock CLK_ACLK100>; 223 + clock-names = "bus"; 224 + operating-points-v2 = <&bus_peri_opp_table>; 225 + status = "disabled"; 226 + }; 227 + 228 + bus_fsys: bus_fsys { 229 + compatible = "samsung,exynos-bus"; 230 + clocks = <&clock CLK_ACLK133>; 231 + clock-names = "bus"; 232 + operating-points-v2 = <&bus_fsys_opp_table>; 233 + status = "disabled"; 234 + }; 235 + 236 + bus_display: bus_display { 237 + compatible = "samsung,exynos-bus"; 238 + clocks = <&clock CLK_ACLK160>; 239 + clock-names = "bus"; 240 + operating-points-v2 = <&bus_display_opp_table>; 241 + status = "disabled"; 242 + }; 243 + 244 + bus_lcd0: bus_lcd0 { 245 + compatible = "samsung,exynos-bus"; 246 + clocks = <&clock CLK_ACLK200>; 247 + clock-names = "bus"; 248 + operating-points-v2 = <&bus_leftbus_opp_table>; 249 + status = "disabled"; 250 + }; 251 + 252 + bus_leftbus: bus_leftbus { 253 + compatible = "samsung,exynos-bus"; 254 + clocks = <&clock CLK_DIV_GDL>; 255 + clock-names = "bus"; 256 + operating-points-v2 = <&bus_leftbus_opp_table>; 257 + status = "disabled"; 258 + }; 259 + 260 + bus_rightbus: bus_rightbus { 261 + compatible = "samsung,exynos-bus"; 262 + clocks = <&clock CLK_DIV_GDR>; 263 + clock-names = "bus"; 264 + operating-points-v2 = <&bus_leftbus_opp_table>; 265 + status = "disabled"; 266 + }; 267 + 268 + bus_mfc: bus_mfc { 269 + compatible = "samsung,exynos-bus"; 270 + clocks = <&clock CLK_SCLK_MFC>; 271 + clock-names = "bus"; 272 + operating-points-v2 = <&bus_leftbus_opp_table>; 273 + status = "disabled"; 274 + }; 275 + 276 + bus_dmc_opp_table: opp_table1 { 277 + compatible = "operating-points-v2"; 278 + opp-shared; 279 + 280 + opp-134000000 { 281 + opp-hz = /bits/ 64 <134000000>; 282 + opp-microvolt = <1025000>; 283 + }; 284 + opp-267000000 { 285 + opp-hz = /bits/ 64 <267000000>; 286 + opp-microvolt = <1050000>; 287 + }; 288 + opp-400000000 { 289 + opp-hz = /bits/ 64 <400000000>; 290 + opp-microvolt = <1150000>; 291 + }; 292 + }; 293 + 294 + bus_acp_opp_table: opp_table2 { 295 + compatible = "operating-points-v2"; 296 + opp-shared; 297 + 298 + opp-134000000 { 299 + opp-hz = /bits/ 64 <134000000>; 300 + }; 301 + opp-160000000 { 302 + opp-hz = /bits/ 64 <160000000>; 303 + }; 304 + opp-200000000 { 305 + opp-hz = /bits/ 64 <200000000>; 306 + }; 307 + }; 308 + 309 + bus_peri_opp_table: opp_table3 { 310 + compatible = "operating-points-v2"; 311 + opp-shared; 312 + 313 + opp-5000000 { 314 + opp-hz = /bits/ 64 <5000000>; 315 + }; 316 + opp-100000000 { 317 + opp-hz = /bits/ 64 <100000000>; 318 + }; 319 + }; 320 + 321 + bus_fsys_opp_table: opp_table4 { 322 + compatible = "operating-points-v2"; 323 + opp-shared; 324 + 325 + opp-10000000 { 326 + opp-hz = /bits/ 64 <10000000>; 327 + }; 328 + opp-134000000 { 329 + opp-hz = /bits/ 64 <134000000>; 330 + }; 331 + }; 332 + 333 + bus_display_opp_table: opp_table5 { 334 + compatible = "operating-points-v2"; 335 + opp-shared; 336 + 337 + opp-100000000 { 338 + opp-hz = /bits/ 64 <100000000>; 339 + }; 340 + opp-134000000 { 341 + opp-hz = /bits/ 64 <134000000>; 342 + }; 343 + opp-160000000 { 344 + opp-hz = /bits/ 64 <160000000>; 345 + }; 346 + }; 347 + 348 + bus_leftbus_opp_table: opp_table6 { 349 + compatible = "operating-points-v2"; 350 + opp-shared; 351 + 352 + opp-100000000 { 353 + opp-hz = /bits/ 64 <100000000>; 354 + }; 355 + opp-160000000 { 356 + opp-hz = /bits/ 64 <160000000>; 357 + }; 358 + opp-200000000 { 359 + opp-hz = /bits/ 64 <200000000>; 360 + }; 361 + }; 163 362 }; 164 363 165 364 thermal-zones { ··· 365 172 thermal-sensors = <&tmu 0>; 366 173 367 174 trips { 368 - cpu_alert0: cpu-alert-0 { 369 - temperature = <85000>; /* millicelsius */ 370 - }; 371 - cpu_alert1: cpu-alert-1 { 372 - temperature = <100000>; /* millicelsius */ 373 - }; 374 - cpu_alert2: cpu-alert-2 { 375 - temperature = <110000>; /* millicelsius */ 376 - }; 175 + cpu_alert0: cpu-alert-0 { 176 + temperature = <85000>; /* millicelsius */ 177 + }; 178 + cpu_alert1: cpu-alert-1 { 179 + temperature = <100000>; /* millicelsius */ 180 + }; 181 + cpu_alert2: cpu-alert-2 { 182 + temperature = <110000>; /* millicelsius */ 183 + }; 377 184 }; 378 - }; 379 - }; 380 - 381 - g2d: g2d@12800000 { 382 - compatible = "samsung,s5pv210-g2d"; 383 - reg = <0x12800000 0x1000>; 384 - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 385 - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 386 - clock-names = "sclk_fimg2d", "fimg2d"; 387 - power-domains = <&pd_lcd0>; 388 - iommus = <&sysmmu_g2d>; 389 - }; 390 - 391 - camera { 392 - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 393 - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 394 - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 395 - 396 - fimc_0: fimc@11800000 { 397 - samsung,pix-limits = <4224 8192 1920 4224>; 398 - samsung,mainscaler-ext; 399 - samsung,cam-if; 400 - }; 401 - 402 - fimc_1: fimc@11810000 { 403 - samsung,pix-limits = <4224 8192 1920 4224>; 404 - samsung,mainscaler-ext; 405 - samsung,cam-if; 406 - }; 407 - 408 - fimc_2: fimc@11820000 { 409 - samsung,pix-limits = <4224 8192 1920 4224>; 410 - samsung,mainscaler-ext; 411 - samsung,lcd-wb; 412 - }; 413 - 414 - fimc_3: fimc@11830000 { 415 - samsung,pix-limits = <1920 8192 1366 1920>; 416 - samsung,rotators = <0>; 417 - samsung,mainscaler-ext; 418 - samsung,lcd-wb; 419 - }; 420 - }; 421 - 422 - mixer: mixer@12c10000 { 423 - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", 424 - "sclk_mixer"; 425 - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 426 - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, 427 - <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; 428 - }; 429 - 430 - ppmu_lcd1: ppmu_lcd1@12240000 { 431 - compatible = "samsung,exynos-ppmu"; 432 - reg = <0x12240000 0x2000>; 433 - clocks = <&clock CLK_PPMULCD1>; 434 - clock-names = "ppmu"; 435 - status = "disabled"; 436 - }; 437 - 438 - sysmmu_g2d: sysmmu@12a20000 { 439 - compatible = "samsung,exynos-sysmmu"; 440 - reg = <0x12A20000 0x1000>; 441 - interrupt-parent = <&combiner>; 442 - interrupts = <4 7>; 443 - clock-names = "sysmmu", "master"; 444 - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 445 - power-domains = <&pd_lcd0>; 446 - #iommu-cells = <0>; 447 - }; 448 - 449 - sysmmu_fimd1: sysmmu@12220000 { 450 - compatible = "samsung,exynos-sysmmu"; 451 - interrupt-parent = <&combiner>; 452 - reg = <0x12220000 0x1000>; 453 - interrupts = <5 3>; 454 - clock-names = "sysmmu", "master"; 455 - clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 456 - power-domains = <&pd_lcd1>; 457 - #iommu-cells = <0>; 458 - }; 459 - 460 - bus_dmc: bus_dmc { 461 - compatible = "samsung,exynos-bus"; 462 - clocks = <&clock CLK_DIV_DMC>; 463 - clock-names = "bus"; 464 - operating-points-v2 = <&bus_dmc_opp_table>; 465 - status = "disabled"; 466 - }; 467 - 468 - bus_acp: bus_acp { 469 - compatible = "samsung,exynos-bus"; 470 - clocks = <&clock CLK_DIV_ACP>; 471 - clock-names = "bus"; 472 - operating-points-v2 = <&bus_acp_opp_table>; 473 - status = "disabled"; 474 - }; 475 - 476 - bus_peri: bus_peri { 477 - compatible = "samsung,exynos-bus"; 478 - clocks = <&clock CLK_ACLK100>; 479 - clock-names = "bus"; 480 - operating-points-v2 = <&bus_peri_opp_table>; 481 - status = "disabled"; 482 - }; 483 - 484 - bus_fsys: bus_fsys { 485 - compatible = "samsung,exynos-bus"; 486 - clocks = <&clock CLK_ACLK133>; 487 - clock-names = "bus"; 488 - operating-points-v2 = <&bus_fsys_opp_table>; 489 - status = "disabled"; 490 - }; 491 - 492 - bus_display: bus_display { 493 - compatible = "samsung,exynos-bus"; 494 - clocks = <&clock CLK_ACLK160>; 495 - clock-names = "bus"; 496 - operating-points-v2 = <&bus_display_opp_table>; 497 - status = "disabled"; 498 - }; 499 - 500 - bus_lcd0: bus_lcd0 { 501 - compatible = "samsung,exynos-bus"; 502 - clocks = <&clock CLK_ACLK200>; 503 - clock-names = "bus"; 504 - operating-points-v2 = <&bus_leftbus_opp_table>; 505 - status = "disabled"; 506 - }; 507 - 508 - bus_leftbus: bus_leftbus { 509 - compatible = "samsung,exynos-bus"; 510 - clocks = <&clock CLK_DIV_GDL>; 511 - clock-names = "bus"; 512 - operating-points-v2 = <&bus_leftbus_opp_table>; 513 - status = "disabled"; 514 - }; 515 - 516 - bus_rightbus: bus_rightbus { 517 - compatible = "samsung,exynos-bus"; 518 - clocks = <&clock CLK_DIV_GDR>; 519 - clock-names = "bus"; 520 - operating-points-v2 = <&bus_leftbus_opp_table>; 521 - status = "disabled"; 522 - }; 523 - 524 - bus_mfc: bus_mfc { 525 - compatible = "samsung,exynos-bus"; 526 - clocks = <&clock CLK_SCLK_MFC>; 527 - clock-names = "bus"; 528 - operating-points-v2 = <&bus_leftbus_opp_table>; 529 - status = "disabled"; 530 - }; 531 - 532 - bus_dmc_opp_table: opp_table1 { 533 - compatible = "operating-points-v2"; 534 - opp-shared; 535 - 536 - opp-134000000 { 537 - opp-hz = /bits/ 64 <134000000>; 538 - opp-microvolt = <1025000>; 539 - }; 540 - opp-267000000 { 541 - opp-hz = /bits/ 64 <267000000>; 542 - opp-microvolt = <1050000>; 543 - }; 544 - opp-400000000 { 545 - opp-hz = /bits/ 64 <400000000>; 546 - opp-microvolt = <1150000>; 547 - }; 548 - }; 549 - 550 - bus_acp_opp_table: opp_table2 { 551 - compatible = "operating-points-v2"; 552 - opp-shared; 553 - 554 - opp-134000000 { 555 - opp-hz = /bits/ 64 <134000000>; 556 - }; 557 - opp-160000000 { 558 - opp-hz = /bits/ 64 <160000000>; 559 - }; 560 - opp-200000000 { 561 - opp-hz = /bits/ 64 <200000000>; 562 - }; 563 - }; 564 - 565 - bus_peri_opp_table: opp_table3 { 566 - compatible = "operating-points-v2"; 567 - opp-shared; 568 - 569 - opp-5000000 { 570 - opp-hz = /bits/ 64 <5000000>; 571 - }; 572 - opp-100000000 { 573 - opp-hz = /bits/ 64 <100000000>; 574 - }; 575 - }; 576 - 577 - bus_fsys_opp_table: opp_table4 { 578 - compatible = "operating-points-v2"; 579 - opp-shared; 580 - 581 - opp-10000000 { 582 - opp-hz = /bits/ 64 <10000000>; 583 - }; 584 - opp-134000000 { 585 - opp-hz = /bits/ 64 <134000000>; 586 - }; 587 - }; 588 - 589 - bus_display_opp_table: opp_table5 { 590 - compatible = "operating-points-v2"; 591 - opp-shared; 592 - 593 - opp-100000000 { 594 - opp-hz = /bits/ 64 <100000000>; 595 - }; 596 - opp-134000000 { 597 - opp-hz = /bits/ 64 <134000000>; 598 - }; 599 - opp-160000000 { 600 - opp-hz = /bits/ 64 <160000000>; 601 - }; 602 - }; 603 - 604 - bus_leftbus_opp_table: opp_table6 { 605 - compatible = "operating-points-v2"; 606 - opp-shared; 607 - 608 - opp-100000000 { 609 - opp-hz = /bits/ 64 <100000000>; 610 - }; 611 - opp-160000000 { 612 - opp-hz = /bits/ 64 <160000000>; 613 - }; 614 - opp-200000000 { 615 - opp-hz = /bits/ 64 <200000000>; 616 185 }; 617 186 }; 618 187 }; 619 188 620 189 &gic { 621 190 cpu-offset = <0x8000>; 191 + }; 192 + 193 + &camera { 194 + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 195 + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 196 + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 622 197 }; 623 198 624 199 &combiner { ··· 409 448 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 410 449 }; 411 450 451 + &fimc_0 { 452 + samsung,pix-limits = <4224 8192 1920 4224>; 453 + samsung,mainscaler-ext; 454 + samsung,cam-if; 455 + }; 456 + 457 + &fimc_1 { 458 + samsung,pix-limits = <4224 8192 1920 4224>; 459 + samsung,mainscaler-ext; 460 + samsung,cam-if; 461 + }; 462 + 463 + &fimc_2 { 464 + samsung,pix-limits = <4224 8192 1920 4224>; 465 + samsung,mainscaler-ext; 466 + samsung,lcd-wb; 467 + }; 468 + 469 + &fimc_3 { 470 + samsung,pix-limits = <1920 8192 1366 1920>; 471 + samsung,rotators = <0>; 472 + samsung,mainscaler-ext; 473 + samsung,lcd-wb; 474 + }; 475 + 412 476 &mdma1 { 413 477 power-domains = <&pd_lcd0>; 478 + }; 479 + 480 + &mixer { 481 + clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", 482 + "sclk_mixer"; 483 + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 484 + <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, 485 + <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; 414 486 }; 415 487 416 488 &pmu_system_controller { ··· 462 468 &sysmmu_rotator { 463 469 power-domains = <&pd_lcd0>; 464 470 }; 471 + 472 + &tmu { 473 + compatible = "samsung,exynos4210-tmu"; 474 + clocks = <&clock CLK_TMU_APBIF>; 475 + clock-names = "tmu_apbif"; 476 + samsung,tmu_gain = <15>; 477 + samsung,tmu_reference_voltage = <7>; 478 + }; 479 + 480 + #include "exynos4210-pinctrl.dtsi"
+140
arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Samsung's Exynos4412 based Galaxy S3 board device tree source 4 + * 5 + * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 + * http://www.samsung.com 7 + */ 8 + 9 + /dts-v1/; 10 + #include "exynos4412-midas.dtsi" 11 + 12 + / { 13 + aliases { 14 + i2c9 = &i2c_ak8975; 15 + i2c10 = &i2c_cm36651; 16 + }; 17 + 18 + regulators { 19 + lcd_vdd3_reg: voltage-regulator-2 { 20 + compatible = "regulator-fixed"; 21 + regulator-name = "LCD_VDD_2.2V"; 22 + regulator-min-microvolt = <2200000>; 23 + regulator-max-microvolt = <2200000>; 24 + gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; 25 + enable-active-high; 26 + }; 27 + 28 + ps_als_reg: voltage-regulator-5 { 29 + compatible = "regulator-fixed"; 30 + regulator-name = "LED_A_3.0V"; 31 + regulator-min-microvolt = <3000000>; 32 + regulator-max-microvolt = <3000000>; 33 + gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; 34 + enable-active-high; 35 + }; 36 + }; 37 + 38 + i2c_ak8975: i2c-gpio-0 { 39 + compatible = "i2c-gpio"; 40 + gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; 41 + i2c-gpio,delay-us = <2>; 42 + #address-cells = <1>; 43 + #size-cells = <0>; 44 + status = "okay"; 45 + 46 + ak8975@c { 47 + compatible = "asahi-kasei,ak8975"; 48 + reg = <0x0c>; 49 + gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; 50 + }; 51 + }; 52 + 53 + i2c_cm36651: i2c-gpio-2 { 54 + compatible = "i2c-gpio"; 55 + gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; 56 + i2c-gpio,delay-us = <2>; 57 + #address-cells = <1>; 58 + #size-cells = <0>; 59 + 60 + cm36651@18 { 61 + compatible = "capella,cm36651"; 62 + reg = <0x18>; 63 + interrupt-parent = <&gpx0>; 64 + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 65 + vled-supply = <&ps_als_reg>; 66 + }; 67 + }; 68 + }; 69 + 70 + &buck9_reg { 71 + maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; 72 + }; 73 + 74 + &cam_af_reg { 75 + gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; 76 + status = "okay"; 77 + }; 78 + 79 + &cam_io_reg { 80 + gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; 81 + status = "okay"; 82 + }; 83 + 84 + &dsi_0 { 85 + status = "okay"; 86 + 87 + panel@0 { 88 + compatible = "samsung,s6e8aa0"; 89 + reg = <0>; 90 + vdd3-supply = <&lcd_vdd3_reg>; 91 + vci-supply = <&ldo25_reg>; 92 + reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; 93 + power-on-delay= <50>; 94 + reset-delay = <100>; 95 + init-delay = <100>; 96 + flip-horizontal; 97 + flip-vertical; 98 + panel-width-mm = <58>; 99 + panel-height-mm = <103>; 100 + 101 + display-timings { 102 + timing-0 { 103 + clock-frequency = <57153600>; 104 + hactive = <720>; 105 + vactive = <1280>; 106 + hfront-porch = <5>; 107 + hback-porch = <5>; 108 + hsync-len = <5>; 109 + vfront-porch = <13>; 110 + vback-porch = <1>; 111 + vsync-len = <2>; 112 + }; 113 + }; 114 + }; 115 + }; 116 + 117 + &i2c_3 { 118 + mms114-touchscreen@48 { 119 + compatible = "melfas,mms114"; 120 + reg = <0x48>; 121 + interrupt-parent = <&gpm2>; 122 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 123 + x-size = <720>; 124 + y-size = <1280>; 125 + avdd-supply = <&ldo23_reg>; 126 + vdd-supply = <&ldo24_reg>; 127 + }; 128 + }; 129 + 130 + &ldo25_reg { 131 + regulator-name = "LCD_VCC_3.3V"; 132 + regulator-min-microvolt = <2800000>; 133 + regulator-max-microvolt = <2800000>; 134 + }; 135 + 136 + &s5c73m3 { 137 + standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ 138 + vdda-supply = <&ldo17_reg>; 139 + status = "okay"; 140 + };
+22
arch/arm/boot/dts/exynos4412-i9300.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Samsung's Exynos4412 based M0 (GT-I9300) board device tree source 4 + * 5 + * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 + * http://www.samsung.com 7 + */ 8 + 9 + /dts-v1/; 10 + #include "exynos4412-galaxy-s3.dtsi" 11 + 12 + / { 13 + model = "Samsung Galaxy S3 (GT-I9300) based on Exynos4412"; 14 + compatible = "samsung,i9300", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; 15 + 16 + /* bootargs are passed in by bootloader */ 17 + 18 + memory@40000000 { 19 + device_type = "memory"; 20 + reg = <0x40000000 0x40000000>; 21 + }; 22 + };
+20
arch/arm/boot/dts/exynos4412-i9305.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /dts-v1/; 3 + #include "exynos4412-galaxy-s3.dtsi" 4 + 5 + / { 6 + model = "Samsung Galaxy S3 (GT-I9305) based on Exynos4412"; 7 + compatible = "samsung,i9305", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; 8 + 9 + /* bootargs are passed in by bootloader */ 10 + 11 + memory@40000000 { 12 + device_type = "memory"; 13 + reg = <0x40000000 0x80000000>; 14 + }; 15 + }; 16 + 17 + &i2c0_bus { 18 + /* SCL and SDA pins are swapped */ 19 + samsung,pins = "gpd1-1", "gpd1-0"; 20 + };
+8 -8
arch/arm/boot/dts/exynos4412-itop-elite.dts
··· 116 116 compatible = "pwm-beeper"; 117 117 pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>; 118 118 }; 119 - 120 - camera: camera { 121 - pinctrl-0 = <&cam_port_a_clk_active>; 122 - pinctrl-names = "default"; 123 - status = "okay"; 124 - assigned-clocks = <&clock CLK_MOUT_CAM0>; 125 - assigned-clock-parents = <&clock CLK_XUSBXTI>; 126 - }; 127 119 }; 128 120 129 121 &adc { 130 122 vdd-supply = <&ldo3_reg>; 131 123 status = "okay"; 124 + }; 125 + 126 + &camera { 127 + pinctrl-0 = <&cam_port_a_clk_active>; 128 + pinctrl-names = "default"; 129 + status = "okay"; 130 + assigned-clocks = <&clock CLK_MOUT_CAM0>; 131 + assigned-clock-parents = <&clock CLK_XUSBXTI>; 132 132 }; 133 133 134 134 &clock_audss {
+1308
arch/arm/boot/dts/exynos4412-midas.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Samsung's Exynos4412 based Trats 2 board device tree source 4 + * 5 + * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 + * http://www.samsung.com 7 + * 8 + * Device tree source file for Samsung's Trats 2 board which is based on 9 + * Samsung's Exynos4412 SoC. 10 + */ 11 + 12 + /dts-v1/; 13 + #include "exynos4412.dtsi" 14 + #include "exynos4412-ppmu-common.dtsi" 15 + #include <dt-bindings/gpio/gpio.h> 16 + #include <dt-bindings/interrupt-controller/irq.h> 17 + #include <dt-bindings/clock/maxim,max77686.h> 18 + #include <dt-bindings/pinctrl/samsung.h> 19 + 20 + / { 21 + compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; 22 + 23 + aliases { 24 + i2c11 = &i2c_max77693; 25 + i2c12 = &i2c_max77693_fuel; 26 + }; 27 + 28 + chosen { 29 + stdout-path = &serial_2; 30 + }; 31 + 32 + firmware@204f000 { 33 + compatible = "samsung,secure-firmware"; 34 + reg = <0x0204F000 0x1000>; 35 + }; 36 + 37 + fixed-rate-clocks { 38 + xxti { 39 + compatible = "samsung,clock-xxti", "fixed-clock"; 40 + clock-frequency = <0>; 41 + }; 42 + 43 + xusbxti { 44 + compatible = "samsung,clock-xusbxti", "fixed-clock"; 45 + clock-frequency = <24000000>; 46 + }; 47 + }; 48 + 49 + regulators { 50 + compatible = "simple-bus"; 51 + #address-cells = <1>; 52 + #size-cells = <0>; 53 + 54 + cam_io_reg: voltage-regulator-1 { 55 + compatible = "regulator-fixed"; 56 + regulator-name = "CAM_SENSOR_A"; 57 + regulator-min-microvolt = <2800000>; 58 + regulator-max-microvolt = <2800000>; 59 + enable-active-high; 60 + status = "disabled"; 61 + }; 62 + 63 + cam_af_reg: voltage-regulator-3 { 64 + compatible = "regulator-fixed"; 65 + regulator-name = "CAM_AF"; 66 + regulator-min-microvolt = <2800000>; 67 + regulator-max-microvolt = <2800000>; 68 + enable-active-high; 69 + status = "disabled"; 70 + }; 71 + 72 + vsil12: voltage-regulator-6 { 73 + compatible = "regulator-fixed"; 74 + regulator-name = "VSIL_1.2V"; 75 + regulator-min-microvolt = <1200000>; 76 + regulator-max-microvolt = <1200000>; 77 + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; 78 + enable-active-high; 79 + vin-supply = <&buck7_reg>; 80 + }; 81 + 82 + vcc33mhl: voltage-regulator-7 { 83 + compatible = "regulator-fixed"; 84 + regulator-name = "VCC_3.3_MHL"; 85 + regulator-min-microvolt = <3300000>; 86 + regulator-max-microvolt = <3300000>; 87 + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; 88 + enable-active-high; 89 + }; 90 + 91 + vcc18mhl: voltage-regulator-8 { 92 + compatible = "regulator-fixed"; 93 + regulator-name = "VCC_1.8_MHL"; 94 + regulator-min-microvolt = <1800000>; 95 + regulator-max-microvolt = <1800000>; 96 + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; 97 + enable-active-high; 98 + }; 99 + }; 100 + 101 + gpio-keys { 102 + compatible = "gpio-keys"; 103 + 104 + key-down { 105 + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; 106 + linux,code = <114>; 107 + label = "volume down"; 108 + debounce-interval = <10>; 109 + }; 110 + 111 + key-up { 112 + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; 113 + linux,code = <115>; 114 + label = "volume up"; 115 + debounce-interval = <10>; 116 + }; 117 + 118 + key-power { 119 + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; 120 + linux,code = <116>; 121 + label = "power"; 122 + debounce-interval = <10>; 123 + wakeup-source; 124 + }; 125 + 126 + key-ok { 127 + gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; 128 + linux,code = <139>; 129 + label = "ok"; 130 + debounce-inteval = <10>; 131 + wakeup-source; 132 + }; 133 + }; 134 + 135 + i2c_max77693: i2c-gpio-1 { 136 + compatible = "i2c-gpio"; 137 + gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; 138 + i2c-gpio,delay-us = <2>; 139 + #address-cells = <1>; 140 + #size-cells = <0>; 141 + status = "okay"; 142 + 143 + max77693@66 { 144 + compatible = "maxim,max77693"; 145 + interrupt-parent = <&gpx1>; 146 + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 147 + reg = <0x66>; 148 + 149 + regulators { 150 + esafeout1_reg: ESAFEOUT1 { 151 + regulator-name = "ESAFEOUT1"; 152 + }; 153 + esafeout2_reg: ESAFEOUT2 { 154 + regulator-name = "ESAFEOUT2"; 155 + }; 156 + charger_reg: CHARGER { 157 + regulator-name = "CHARGER"; 158 + regulator-min-microamp = <60000>; 159 + regulator-max-microamp = <2580000>; 160 + }; 161 + }; 162 + 163 + max77693_haptic { 164 + compatible = "maxim,max77693-haptic"; 165 + haptic-supply = <&ldo26_reg>; 166 + pwms = <&pwm 0 38022 0>; 167 + }; 168 + 169 + charger { 170 + compatible = "maxim,max77693-charger"; 171 + 172 + maxim,constant-microvolt = <4350000>; 173 + maxim,min-system-microvolt = <3600000>; 174 + maxim,thermal-regulation-celsius = <100>; 175 + maxim,battery-overcurrent-microamp = <3500000>; 176 + maxim,charge-input-threshold-microvolt = <4300000>; 177 + }; 178 + }; 179 + }; 180 + 181 + i2c_max77693_fuel: i2c-gpio-3 { 182 + compatible = "i2c-gpio"; 183 + gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>; 184 + i2c-gpio,delay-us = <2>; 185 + #address-cells = <1>; 186 + #size-cells = <0>; 187 + status = "okay"; 188 + 189 + max77693-fuel-gauge@36 { 190 + compatible = "maxim,max17047"; 191 + interrupt-parent = <&gpx2>; 192 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 193 + reg = <0x36>; 194 + 195 + maxim,over-heat-temp = <700>; 196 + maxim,over-volt = <4500>; 197 + }; 198 + }; 199 + 200 + i2c-mhl { 201 + compatible = "i2c-gpio"; 202 + gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; 203 + i2c-gpio,delay-us = <100>; 204 + #address-cells = <1>; 205 + #size-cells = <0>; 206 + 207 + pinctrl-0 = <&i2c_mhl_bus>; 208 + pinctrl-names = "default"; 209 + status = "okay"; 210 + 211 + sii9234: hdmi-bridge@39 { 212 + compatible = "sil,sii9234"; 213 + avcc33-supply = <&vcc33mhl>; 214 + iovcc18-supply = <&vcc18mhl>; 215 + avcc12-supply = <&vsil12>; 216 + cvcc12-supply = <&vsil12>; 217 + reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; 218 + interrupt-parent = <&gpf3>; 219 + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 220 + reg = <0x39>; 221 + 222 + port { 223 + mhl_to_hdmi: endpoint { 224 + remote-endpoint = <&hdmi_to_mhl>; 225 + }; 226 + }; 227 + }; 228 + }; 229 + 230 + wlan_pwrseq: sdhci3-pwrseq { 231 + compatible = "mmc-pwrseq-simple"; 232 + reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>; 233 + clocks = <&max77686 MAX77686_CLK_PMIC>; 234 + clock-names = "ext_clock"; 235 + }; 236 + 237 + sound { 238 + compatible = "samsung,trats2-audio"; 239 + samsung,i2s-controller = <&i2s0>; 240 + samsung,model = "Trats2"; 241 + samsung,audio-codec = <&wm1811>; 242 + samsung,audio-routing = 243 + "SPK", "SPKOUTLN", 244 + "SPK", "SPKOUTLP", 245 + "SPK", "SPKOUTRN", 246 + "SPK", "SPKOUTRP"; 247 + }; 248 + 249 + thermistor-ap { 250 + compatible = "murata,ncp15wb473"; 251 + pullup-uv = <1800000>; /* VCC_1.8V_AP */ 252 + pullup-ohm = <100000>; /* 100K */ 253 + pulldown-ohm = <100000>; /* 100K */ 254 + io-channels = <&adc 1>; /* AP temperature */ 255 + }; 256 + 257 + thermistor-battery { 258 + compatible = "murata,ncp15wb473"; 259 + pullup-uv = <1800000>; /* VCC_1.8V_AP */ 260 + pullup-ohm = <100000>; /* 100K */ 261 + pulldown-ohm = <100000>; /* 100K */ 262 + io-channels = <&adc 2>; /* Battery temperature */ 263 + }; 264 + 265 + thermal-zones { 266 + cpu_thermal: cpu-thermal { 267 + cooling-maps { 268 + map0 { 269 + /* Corresponds to 800MHz at freq_table */ 270 + cooling-device = <&cpu0 7 7>; 271 + }; 272 + map1 { 273 + /* Corresponds to 200MHz at freq_table */ 274 + cooling-device = <&cpu0 13 13>; 275 + }; 276 + }; 277 + }; 278 + }; 279 + }; 280 + 281 + &adc { 282 + vdd-supply = <&ldo3_reg>; 283 + status = "okay"; 284 + }; 285 + 286 + &bus_dmc { 287 + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; 288 + vdd-supply = <&buck1_reg>; 289 + status = "okay"; 290 + }; 291 + 292 + &bus_acp { 293 + devfreq = <&bus_dmc>; 294 + status = "okay"; 295 + }; 296 + 297 + &bus_c2c { 298 + devfreq = <&bus_dmc>; 299 + status = "okay"; 300 + }; 301 + 302 + &bus_leftbus { 303 + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; 304 + vdd-supply = <&buck3_reg>; 305 + status = "okay"; 306 + }; 307 + 308 + &bus_rightbus { 309 + devfreq = <&bus_leftbus>; 310 + status = "okay"; 311 + }; 312 + 313 + &bus_display { 314 + devfreq = <&bus_leftbus>; 315 + status = "okay"; 316 + }; 317 + 318 + &bus_fsys { 319 + devfreq = <&bus_leftbus>; 320 + status = "okay"; 321 + }; 322 + 323 + &bus_peri { 324 + devfreq = <&bus_leftbus>; 325 + status = "okay"; 326 + }; 327 + 328 + &bus_mfc { 329 + devfreq = <&bus_leftbus>; 330 + status = "okay"; 331 + }; 332 + 333 + &camera { 334 + pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; 335 + pinctrl-names = "default"; 336 + status = "okay"; 337 + assigned-clocks = <&clock CLK_MOUT_CAM0>, 338 + <&clock CLK_MOUT_CAM1>; 339 + assigned-clock-parents = <&clock CLK_XUSBXTI>, 340 + <&clock CLK_XUSBXTI>; 341 + }; 342 + 343 + &cpu0 { 344 + cpu0-supply = <&buck2_reg>; 345 + }; 346 + 347 + &csis_0 { 348 + status = "okay"; 349 + vddcore-supply = <&ldo8_reg>; 350 + vddio-supply = <&ldo10_reg>; 351 + assigned-clocks = <&clock CLK_MOUT_CSIS0>, 352 + <&clock CLK_SCLK_CSIS0>; 353 + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 354 + assigned-clock-rates = <0>, <176000000>; 355 + 356 + /* Camera C (3) MIPI CSI-2 (CSIS0) */ 357 + port@3 { 358 + reg = <3>; 359 + csis0_ep: endpoint { 360 + remote-endpoint = <&s5c73m3_ep>; 361 + data-lanes = <1 2 3 4>; 362 + samsung,csis-hs-settle = <12>; 363 + }; 364 + }; 365 + }; 366 + 367 + &csis_1 { 368 + status = "okay"; 369 + vddcore-supply = <&ldo8_reg>; 370 + vddio-supply = <&ldo10_reg>; 371 + assigned-clocks = <&clock CLK_MOUT_CSIS1>, 372 + <&clock CLK_SCLK_CSIS1>; 373 + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 374 + assigned-clock-rates = <0>, <176000000>; 375 + 376 + /* Camera D (4) MIPI CSI-2 (CSIS1) */ 377 + port@4 { 378 + reg = <4>; 379 + csis1_ep: endpoint { 380 + remote-endpoint = <&is_s5k6a3_ep>; 381 + data-lanes = <1>; 382 + samsung,csis-hs-settle = <18>; 383 + samsung,csis-wclk; 384 + }; 385 + }; 386 + }; 387 + 388 + &dsi_0 { 389 + vddcore-supply = <&ldo8_reg>; 390 + vddio-supply = <&ldo10_reg>; 391 + samsung,burst-clock-frequency = <500000000>; 392 + samsung,esc-clock-frequency = <20000000>; 393 + samsung,pll-clock-frequency = <24000000>; 394 + }; 395 + 396 + &exynos_usbphy { 397 + vbus-supply = <&esafeout1_reg>; 398 + status = "okay"; 399 + }; 400 + 401 + &fimc_0 { 402 + status = "okay"; 403 + assigned-clocks = <&clock CLK_MOUT_FIMC0>, 404 + <&clock CLK_SCLK_FIMC0>; 405 + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 406 + assigned-clock-rates = <0>, <176000000>; 407 + }; 408 + 409 + &fimc_1 { 410 + status = "okay"; 411 + assigned-clocks = <&clock CLK_MOUT_FIMC1>, 412 + <&clock CLK_SCLK_FIMC1>; 413 + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 414 + assigned-clock-rates = <0>, <176000000>; 415 + }; 416 + 417 + &fimc_2 { 418 + status = "okay"; 419 + assigned-clocks = <&clock CLK_MOUT_FIMC2>, 420 + <&clock CLK_SCLK_FIMC2>; 421 + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 422 + assigned-clock-rates = <0>, <176000000>; 423 + }; 424 + 425 + &fimc_3 { 426 + status = "okay"; 427 + assigned-clocks = <&clock CLK_MOUT_FIMC3>, 428 + <&clock CLK_SCLK_FIMC3>; 429 + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 430 + assigned-clock-rates = <0>, <176000000>; 431 + }; 432 + 433 + &fimc_is { 434 + pinctrl-0 = <&fimc_is_uart>; 435 + pinctrl-names = "default"; 436 + status = "okay"; 437 + 438 + }; 439 + 440 + &fimc_lite_0 { 441 + status = "okay"; 442 + }; 443 + 444 + &fimc_lite_1 { 445 + status = "okay"; 446 + }; 447 + 448 + &fimd { 449 + status = "okay"; 450 + }; 451 + 452 + &hdmi { 453 + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; 454 + pinctrl-names = "default"; 455 + pinctrl-0 = <&hdmi_hpd>; 456 + vdd-supply = <&ldo3_reg>; 457 + vdd_osc-supply = <&ldo4_reg>; 458 + vdd_pll-supply = <&ldo3_reg>; 459 + ddc = <&i2c_5>; 460 + status = "okay"; 461 + 462 + ports { 463 + #address-cells = <1>; 464 + #size-cells = <0>; 465 + 466 + port@1 { 467 + reg = <1>; 468 + hdmi_to_mhl: endpoint { 469 + remote-endpoint = <&mhl_to_hdmi>; 470 + }; 471 + }; 472 + }; 473 + }; 474 + 475 + &hsotg { 476 + vusb_d-supply = <&ldo15_reg>; 477 + vusb_a-supply = <&ldo12_reg>; 478 + dr_mode = "peripheral"; 479 + status = "okay"; 480 + }; 481 + 482 + &i2c_0 { 483 + samsung,i2c-sda-delay = <100>; 484 + samsung,i2c-slave-addr = <0x10>; 485 + samsung,i2c-max-bus-freq = <400000>; 486 + pinctrl-0 = <&i2c0_bus>; 487 + pinctrl-names = "default"; 488 + status = "okay"; 489 + 490 + s5c73m3: s5c73m3@3c { 491 + compatible = "samsung,s5c73m3"; 492 + reg = <0x3c>; 493 + xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ 494 + vdd-int-supply = <&buck9_reg>; 495 + vddio-cis-supply = <&ldo9_reg>; 496 + vddio-host-supply = <&ldo18_reg>; 497 + vdd-af-supply = <&cam_af_reg>; 498 + vdd-reg-supply = <&cam_io_reg>; 499 + clock-frequency = <24000000>; 500 + /* CAM_A_CLKOUT */ 501 + clocks = <&camera 0>; 502 + clock-names = "cis_extclk"; 503 + status = "disabled"; 504 + port { 505 + s5c73m3_ep: endpoint { 506 + remote-endpoint = <&csis0_ep>; 507 + data-lanes = <1 2 3 4>; 508 + }; 509 + }; 510 + }; 511 + }; 512 + 513 + &i2c1_isp { 514 + pinctrl-0 = <&fimc_is_i2c1>; 515 + pinctrl-names = "default"; 516 + 517 + s5k6a3@10 { 518 + compatible = "samsung,s5k6a3"; 519 + reg = <0x10>; 520 + svdda-supply = <&cam_io_reg>; 521 + svddio-supply = <&ldo19_reg>; 522 + afvdd-supply = <&ldo19_reg>; 523 + clock-frequency = <24000000>; 524 + /* CAM_B_CLKOUT */ 525 + clocks = <&camera 1>; 526 + clock-names = "extclk"; 527 + samsung,camclk-out = <1>; 528 + gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; 529 + 530 + port { 531 + is_s5k6a3_ep: endpoint { 532 + remote-endpoint = <&csis1_ep>; 533 + data-lanes = <1>; 534 + }; 535 + }; 536 + }; 537 + }; 538 + 539 + &i2c_3 { 540 + samsung,i2c-sda-delay = <100>; 541 + samsung,i2c-slave-addr = <0x10>; 542 + samsung,i2c-max-bus-freq = <400000>; 543 + pinctrl-0 = <&i2c3_bus>; 544 + pinctrl-names = "default"; 545 + status = "okay"; 546 + }; 547 + 548 + &i2c_4 { 549 + samsung,i2c-sda-delay = <100>; 550 + samsung,i2c-slave-addr = <0x10>; 551 + samsung,i2c-max-bus-freq = <100000>; 552 + pinctrl-0 = <&i2c4_bus>; 553 + pinctrl-names = "default"; 554 + status = "okay"; 555 + 556 + wm1811: wm1811@1a { 557 + compatible = "wlf,wm1811"; 558 + reg = <0x1a>; 559 + clocks = <&pmu_system_controller 0>; 560 + clock-names = "MCLK1"; 561 + DCVDD-supply = <&ldo3_reg>; 562 + DBVDD1-supply = <&ldo3_reg>; 563 + wlf,ldo1ena = <&gpj0 4 0>; 564 + }; 565 + }; 566 + 567 + &i2c_5 { 568 + status = "okay"; 569 + }; 570 + 571 + &i2c_7 { 572 + samsung,i2c-sda-delay = <100>; 573 + samsung,i2c-slave-addr = <0x10>; 574 + samsung,i2c-max-bus-freq = <100000>; 575 + pinctrl-0 = <&i2c7_bus>; 576 + pinctrl-names = "default"; 577 + status = "okay"; 578 + 579 + max77686: max77686_pmic@9 { 580 + compatible = "maxim,max77686"; 581 + interrupt-parent = <&gpx0>; 582 + interrupts = <7 IRQ_TYPE_NONE>; 583 + reg = <0x09>; 584 + #clock-cells = <1>; 585 + 586 + voltage-regulators { 587 + ldo1_reg: LDO1 { 588 + regulator-name = "VALIVE_1.0V_AP"; 589 + regulator-min-microvolt = <1000000>; 590 + regulator-max-microvolt = <1000000>; 591 + regulator-always-on; 592 + }; 593 + 594 + ldo2_reg: LDO2 { 595 + regulator-name = "VM1M2_1.2V_AP"; 596 + regulator-min-microvolt = <1200000>; 597 + regulator-max-microvolt = <1200000>; 598 + regulator-always-on; 599 + regulator-state-mem { 600 + regulator-on-in-suspend; 601 + }; 602 + }; 603 + 604 + ldo3_reg: LDO3 { 605 + regulator-name = "VCC_1.8V_AP"; 606 + regulator-min-microvolt = <1800000>; 607 + regulator-max-microvolt = <1800000>; 608 + regulator-always-on; 609 + }; 610 + 611 + ldo4_reg: LDO4 { 612 + regulator-name = "VCC_2.8V_AP"; 613 + regulator-min-microvolt = <2800000>; 614 + regulator-max-microvolt = <2800000>; 615 + regulator-always-on; 616 + }; 617 + 618 + ldo5_reg: LDO5 { 619 + regulator-name = "VCC_1.8V_IO"; 620 + regulator-min-microvolt = <1800000>; 621 + regulator-max-microvolt = <1800000>; 622 + regulator-always-on; 623 + }; 624 + 625 + ldo6_reg: LDO6 { 626 + regulator-name = "VMPLL_1.0V_AP"; 627 + regulator-min-microvolt = <1000000>; 628 + regulator-max-microvolt = <1000000>; 629 + regulator-always-on; 630 + regulator-state-mem { 631 + regulator-on-in-suspend; 632 + }; 633 + }; 634 + 635 + ldo7_reg: LDO7 { 636 + regulator-name = "VPLL_1.0V_AP"; 637 + regulator-min-microvolt = <1000000>; 638 + regulator-max-microvolt = <1000000>; 639 + regulator-always-on; 640 + regulator-state-mem { 641 + regulator-on-in-suspend; 642 + }; 643 + }; 644 + 645 + ldo8_reg: LDO8 { 646 + regulator-name = "VMIPI_1.0V"; 647 + regulator-min-microvolt = <1000000>; 648 + regulator-max-microvolt = <1000000>; 649 + regulator-state-mem { 650 + regulator-off-in-suspend; 651 + }; 652 + }; 653 + 654 + ldo9_reg: LDO9 { 655 + regulator-name = "CAM_ISP_MIPI_1.2V"; 656 + regulator-min-microvolt = <1200000>; 657 + regulator-max-microvolt = <1200000>; 658 + }; 659 + 660 + ldo10_reg: LDO10 { 661 + regulator-name = "VMIPI_1.8V"; 662 + regulator-min-microvolt = <1800000>; 663 + regulator-max-microvolt = <1800000>; 664 + regulator-state-mem { 665 + regulator-off-in-suspend; 666 + }; 667 + }; 668 + 669 + ldo11_reg: LDO11 { 670 + regulator-name = "VABB1_1.95V"; 671 + regulator-min-microvolt = <1950000>; 672 + regulator-max-microvolt = <1950000>; 673 + regulator-always-on; 674 + regulator-state-mem { 675 + regulator-off-in-suspend; 676 + }; 677 + }; 678 + 679 + ldo12_reg: LDO12 { 680 + regulator-name = "VUOTG_3.0V"; 681 + regulator-min-microvolt = <3000000>; 682 + regulator-max-microvolt = <3000000>; 683 + regulator-state-mem { 684 + regulator-off-in-suspend; 685 + }; 686 + }; 687 + 688 + ldo13_reg: LDO13 { 689 + regulator-name = "NFC_AVDD_1.8V"; 690 + regulator-min-microvolt = <1800000>; 691 + regulator-max-microvolt = <1800000>; 692 + }; 693 + 694 + ldo14_reg: LDO14 { 695 + regulator-name = "VABB2_1.95V"; 696 + regulator-min-microvolt = <1950000>; 697 + regulator-max-microvolt = <1950000>; 698 + regulator-always-on; 699 + regulator-state-mem { 700 + regulator-off-in-suspend; 701 + }; 702 + }; 703 + 704 + ldo15_reg: LDO15 { 705 + regulator-name = "VHSIC_1.0V"; 706 + regulator-min-microvolt = <1000000>; 707 + regulator-max-microvolt = <1000000>; 708 + regulator-state-mem { 709 + regulator-on-in-suspend; 710 + }; 711 + }; 712 + 713 + ldo16_reg: LDO16 { 714 + regulator-name = "VHSIC_1.8V"; 715 + regulator-min-microvolt = <1800000>; 716 + regulator-max-microvolt = <1800000>; 717 + regulator-state-mem { 718 + regulator-on-in-suspend; 719 + }; 720 + }; 721 + 722 + ldo17_reg: LDO17 { 723 + regulator-name = "CAM_SENSOR_CORE_1.2V"; 724 + regulator-min-microvolt = <1200000>; 725 + regulator-max-microvolt = <1200000>; 726 + }; 727 + 728 + ldo18_reg: LDO18 { 729 + regulator-name = "CAM_ISP_SEN_IO_1.8V"; 730 + regulator-min-microvolt = <1800000>; 731 + regulator-max-microvolt = <1800000>; 732 + }; 733 + 734 + ldo19_reg: LDO19 { 735 + regulator-name = "VT_CAM_1.8V"; 736 + regulator-min-microvolt = <1800000>; 737 + regulator-max-microvolt = <1800000>; 738 + }; 739 + 740 + ldo20_reg: LDO20 { 741 + regulator-name = "VDDQ_PRE_1.8V"; 742 + regulator-min-microvolt = <1800000>; 743 + regulator-max-microvolt = <1800000>; 744 + }; 745 + 746 + ldo21_reg: LDO21 { 747 + regulator-name = "VTF_2.8V"; 748 + regulator-min-microvolt = <2800000>; 749 + regulator-max-microvolt = <2800000>; 750 + maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; 751 + }; 752 + 753 + ldo22_reg: LDO22 { 754 + regulator-name = "VMEM_VDD_2.8V"; 755 + regulator-min-microvolt = <2800000>; 756 + regulator-max-microvolt = <2800000>; 757 + maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; 758 + }; 759 + 760 + ldo23_reg: LDO23 { 761 + regulator-name = "TSP_AVDD_3.3V"; 762 + regulator-min-microvolt = <3300000>; 763 + regulator-max-microvolt = <3300000>; 764 + }; 765 + 766 + ldo24_reg: LDO24 { 767 + regulator-name = "TSP_VDD_1.8V"; 768 + regulator-min-microvolt = <1800000>; 769 + regulator-max-microvolt = <1800000>; 770 + }; 771 + 772 + ldo25_reg: LDO25 { 773 + regulator-name = "LDO25"; 774 + }; 775 + 776 + ldo26_reg: LDO26 { 777 + regulator-name = "MOTOR_VCC_3.0V"; 778 + regulator-min-microvolt = <3000000>; 779 + regulator-max-microvolt = <3000000>; 780 + }; 781 + 782 + buck1_reg: BUCK1 { 783 + regulator-name = "vdd_mif"; 784 + regulator-min-microvolt = <850000>; 785 + regulator-max-microvolt = <1100000>; 786 + regulator-always-on; 787 + regulator-boot-on; 788 + regulator-state-mem { 789 + regulator-off-in-suspend; 790 + }; 791 + }; 792 + 793 + buck2_reg: BUCK2 { 794 + regulator-name = "vdd_arm"; 795 + regulator-min-microvolt = <850000>; 796 + regulator-max-microvolt = <1500000>; 797 + regulator-always-on; 798 + regulator-boot-on; 799 + regulator-state-mem { 800 + regulator-on-in-suspend; 801 + }; 802 + }; 803 + 804 + buck3_reg: BUCK3 { 805 + regulator-name = "vdd_int"; 806 + regulator-min-microvolt = <850000>; 807 + regulator-max-microvolt = <1150000>; 808 + regulator-always-on; 809 + regulator-boot-on; 810 + regulator-state-mem { 811 + regulator-off-in-suspend; 812 + }; 813 + }; 814 + 815 + buck4_reg: BUCK4 { 816 + regulator-name = "vdd_g3d"; 817 + regulator-min-microvolt = <850000>; 818 + regulator-max-microvolt = <1150000>; 819 + regulator-boot-on; 820 + regulator-state-mem { 821 + regulator-off-in-suspend; 822 + }; 823 + }; 824 + 825 + buck5_reg: BUCK5 { 826 + regulator-name = "VMEM_1.2V_AP"; 827 + regulator-min-microvolt = <1200000>; 828 + regulator-max-microvolt = <1200000>; 829 + regulator-always-on; 830 + }; 831 + 832 + buck6_reg: BUCK6 { 833 + regulator-name = "VCC_SUB_1.35V"; 834 + regulator-min-microvolt = <1350000>; 835 + regulator-max-microvolt = <1350000>; 836 + regulator-always-on; 837 + }; 838 + 839 + buck7_reg: BUCK7 { 840 + regulator-name = "VCC_SUB_2.0V"; 841 + regulator-min-microvolt = <2000000>; 842 + regulator-max-microvolt = <2000000>; 843 + regulator-always-on; 844 + }; 845 + 846 + buck8_reg: BUCK8 { 847 + regulator-name = "VMEM_VDDF_3.0V"; 848 + regulator-min-microvolt = <2850000>; 849 + regulator-max-microvolt = <2850000>; 850 + maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; 851 + }; 852 + 853 + buck9_reg: BUCK9 { 854 + regulator-name = "CAM_ISP_CORE_1.2V"; 855 + regulator-min-microvolt = <1000000>; 856 + regulator-max-microvolt = <1200000>; 857 + }; 858 + }; 859 + }; 860 + }; 861 + 862 + &i2c_8 { 863 + status = "okay"; 864 + }; 865 + 866 + &i2s0 { 867 + pinctrl-0 = <&i2s0_bus>; 868 + pinctrl-names = "default"; 869 + status = "okay"; 870 + }; 871 + 872 + &mixer { 873 + status = "okay"; 874 + }; 875 + 876 + &mshc_0 { 877 + broken-cd; 878 + non-removable; 879 + card-detect-delay = <200>; 880 + vmmc-supply = <&ldo22_reg>; 881 + clock-frequency = <400000000>; 882 + samsung,dw-mshc-ciu-div = <0>; 883 + samsung,dw-mshc-sdr-timing = <2 3>; 884 + samsung,dw-mshc-ddr-timing = <1 2>; 885 + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 886 + pinctrl-names = "default"; 887 + status = "okay"; 888 + bus-width = <8>; 889 + cap-mmc-highspeed; 890 + }; 891 + 892 + &pmu_system_controller { 893 + assigned-clocks = <&pmu_system_controller 0>; 894 + assigned-clock-parents = <&clock CLK_XUSBXTI>; 895 + }; 896 + 897 + &pinctrl_0 { 898 + pinctrl-names = "default"; 899 + pinctrl-0 = <&sleep0>; 900 + 901 + mhl_int: mhl-int { 902 + samsung,pins = "gpf3-5"; 903 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 904 + }; 905 + 906 + i2c_mhl_bus: i2c-mhl-bus { 907 + samsung,pins = "gpf0-4", "gpf0-6"; 908 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 909 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 910 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 911 + }; 912 + 913 + sleep0: sleep-states { 914 + PIN_SLP(gpa0-0, INPUT, NONE); 915 + PIN_SLP(gpa0-1, OUT0, NONE); 916 + PIN_SLP(gpa0-2, INPUT, NONE); 917 + PIN_SLP(gpa0-3, INPUT, UP); 918 + PIN_SLP(gpa0-4, INPUT, NONE); 919 + PIN_SLP(gpa0-5, INPUT, DOWN); 920 + PIN_SLP(gpa0-6, INPUT, DOWN); 921 + PIN_SLP(gpa0-7, INPUT, UP); 922 + 923 + PIN_SLP(gpa1-0, INPUT, DOWN); 924 + PIN_SLP(gpa1-1, INPUT, DOWN); 925 + PIN_SLP(gpa1-2, INPUT, DOWN); 926 + PIN_SLP(gpa1-3, INPUT, DOWN); 927 + PIN_SLP(gpa1-4, INPUT, DOWN); 928 + PIN_SLP(gpa1-5, INPUT, DOWN); 929 + 930 + PIN_SLP(gpb-0, INPUT, NONE); 931 + PIN_SLP(gpb-1, INPUT, NONE); 932 + PIN_SLP(gpb-2, INPUT, NONE); 933 + PIN_SLP(gpb-3, INPUT, NONE); 934 + PIN_SLP(gpb-4, INPUT, DOWN); 935 + PIN_SLP(gpb-5, INPUT, UP); 936 + PIN_SLP(gpb-6, INPUT, DOWN); 937 + PIN_SLP(gpb-7, INPUT, DOWN); 938 + 939 + PIN_SLP(gpc0-0, INPUT, DOWN); 940 + PIN_SLP(gpc0-1, INPUT, DOWN); 941 + PIN_SLP(gpc0-2, INPUT, DOWN); 942 + PIN_SLP(gpc0-3, INPUT, DOWN); 943 + PIN_SLP(gpc0-4, INPUT, DOWN); 944 + 945 + PIN_SLP(gpc1-0, INPUT, NONE); 946 + PIN_SLP(gpc1-1, PREV, NONE); 947 + PIN_SLP(gpc1-2, INPUT, NONE); 948 + PIN_SLP(gpc1-3, INPUT, NONE); 949 + PIN_SLP(gpc1-4, INPUT, NONE); 950 + 951 + PIN_SLP(gpd0-0, INPUT, DOWN); 952 + PIN_SLP(gpd0-1, INPUT, DOWN); 953 + PIN_SLP(gpd0-2, INPUT, NONE); 954 + PIN_SLP(gpd0-3, INPUT, NONE); 955 + 956 + PIN_SLP(gpd1-0, INPUT, DOWN); 957 + PIN_SLP(gpd1-1, INPUT, DOWN); 958 + PIN_SLP(gpd1-2, INPUT, NONE); 959 + PIN_SLP(gpd1-3, INPUT, NONE); 960 + 961 + PIN_SLP(gpf0-0, INPUT, NONE); 962 + PIN_SLP(gpf0-1, INPUT, NONE); 963 + PIN_SLP(gpf0-2, INPUT, DOWN); 964 + PIN_SLP(gpf0-3, INPUT, DOWN); 965 + PIN_SLP(gpf0-4, INPUT, NONE); 966 + PIN_SLP(gpf0-5, INPUT, DOWN); 967 + PIN_SLP(gpf0-6, INPUT, NONE); 968 + PIN_SLP(gpf0-7, INPUT, DOWN); 969 + 970 + PIN_SLP(gpf1-0, INPUT, DOWN); 971 + PIN_SLP(gpf1-1, INPUT, DOWN); 972 + PIN_SLP(gpf1-2, INPUT, DOWN); 973 + PIN_SLP(gpf1-3, INPUT, DOWN); 974 + PIN_SLP(gpf1-4, INPUT, NONE); 975 + PIN_SLP(gpf1-5, INPUT, NONE); 976 + PIN_SLP(gpf1-6, INPUT, DOWN); 977 + PIN_SLP(gpf1-7, PREV, NONE); 978 + 979 + PIN_SLP(gpf2-0, PREV, NONE); 980 + PIN_SLP(gpf2-1, INPUT, DOWN); 981 + PIN_SLP(gpf2-2, INPUT, DOWN); 982 + PIN_SLP(gpf2-3, INPUT, DOWN); 983 + PIN_SLP(gpf2-4, INPUT, DOWN); 984 + PIN_SLP(gpf2-5, INPUT, DOWN); 985 + PIN_SLP(gpf2-6, INPUT, NONE); 986 + PIN_SLP(gpf2-7, INPUT, NONE); 987 + 988 + PIN_SLP(gpf3-0, INPUT, NONE); 989 + PIN_SLP(gpf3-1, PREV, NONE); 990 + PIN_SLP(gpf3-2, PREV, NONE); 991 + PIN_SLP(gpf3-3, PREV, NONE); 992 + PIN_SLP(gpf3-4, OUT1, NONE); 993 + PIN_SLP(gpf3-5, INPUT, DOWN); 994 + 995 + PIN_SLP(gpj0-0, PREV, NONE); 996 + PIN_SLP(gpj0-1, PREV, NONE); 997 + PIN_SLP(gpj0-2, PREV, NONE); 998 + PIN_SLP(gpj0-3, INPUT, DOWN); 999 + PIN_SLP(gpj0-4, PREV, NONE); 1000 + PIN_SLP(gpj0-5, PREV, NONE); 1001 + PIN_SLP(gpj0-6, INPUT, DOWN); 1002 + PIN_SLP(gpj0-7, INPUT, DOWN); 1003 + 1004 + PIN_SLP(gpj1-0, INPUT, DOWN); 1005 + PIN_SLP(gpj1-1, PREV, NONE); 1006 + PIN_SLP(gpj1-2, PREV, NONE); 1007 + PIN_SLP(gpj1-3, INPUT, DOWN); 1008 + PIN_SLP(gpj1-4, INPUT, DOWN); 1009 + }; 1010 + }; 1011 + 1012 + &pinctrl_1 { 1013 + pinctrl-names = "default"; 1014 + pinctrl-0 = <&sleep1>; 1015 + 1016 + hdmi_hpd: hdmi-hpd { 1017 + samsung,pins = "gpx3-7"; 1018 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 1019 + }; 1020 + 1021 + sleep1: sleep-states { 1022 + PIN_SLP(gpk0-0, PREV, NONE); 1023 + PIN_SLP(gpk0-1, PREV, NONE); 1024 + PIN_SLP(gpk0-2, OUT0, NONE); 1025 + PIN_SLP(gpk0-3, PREV, NONE); 1026 + PIN_SLP(gpk0-4, PREV, NONE); 1027 + PIN_SLP(gpk0-5, PREV, NONE); 1028 + PIN_SLP(gpk0-6, PREV, NONE); 1029 + 1030 + PIN_SLP(gpk1-0, INPUT, DOWN); 1031 + PIN_SLP(gpk1-1, INPUT, DOWN); 1032 + PIN_SLP(gpk1-2, INPUT, DOWN); 1033 + PIN_SLP(gpk1-3, PREV, NONE); 1034 + PIN_SLP(gpk1-4, PREV, NONE); 1035 + PIN_SLP(gpk1-5, PREV, NONE); 1036 + PIN_SLP(gpk1-6, PREV, NONE); 1037 + 1038 + PIN_SLP(gpk2-0, INPUT, DOWN); 1039 + PIN_SLP(gpk2-1, INPUT, DOWN); 1040 + PIN_SLP(gpk2-2, INPUT, DOWN); 1041 + PIN_SLP(gpk2-3, INPUT, DOWN); 1042 + PIN_SLP(gpk2-4, INPUT, DOWN); 1043 + PIN_SLP(gpk2-5, INPUT, DOWN); 1044 + PIN_SLP(gpk2-6, INPUT, DOWN); 1045 + 1046 + PIN_SLP(gpk3-0, OUT0, NONE); 1047 + PIN_SLP(gpk3-1, INPUT, NONE); 1048 + PIN_SLP(gpk3-2, INPUT, DOWN); 1049 + PIN_SLP(gpk3-3, INPUT, NONE); 1050 + PIN_SLP(gpk3-4, INPUT, NONE); 1051 + PIN_SLP(gpk3-5, INPUT, NONE); 1052 + PIN_SLP(gpk3-6, INPUT, NONE); 1053 + 1054 + PIN_SLP(gpl0-0, INPUT, DOWN); 1055 + PIN_SLP(gpl0-1, INPUT, DOWN); 1056 + PIN_SLP(gpl0-2, INPUT, DOWN); 1057 + PIN_SLP(gpl0-3, INPUT, DOWN); 1058 + PIN_SLP(gpl0-4, PREV, NONE); 1059 + PIN_SLP(gpl0-6, PREV, NONE); 1060 + 1061 + PIN_SLP(gpl1-0, INPUT, DOWN); 1062 + PIN_SLP(gpl1-1, INPUT, DOWN); 1063 + PIN_SLP(gpl2-0, INPUT, DOWN); 1064 + PIN_SLP(gpl2-1, INPUT, DOWN); 1065 + PIN_SLP(gpl2-2, INPUT, DOWN); 1066 + PIN_SLP(gpl2-3, INPUT, DOWN); 1067 + PIN_SLP(gpl2-4, INPUT, DOWN); 1068 + PIN_SLP(gpl2-5, INPUT, DOWN); 1069 + PIN_SLP(gpl2-6, PREV, NONE); 1070 + PIN_SLP(gpl2-7, INPUT, DOWN); 1071 + 1072 + PIN_SLP(gpm0-0, INPUT, DOWN); 1073 + PIN_SLP(gpm0-1, INPUT, DOWN); 1074 + PIN_SLP(gpm0-2, INPUT, DOWN); 1075 + PIN_SLP(gpm0-3, INPUT, DOWN); 1076 + PIN_SLP(gpm0-4, INPUT, DOWN); 1077 + PIN_SLP(gpm0-5, INPUT, DOWN); 1078 + PIN_SLP(gpm0-6, INPUT, DOWN); 1079 + PIN_SLP(gpm0-7, INPUT, DOWN); 1080 + 1081 + PIN_SLP(gpm1-0, INPUT, DOWN); 1082 + PIN_SLP(gpm1-1, INPUT, DOWN); 1083 + PIN_SLP(gpm1-2, INPUT, NONE); 1084 + PIN_SLP(gpm1-3, INPUT, NONE); 1085 + PIN_SLP(gpm1-4, INPUT, NONE); 1086 + PIN_SLP(gpm1-5, INPUT, NONE); 1087 + PIN_SLP(gpm1-6, INPUT, DOWN); 1088 + 1089 + PIN_SLP(gpm2-0, INPUT, NONE); 1090 + PIN_SLP(gpm2-1, INPUT, NONE); 1091 + PIN_SLP(gpm2-2, INPUT, DOWN); 1092 + PIN_SLP(gpm2-3, INPUT, DOWN); 1093 + PIN_SLP(gpm2-4, INPUT, DOWN); 1094 + 1095 + PIN_SLP(gpm3-0, PREV, NONE); 1096 + PIN_SLP(gpm3-1, PREV, NONE); 1097 + PIN_SLP(gpm3-2, PREV, NONE); 1098 + PIN_SLP(gpm3-3, OUT1, NONE); 1099 + PIN_SLP(gpm3-4, INPUT, DOWN); 1100 + PIN_SLP(gpm3-5, INPUT, DOWN); 1101 + PIN_SLP(gpm3-6, INPUT, DOWN); 1102 + PIN_SLP(gpm3-7, INPUT, DOWN); 1103 + 1104 + PIN_SLP(gpm4-0, INPUT, DOWN); 1105 + PIN_SLP(gpm4-1, INPUT, DOWN); 1106 + PIN_SLP(gpm4-2, INPUT, DOWN); 1107 + PIN_SLP(gpm4-3, INPUT, DOWN); 1108 + PIN_SLP(gpm4-4, INPUT, DOWN); 1109 + PIN_SLP(gpm4-5, INPUT, DOWN); 1110 + PIN_SLP(gpm4-6, INPUT, DOWN); 1111 + PIN_SLP(gpm4-7, INPUT, DOWN); 1112 + 1113 + PIN_SLP(gpy0-0, INPUT, DOWN); 1114 + PIN_SLP(gpy0-1, INPUT, DOWN); 1115 + PIN_SLP(gpy0-2, INPUT, DOWN); 1116 + PIN_SLP(gpy0-3, INPUT, DOWN); 1117 + PIN_SLP(gpy0-4, INPUT, DOWN); 1118 + PIN_SLP(gpy0-5, INPUT, DOWN); 1119 + 1120 + PIN_SLP(gpy1-0, INPUT, DOWN); 1121 + PIN_SLP(gpy1-1, INPUT, DOWN); 1122 + PIN_SLP(gpy1-2, INPUT, DOWN); 1123 + PIN_SLP(gpy1-3, INPUT, DOWN); 1124 + 1125 + PIN_SLP(gpy2-0, PREV, NONE); 1126 + PIN_SLP(gpy2-1, INPUT, DOWN); 1127 + PIN_SLP(gpy2-2, INPUT, NONE); 1128 + PIN_SLP(gpy2-3, INPUT, NONE); 1129 + PIN_SLP(gpy2-4, INPUT, NONE); 1130 + PIN_SLP(gpy2-5, INPUT, NONE); 1131 + 1132 + PIN_SLP(gpy3-0, INPUT, DOWN); 1133 + PIN_SLP(gpy3-1, INPUT, DOWN); 1134 + PIN_SLP(gpy3-2, INPUT, DOWN); 1135 + PIN_SLP(gpy3-3, INPUT, DOWN); 1136 + PIN_SLP(gpy3-4, INPUT, DOWN); 1137 + PIN_SLP(gpy3-5, INPUT, DOWN); 1138 + PIN_SLP(gpy3-6, INPUT, DOWN); 1139 + PIN_SLP(gpy3-7, INPUT, DOWN); 1140 + 1141 + PIN_SLP(gpy4-0, INPUT, DOWN); 1142 + PIN_SLP(gpy4-1, INPUT, DOWN); 1143 + PIN_SLP(gpy4-2, INPUT, DOWN); 1144 + PIN_SLP(gpy4-3, INPUT, DOWN); 1145 + PIN_SLP(gpy4-4, INPUT, DOWN); 1146 + PIN_SLP(gpy4-5, INPUT, DOWN); 1147 + PIN_SLP(gpy4-6, INPUT, DOWN); 1148 + PIN_SLP(gpy4-7, INPUT, DOWN); 1149 + 1150 + PIN_SLP(gpy5-0, INPUT, DOWN); 1151 + PIN_SLP(gpy5-1, INPUT, DOWN); 1152 + PIN_SLP(gpy5-2, INPUT, DOWN); 1153 + PIN_SLP(gpy5-3, INPUT, DOWN); 1154 + PIN_SLP(gpy5-4, INPUT, DOWN); 1155 + PIN_SLP(gpy5-5, INPUT, DOWN); 1156 + PIN_SLP(gpy5-6, INPUT, DOWN); 1157 + PIN_SLP(gpy5-7, INPUT, DOWN); 1158 + 1159 + PIN_SLP(gpy6-0, INPUT, DOWN); 1160 + PIN_SLP(gpy6-1, INPUT, DOWN); 1161 + PIN_SLP(gpy6-2, INPUT, DOWN); 1162 + PIN_SLP(gpy6-3, INPUT, DOWN); 1163 + PIN_SLP(gpy6-4, INPUT, DOWN); 1164 + PIN_SLP(gpy6-5, INPUT, DOWN); 1165 + PIN_SLP(gpy6-6, INPUT, DOWN); 1166 + PIN_SLP(gpy6-7, INPUT, DOWN); 1167 + }; 1168 + }; 1169 + 1170 + &pinctrl_2 { 1171 + pinctrl-names = "default"; 1172 + pinctrl-0 = <&sleep2>; 1173 + 1174 + sleep2: sleep-states { 1175 + PIN_SLP(gpz-0, INPUT, DOWN); 1176 + PIN_SLP(gpz-1, INPUT, DOWN); 1177 + PIN_SLP(gpz-2, INPUT, DOWN); 1178 + PIN_SLP(gpz-3, INPUT, DOWN); 1179 + PIN_SLP(gpz-4, INPUT, DOWN); 1180 + PIN_SLP(gpz-5, INPUT, DOWN); 1181 + PIN_SLP(gpz-6, INPUT, DOWN); 1182 + }; 1183 + }; 1184 + 1185 + &pinctrl_3 { 1186 + pinctrl-names = "default"; 1187 + pinctrl-0 = <&sleep3>; 1188 + 1189 + sleep3: sleep-states { 1190 + PIN_SLP(gpv0-0, INPUT, DOWN); 1191 + PIN_SLP(gpv0-1, INPUT, DOWN); 1192 + PIN_SLP(gpv0-2, INPUT, DOWN); 1193 + PIN_SLP(gpv0-3, INPUT, DOWN); 1194 + PIN_SLP(gpv0-4, INPUT, DOWN); 1195 + PIN_SLP(gpv0-5, INPUT, DOWN); 1196 + PIN_SLP(gpv0-6, INPUT, DOWN); 1197 + PIN_SLP(gpv0-7, INPUT, DOWN); 1198 + 1199 + PIN_SLP(gpv1-0, INPUT, DOWN); 1200 + PIN_SLP(gpv1-1, INPUT, DOWN); 1201 + PIN_SLP(gpv1-2, INPUT, DOWN); 1202 + PIN_SLP(gpv1-3, INPUT, DOWN); 1203 + PIN_SLP(gpv1-4, INPUT, DOWN); 1204 + PIN_SLP(gpv1-5, INPUT, DOWN); 1205 + PIN_SLP(gpv1-6, INPUT, DOWN); 1206 + PIN_SLP(gpv1-7, INPUT, DOWN); 1207 + 1208 + PIN_SLP(gpv2-0, INPUT, DOWN); 1209 + PIN_SLP(gpv2-1, INPUT, DOWN); 1210 + PIN_SLP(gpv2-2, INPUT, DOWN); 1211 + PIN_SLP(gpv2-3, INPUT, DOWN); 1212 + PIN_SLP(gpv2-4, INPUT, DOWN); 1213 + PIN_SLP(gpv2-5, INPUT, DOWN); 1214 + PIN_SLP(gpv2-6, INPUT, DOWN); 1215 + PIN_SLP(gpv2-7, INPUT, DOWN); 1216 + 1217 + PIN_SLP(gpv3-0, INPUT, DOWN); 1218 + PIN_SLP(gpv3-1, INPUT, DOWN); 1219 + PIN_SLP(gpv3-2, INPUT, DOWN); 1220 + PIN_SLP(gpv3-3, INPUT, DOWN); 1221 + PIN_SLP(gpv3-4, INPUT, DOWN); 1222 + PIN_SLP(gpv3-5, INPUT, DOWN); 1223 + PIN_SLP(gpv3-6, INPUT, DOWN); 1224 + PIN_SLP(gpv3-7, INPUT, DOWN); 1225 + 1226 + PIN_SLP(gpv4-0, INPUT, DOWN); 1227 + }; 1228 + }; 1229 + 1230 + &pwm { 1231 + pinctrl-0 = <&pwm0_out>; 1232 + pinctrl-names = "default"; 1233 + samsung,pwm-outputs = <0>; 1234 + status = "okay"; 1235 + }; 1236 + 1237 + &rtc { 1238 + status = "okay"; 1239 + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; 1240 + clock-names = "rtc", "rtc_src"; 1241 + }; 1242 + 1243 + &sdhci_2 { 1244 + bus-width = <4>; 1245 + cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; 1246 + cd-inverted; 1247 + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; 1248 + pinctrl-names = "default"; 1249 + vmmc-supply = <&ldo21_reg>; 1250 + status = "okay"; 1251 + }; 1252 + 1253 + &sdhci_3 { 1254 + #address-cells = <1>; 1255 + #size-cells = <0>; 1256 + non-removable; 1257 + bus-width = <4>; 1258 + 1259 + mmc-pwrseq = <&wlan_pwrseq>; 1260 + pinctrl-names = "default"; 1261 + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; 1262 + status = "okay"; 1263 + 1264 + brcmf: wifi@1 { 1265 + reg = <1>; 1266 + compatible = "brcm,bcm4329-fmac"; 1267 + interrupt-parent = <&gpx2>; 1268 + interrupts = <5 IRQ_TYPE_NONE>; 1269 + interrupt-names = "host-wake"; 1270 + }; 1271 + }; 1272 + 1273 + &serial_0 { 1274 + status = "okay"; 1275 + }; 1276 + 1277 + &serial_1 { 1278 + status = "okay"; 1279 + }; 1280 + 1281 + &serial_2 { 1282 + status = "okay"; 1283 + }; 1284 + 1285 + &serial_3 { 1286 + status = "okay"; 1287 + }; 1288 + 1289 + &spi_1 { 1290 + pinctrl-names = "default"; 1291 + pinctrl-0 = <&spi1_bus>; 1292 + cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; 1293 + status = "okay"; 1294 + 1295 + s5c73m3_spi: s5c73m3@0 { 1296 + compatible = "samsung,s5c73m3"; 1297 + spi-max-frequency = <50000000>; 1298 + reg = <0>; 1299 + controller-data { 1300 + samsung,spi-feedback-delay = <2>; 1301 + }; 1302 + }; 1303 + }; 1304 + 1305 + &tmu { 1306 + vtmu-supply = <&ldo10_reg>; 1307 + status = "okay"; 1308 + };
+77
arch/arm/boot/dts/exynos4412-n710x.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /dts-v1/; 3 + #include "exynos4412-midas.dtsi" 4 + 5 + / { 6 + compatible = "samsung,n710x", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; 7 + model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412"; 8 + 9 + memory@40000000 { 10 + device_type = "memory"; 11 + reg = <0x40000000 0x80000000>; 12 + }; 13 + 14 + /* bootargs are passed in by bootloader */ 15 + 16 + regulators { 17 + cam_vdda_reg: voltage-regulator-9 { 18 + compatible = "regulator-fixed"; 19 + regulator-name = "CAM_SENSOR_CORE_1.2V"; 20 + regulator-min-microvolt = <1200000>; 21 + regulator-max-microvolt = <1200000>; 22 + gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>; 23 + enable-active-high; 24 + }; 25 + }; 26 + }; 27 + 28 + &buck9_reg { 29 + maxim,ena-gpios = <&gpm1 0 GPIO_ACTIVE_HIGH>; 30 + }; 31 + 32 + &cam_af_reg { 33 + gpio = <&gpm1 1 GPIO_ACTIVE_HIGH>; 34 + status = "okay"; 35 + }; 36 + 37 + &cam_io_reg { 38 + gpio = <&gpm0 7 GPIO_ACTIVE_HIGH>; 39 + status = "okay"; 40 + }; 41 + 42 + &i2c_3 { 43 + samsung,i2c-sda-delay = <100>; 44 + samsung,i2c-slave-addr = <0x10>; 45 + samsung,i2c-max-bus-freq = <400000>; 46 + pinctrl-0 = <&i2c3_bus>; 47 + pinctrl-names = "default"; 48 + status = "okay"; 49 + 50 + mms152-touchscreen@48 { 51 + compatible = "melfas,mms152"; 52 + reg = <0x48>; 53 + interrupt-parent = <&gpm2>; 54 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 55 + x-size = <720>; 56 + y-size = <1280>; 57 + avdd-supply = <&ldo23_reg>; 58 + vdd-supply = <&ldo24_reg>; 59 + }; 60 + }; 61 + 62 + &ldo13_reg { 63 + regulator-name = "VCC_1.8V_LCD"; 64 + regulator-always-on; 65 + }; 66 + 67 + &ldo25_reg { 68 + regulator-name = "VCI_3.0V_LCD"; 69 + regulator-min-microvolt = <3000000>; 70 + regulator-max-microvolt = <3000000>; 71 + }; 72 + 73 + &s5c73m3 { 74 + standby-gpios = <&gpm0 6 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ 75 + vdda-supply = <&cam_vdda_reg>; 76 + status = "okay"; 77 + };
+6 -6
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
··· 61 61 reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; 62 62 }; 63 63 64 - camera { 65 - status = "okay"; 66 - pinctrl-names = "default"; 67 - pinctrl-0 = <>; 68 - }; 69 - 70 64 fixed-rate-clocks { 71 65 xxti { 72 66 compatible = "samsung,clock-xxti"; ··· 134 140 &bus_mfc { 135 141 devfreq = <&bus_leftbus>; 136 142 status = "okay"; 143 + }; 144 + 145 + &camera { 146 + status = "okay"; 147 + pinctrl-names = "default"; 148 + pinctrl-0 = <>; 137 149 }; 138 150 139 151 &clock_audss {
+940 -942
arch/arm/boot/dts/exynos4412-pinctrl.dtsi
··· 18 18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ 19 19 } 20 20 21 - / { 22 - pinctrl_0: pinctrl@11400000 { 23 - gpa0: gpa0 { 24 - gpio-controller; 25 - #gpio-cells = <2>; 26 - 27 - interrupt-controller; 28 - #interrupt-cells = <2>; 29 - }; 30 - 31 - gpa1: gpa1 { 32 - gpio-controller; 33 - #gpio-cells = <2>; 34 - 35 - interrupt-controller; 36 - #interrupt-cells = <2>; 37 - }; 38 - 39 - gpb: gpb { 40 - gpio-controller; 41 - #gpio-cells = <2>; 42 - 43 - interrupt-controller; 44 - #interrupt-cells = <2>; 45 - }; 46 - 47 - gpc0: gpc0 { 48 - gpio-controller; 49 - #gpio-cells = <2>; 50 - 51 - interrupt-controller; 52 - #interrupt-cells = <2>; 53 - }; 54 - 55 - gpc1: gpc1 { 56 - gpio-controller; 57 - #gpio-cells = <2>; 58 - 59 - interrupt-controller; 60 - #interrupt-cells = <2>; 61 - }; 62 - 63 - gpd0: gpd0 { 64 - gpio-controller; 65 - #gpio-cells = <2>; 66 - 67 - interrupt-controller; 68 - #interrupt-cells = <2>; 69 - }; 70 - 71 - gpd1: gpd1 { 72 - gpio-controller; 73 - #gpio-cells = <2>; 74 - 75 - interrupt-controller; 76 - #interrupt-cells = <2>; 77 - }; 78 - 79 - gpf0: gpf0 { 80 - gpio-controller; 81 - #gpio-cells = <2>; 82 - 83 - interrupt-controller; 84 - #interrupt-cells = <2>; 85 - }; 86 - 87 - gpf1: gpf1 { 88 - gpio-controller; 89 - #gpio-cells = <2>; 90 - 91 - interrupt-controller; 92 - #interrupt-cells = <2>; 93 - }; 94 - 95 - gpf2: gpf2 { 96 - gpio-controller; 97 - #gpio-cells = <2>; 98 - 99 - interrupt-controller; 100 - #interrupt-cells = <2>; 101 - }; 102 - 103 - gpf3: gpf3 { 104 - gpio-controller; 105 - #gpio-cells = <2>; 106 - 107 - interrupt-controller; 108 - #interrupt-cells = <2>; 109 - }; 110 - 111 - gpj0: gpj0 { 112 - gpio-controller; 113 - #gpio-cells = <2>; 114 - 115 - interrupt-controller; 116 - #interrupt-cells = <2>; 117 - }; 118 - 119 - gpj1: gpj1 { 120 - gpio-controller; 121 - #gpio-cells = <2>; 122 - 123 - interrupt-controller; 124 - #interrupt-cells = <2>; 125 - }; 126 - 127 - uart0_data: uart0-data { 128 - samsung,pins = "gpa0-0", "gpa0-1"; 129 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 130 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 131 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 132 - }; 133 - 134 - uart0_fctl: uart0-fctl { 135 - samsung,pins = "gpa0-2", "gpa0-3"; 136 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 137 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 138 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 139 - }; 140 - 141 - uart1_data: uart1-data { 142 - samsung,pins = "gpa0-4", "gpa0-5"; 143 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 144 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 145 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 146 - }; 147 - 148 - uart1_fctl: uart1-fctl { 149 - samsung,pins = "gpa0-6", "gpa0-7"; 150 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 151 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 152 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 153 - }; 154 - 155 - i2c2_bus: i2c2-bus { 156 - samsung,pins = "gpa0-6", "gpa0-7"; 157 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 158 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 159 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 160 - }; 161 - 162 - uart2_data: uart2-data { 163 - samsung,pins = "gpa1-0", "gpa1-1"; 164 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 165 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 166 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 167 - }; 168 - 169 - uart2_fctl: uart2-fctl { 170 - samsung,pins = "gpa1-2", "gpa1-3"; 171 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 172 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 173 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 174 - }; 175 - 176 - uart_audio_a: uart-audio-a { 177 - samsung,pins = "gpa1-0", "gpa1-1"; 178 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 179 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 180 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 181 - }; 182 - 183 - i2c3_bus: i2c3-bus { 184 - samsung,pins = "gpa1-2", "gpa1-3"; 185 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 186 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 187 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 188 - }; 189 - 190 - uart3_data: uart3-data { 191 - samsung,pins = "gpa1-4", "gpa1-5"; 192 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 193 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 194 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 195 - }; 196 - 197 - uart_audio_b: uart-audio-b { 198 - samsung,pins = "gpa1-4", "gpa1-5"; 199 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 200 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 201 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 202 - }; 203 - 204 - spi0_bus: spi0-bus { 205 - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; 206 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 207 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 208 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 209 - }; 210 - 211 - i2c4_bus: i2c4-bus { 212 - samsung,pins = "gpb-0", "gpb-1"; 213 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 214 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 215 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 216 - }; 217 - 218 - spi1_bus: spi1-bus { 219 - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; 220 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 221 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 222 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 223 - }; 224 - 225 - i2c5_bus: i2c5-bus { 226 - samsung,pins = "gpb-2", "gpb-3"; 227 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 228 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 229 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 230 - }; 231 - 232 - i2s1_bus: i2s1-bus { 233 - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 234 - "gpc0-4"; 235 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 236 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 237 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 238 - }; 239 - 240 - pcm1_bus: pcm1-bus { 241 - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 242 - "gpc0-4"; 243 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 244 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 245 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 246 - }; 247 - 248 - ac97_bus: ac97-bus { 249 - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 250 - "gpc0-4"; 251 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 252 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 253 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 254 - }; 255 - 256 - i2s2_bus: i2s2-bus { 257 - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", 258 - "gpc1-4"; 259 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 260 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 261 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 262 - }; 263 - 264 - pcm2_bus: pcm2-bus { 265 - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", 266 - "gpc1-4"; 267 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 268 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 269 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 270 - }; 271 - 272 - spdif_bus: spdif-bus { 273 - samsung,pins = "gpc1-0", "gpc1-1"; 274 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 275 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 276 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 277 - }; 278 - 279 - i2c6_bus: i2c6-bus { 280 - samsung,pins = "gpc1-3", "gpc1-4"; 281 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 282 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 283 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 284 - }; 285 - 286 - spi2_bus: spi2-bus { 287 - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; 288 - samsung,pin-function = <EXYNOS_PIN_FUNC_5>; 289 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 290 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 291 - }; 292 - 293 - pwm0_out: pwm0-out { 294 - samsung,pins = "gpd0-0"; 295 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 296 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 297 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 298 - }; 299 - 300 - pwm1_out: pwm1-out { 301 - samsung,pins = "gpd0-1"; 302 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 303 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 304 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 305 - }; 306 - 307 - lcd_ctrl: lcd-ctrl { 308 - samsung,pins = "gpd0-0", "gpd0-1"; 309 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 310 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 311 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 312 - }; 313 - 314 - i2c7_bus: i2c7-bus { 315 - samsung,pins = "gpd0-2", "gpd0-3"; 316 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 317 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 318 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 319 - }; 320 - 321 - pwm2_out: pwm2-out { 322 - samsung,pins = "gpd0-2"; 323 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 324 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 325 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 326 - }; 327 - 328 - pwm3_out: pwm3-out { 329 - samsung,pins = "gpd0-3"; 330 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 331 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 332 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 333 - }; 334 - 335 - i2c0_bus: i2c0-bus { 336 - samsung,pins = "gpd1-0", "gpd1-1"; 337 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 338 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 339 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 340 - }; 341 - 342 - mipi0_clk: mipi0-clk { 343 - samsung,pins = "gpd1-0", "gpd1-1"; 344 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 345 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 346 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 347 - }; 348 - 349 - i2c1_bus: i2c1-bus { 350 - samsung,pins = "gpd1-2", "gpd1-3"; 351 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 352 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 353 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 354 - }; 355 - 356 - mipi1_clk: mipi1-clk { 357 - samsung,pins = "gpd1-2", "gpd1-3"; 358 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 359 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 360 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 361 - }; 362 - 363 - lcd_clk: lcd-clk { 364 - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; 365 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 366 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 367 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 368 - }; 369 - 370 - lcd_data16: lcd-data-width16 { 371 - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", 372 - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", 373 - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", 374 - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; 375 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 376 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 377 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 378 - }; 379 - 380 - lcd_data18: lcd-data-width18 { 381 - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", 382 - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", 383 - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", 384 - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", 385 - "gpf3-2", "gpf3-3"; 386 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 387 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 388 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 389 - }; 390 - 391 - lcd_data24: lcd-data-width24 { 392 - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", 393 - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", 394 - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", 395 - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", 396 - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", 397 - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; 398 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 399 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 400 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 401 - }; 402 - 403 - lcd_ldi: lcd-ldi { 404 - samsung,pins = "gpf3-4"; 405 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 406 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 407 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 408 - }; 409 - 410 - cam_port_a_io: cam-port-a-io { 411 - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", 412 - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", 413 - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; 414 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 415 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 416 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 417 - }; 418 - 419 - cam_port_a_clk_active: cam-port-a-clk-active { 420 - samsung,pins = "gpj1-3"; 421 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 422 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 423 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 424 - }; 425 - 426 - cam_port_a_clk_idle: cam-port-a-clk-idle { 427 - samsung,pins = "gpj1-3"; 428 - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 429 - samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 430 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 431 - }; 21 + &pinctrl_0 { 22 + gpa0: gpa0 { 23 + gpio-controller; 24 + #gpio-cells = <2>; 25 + 26 + interrupt-controller; 27 + #interrupt-cells = <2>; 432 28 }; 433 29 434 - pinctrl_1: pinctrl@11000000 { 435 - gpk0: gpk0 { 436 - gpio-controller; 437 - #gpio-cells = <2>; 438 - 439 - interrupt-controller; 440 - #interrupt-cells = <2>; 441 - }; 442 - 443 - gpk1: gpk1 { 444 - gpio-controller; 445 - #gpio-cells = <2>; 446 - 447 - interrupt-controller; 448 - #interrupt-cells = <2>; 449 - }; 450 - 451 - gpk2: gpk2 { 452 - gpio-controller; 453 - #gpio-cells = <2>; 454 - 455 - interrupt-controller; 456 - #interrupt-cells = <2>; 457 - }; 458 - 459 - gpk3: gpk3 { 460 - gpio-controller; 461 - #gpio-cells = <2>; 462 - 463 - interrupt-controller; 464 - #interrupt-cells = <2>; 465 - }; 466 - 467 - gpl0: gpl0 { 468 - gpio-controller; 469 - #gpio-cells = <2>; 470 - 471 - interrupt-controller; 472 - #interrupt-cells = <2>; 473 - }; 474 - 475 - gpl1: gpl1 { 476 - gpio-controller; 477 - #gpio-cells = <2>; 478 - 479 - interrupt-controller; 480 - #interrupt-cells = <2>; 481 - }; 482 - 483 - gpl2: gpl2 { 484 - gpio-controller; 485 - #gpio-cells = <2>; 486 - 487 - interrupt-controller; 488 - #interrupt-cells = <2>; 489 - }; 490 - 491 - gpm0: gpm0 { 492 - gpio-controller; 493 - #gpio-cells = <2>; 494 - 495 - interrupt-controller; 496 - #interrupt-cells = <2>; 497 - }; 498 - 499 - gpm1: gpm1 { 500 - gpio-controller; 501 - #gpio-cells = <2>; 502 - 503 - interrupt-controller; 504 - #interrupt-cells = <2>; 505 - }; 506 - 507 - gpm2: gpm2 { 508 - gpio-controller; 509 - #gpio-cells = <2>; 510 - 511 - interrupt-controller; 512 - #interrupt-cells = <2>; 513 - }; 514 - 515 - gpm3: gpm3 { 516 - gpio-controller; 517 - #gpio-cells = <2>; 518 - 519 - interrupt-controller; 520 - #interrupt-cells = <2>; 521 - }; 522 - 523 - gpm4: gpm4 { 524 - gpio-controller; 525 - #gpio-cells = <2>; 526 - 527 - interrupt-controller; 528 - #interrupt-cells = <2>; 529 - }; 530 - 531 - gpy0: gpy0 { 532 - gpio-controller; 533 - #gpio-cells = <2>; 534 - }; 535 - 536 - gpy1: gpy1 { 537 - gpio-controller; 538 - #gpio-cells = <2>; 539 - }; 540 - 541 - gpy2: gpy2 { 542 - gpio-controller; 543 - #gpio-cells = <2>; 544 - }; 545 - 546 - gpy3: gpy3 { 547 - gpio-controller; 548 - #gpio-cells = <2>; 549 - }; 550 - 551 - gpy4: gpy4 { 552 - gpio-controller; 553 - #gpio-cells = <2>; 554 - }; 555 - 556 - gpy5: gpy5 { 557 - gpio-controller; 558 - #gpio-cells = <2>; 559 - }; 560 - 561 - gpy6: gpy6 { 562 - gpio-controller; 563 - #gpio-cells = <2>; 564 - }; 565 - 566 - gpx0: gpx0 { 567 - gpio-controller; 568 - #gpio-cells = <2>; 569 - 570 - interrupt-controller; 571 - interrupt-parent = <&gic>; 572 - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 573 - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 574 - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 575 - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 576 - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 577 - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 578 - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 579 - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 580 - #interrupt-cells = <2>; 581 - }; 582 - 583 - gpx1: gpx1 { 584 - gpio-controller; 585 - #gpio-cells = <2>; 586 - 587 - interrupt-controller; 588 - interrupt-parent = <&gic>; 589 - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 590 - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 591 - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 592 - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 593 - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 594 - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 595 - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 596 - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 597 - #interrupt-cells = <2>; 598 - }; 599 - 600 - gpx2: gpx2 { 601 - gpio-controller; 602 - #gpio-cells = <2>; 603 - 604 - interrupt-controller; 605 - #interrupt-cells = <2>; 606 - }; 607 - 608 - gpx3: gpx3 { 609 - gpio-controller; 610 - #gpio-cells = <2>; 611 - 612 - interrupt-controller; 613 - #interrupt-cells = <2>; 614 - }; 615 - 616 - sd0_clk: sd0-clk { 617 - samsung,pins = "gpk0-0"; 618 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 619 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 620 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 621 - }; 622 - 623 - sd0_cmd: sd0-cmd { 624 - samsung,pins = "gpk0-1"; 625 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 626 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 627 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 628 - }; 629 - 630 - sd0_cd: sd0-cd { 631 - samsung,pins = "gpk0-2"; 632 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 633 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 634 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 635 - }; 636 - 637 - sd0_bus1: sd0-bus-width1 { 638 - samsung,pins = "gpk0-3"; 639 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 640 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 641 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 642 - }; 643 - 644 - sd0_bus4: sd0-bus-width4 { 645 - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 646 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 647 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 648 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 649 - }; 650 - 651 - sd0_bus8: sd0-bus-width8 { 652 - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 653 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 654 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 655 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 656 - }; 657 - 658 - sd4_clk: sd4-clk { 659 - samsung,pins = "gpk0-0"; 660 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 661 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 662 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 663 - }; 664 - 665 - sd4_cmd: sd4-cmd { 666 - samsung,pins = "gpk0-1"; 667 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 668 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 669 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 670 - }; 671 - 672 - sd4_cd: sd4-cd { 673 - samsung,pins = "gpk0-2"; 674 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 675 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 676 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 677 - }; 678 - 679 - sd4_bus1: sd4-bus-width1 { 680 - samsung,pins = "gpk0-3"; 681 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 682 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 683 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 684 - }; 685 - 686 - sd4_bus4: sd4-bus-width4 { 687 - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 688 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 689 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 690 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 691 - }; 692 - 693 - sd4_bus8: sd4-bus-width8 { 694 - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 695 - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 696 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 697 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 698 - }; 699 - 700 - sd1_clk: sd1-clk { 701 - samsung,pins = "gpk1-0"; 702 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 703 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 704 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 705 - }; 706 - 707 - sd1_cmd: sd1-cmd { 708 - samsung,pins = "gpk1-1"; 709 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 710 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 711 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 712 - }; 713 - 714 - sd1_cd: sd1-cd { 715 - samsung,pins = "gpk1-2"; 716 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 717 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 718 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 719 - }; 720 - 721 - sd1_bus1: sd1-bus-width1 { 722 - samsung,pins = "gpk1-3"; 723 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 724 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 725 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 726 - }; 727 - 728 - sd1_bus4: sd1-bus-width4 { 729 - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 730 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 731 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 732 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 733 - }; 734 - 735 - sd2_clk: sd2-clk { 736 - samsung,pins = "gpk2-0"; 737 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 738 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 739 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 740 - }; 741 - 742 - sd2_cmd: sd2-cmd { 743 - samsung,pins = "gpk2-1"; 744 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 745 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 746 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 747 - }; 748 - 749 - sd2_cd: sd2-cd { 750 - samsung,pins = "gpk2-2"; 751 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 752 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 753 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 754 - }; 755 - 756 - sd2_bus1: sd2-bus-width1 { 757 - samsung,pins = "gpk2-3"; 758 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 759 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 760 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 761 - }; 762 - 763 - sd2_bus4: sd2-bus-width4 { 764 - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; 765 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 766 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 767 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 768 - }; 769 - 770 - sd2_bus8: sd2-bus-width8 { 771 - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 772 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 773 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 774 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 775 - }; 776 - 777 - sd3_clk: sd3-clk { 778 - samsung,pins = "gpk3-0"; 779 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 780 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 781 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 782 - }; 783 - 784 - sd3_cmd: sd3-cmd { 785 - samsung,pins = "gpk3-1"; 786 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 787 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 788 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 789 - }; 790 - 791 - sd3_cd: sd3-cd { 792 - samsung,pins = "gpk3-2"; 793 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 794 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 795 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 796 - }; 797 - 798 - sd3_bus1: sd3-bus-width1 { 799 - samsung,pins = "gpk3-3"; 800 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 801 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 802 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 803 - }; 804 - 805 - sd3_bus4: sd3-bus-width4 { 806 - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 807 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 808 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 809 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 810 - }; 811 - 812 - cam_port_b_io: cam-port-b-io { 813 - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", 814 - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", 815 - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; 816 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 817 - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 818 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 819 - }; 820 - 821 - cam_port_b_clk_active: cam-port-b-clk-active { 822 - samsung,pins = "gpm2-2"; 823 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 824 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 825 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 826 - }; 827 - 828 - cam_port_b_clk_idle: cam-port-b-clk-idle { 829 - samsung,pins = "gpm2-2"; 830 - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 831 - samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 832 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 833 - }; 834 - 835 - eint0: ext-int0 { 836 - samsung,pins = "gpx0-0"; 837 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 838 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 839 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 840 - }; 841 - 842 - eint8: ext-int8 { 843 - samsung,pins = "gpx1-0"; 844 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 845 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 846 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 847 - }; 848 - 849 - eint15: ext-int15 { 850 - samsung,pins = "gpx1-7"; 851 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 852 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 853 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 854 - }; 855 - 856 - eint16: ext-int16 { 857 - samsung,pins = "gpx2-0"; 858 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 859 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 860 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 861 - }; 862 - 863 - eint31: ext-int31 { 864 - samsung,pins = "gpx3-7"; 865 - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 866 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 867 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 868 - }; 869 - 870 - fimc_is_i2c0: fimc-is-i2c0 { 871 - samsung,pins = "gpm4-0", "gpm4-1"; 872 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 873 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 874 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 875 - }; 876 - 877 - fimc_is_i2c1: fimc-is-i2c1 { 878 - samsung,pins = "gpm4-2", "gpm4-3"; 879 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 880 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 881 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 882 - }; 883 - 884 - fimc_is_uart: fimc-is-uart { 885 - samsung,pins = "gpm3-5", "gpm3-7"; 886 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 887 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 888 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 889 - }; 890 - 891 - hdmi_cec: hdmi-cec { 892 - samsung,pins = "gpx3-6"; 893 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 894 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 895 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 896 - }; 30 + gpa1: gpa1 { 31 + gpio-controller; 32 + #gpio-cells = <2>; 33 + 34 + interrupt-controller; 35 + #interrupt-cells = <2>; 897 36 }; 898 37 899 - pinctrl_2: pinctrl@3860000 { 900 - gpz: gpz { 901 - gpio-controller; 902 - #gpio-cells = <2>; 38 + gpb: gpb { 39 + gpio-controller; 40 + #gpio-cells = <2>; 903 41 904 - interrupt-controller; 905 - #interrupt-cells = <2>; 906 - }; 907 - 908 - i2s0_bus: i2s0-bus { 909 - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", 910 - "gpz-4", "gpz-5", "gpz-6"; 911 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 912 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 913 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 914 - }; 915 - 916 - pcm0_bus: pcm0-bus { 917 - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", 918 - "gpz-4"; 919 - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 920 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 921 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 922 - }; 42 + interrupt-controller; 43 + #interrupt-cells = <2>; 923 44 }; 924 45 925 - pinctrl_3: pinctrl@106e0000 { 926 - gpv0: gpv0 { 927 - gpio-controller; 928 - #gpio-cells = <2>; 46 + gpc0: gpc0 { 47 + gpio-controller; 48 + #gpio-cells = <2>; 929 49 930 - interrupt-controller; 931 - #interrupt-cells = <2>; 932 - }; 50 + interrupt-controller; 51 + #interrupt-cells = <2>; 52 + }; 933 53 934 - gpv1: gpv1 { 935 - gpio-controller; 936 - #gpio-cells = <2>; 54 + gpc1: gpc1 { 55 + gpio-controller; 56 + #gpio-cells = <2>; 937 57 938 - interrupt-controller; 939 - #interrupt-cells = <2>; 940 - }; 58 + interrupt-controller; 59 + #interrupt-cells = <2>; 60 + }; 941 61 942 - gpv2: gpv2 { 943 - gpio-controller; 944 - #gpio-cells = <2>; 62 + gpd0: gpd0 { 63 + gpio-controller; 64 + #gpio-cells = <2>; 945 65 946 - interrupt-controller; 947 - #interrupt-cells = <2>; 948 - }; 66 + interrupt-controller; 67 + #interrupt-cells = <2>; 68 + }; 949 69 950 - gpv3: gpv3 { 951 - gpio-controller; 952 - #gpio-cells = <2>; 70 + gpd1: gpd1 { 71 + gpio-controller; 72 + #gpio-cells = <2>; 953 73 954 - interrupt-controller; 955 - #interrupt-cells = <2>; 956 - }; 74 + interrupt-controller; 75 + #interrupt-cells = <2>; 76 + }; 957 77 958 - gpv4: gpv4 { 959 - gpio-controller; 960 - #gpio-cells = <2>; 78 + gpf0: gpf0 { 79 + gpio-controller; 80 + #gpio-cells = <2>; 961 81 962 - interrupt-controller; 963 - #interrupt-cells = <2>; 964 - }; 82 + interrupt-controller; 83 + #interrupt-cells = <2>; 84 + }; 965 85 966 - c2c_bus: c2c-bus { 967 - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", 968 - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", 969 - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", 970 - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", 971 - "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", 972 - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", 973 - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", 974 - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", 975 - "gpv4-0", "gpv4-1"; 976 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 977 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 978 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 979 - }; 86 + gpf1: gpf1 { 87 + gpio-controller; 88 + #gpio-cells = <2>; 89 + 90 + interrupt-controller; 91 + #interrupt-cells = <2>; 92 + }; 93 + 94 + gpf2: gpf2 { 95 + gpio-controller; 96 + #gpio-cells = <2>; 97 + 98 + interrupt-controller; 99 + #interrupt-cells = <2>; 100 + }; 101 + 102 + gpf3: gpf3 { 103 + gpio-controller; 104 + #gpio-cells = <2>; 105 + 106 + interrupt-controller; 107 + #interrupt-cells = <2>; 108 + }; 109 + 110 + gpj0: gpj0 { 111 + gpio-controller; 112 + #gpio-cells = <2>; 113 + 114 + interrupt-controller; 115 + #interrupt-cells = <2>; 116 + }; 117 + 118 + gpj1: gpj1 { 119 + gpio-controller; 120 + #gpio-cells = <2>; 121 + 122 + interrupt-controller; 123 + #interrupt-cells = <2>; 124 + }; 125 + 126 + uart0_data: uart0-data { 127 + samsung,pins = "gpa0-0", "gpa0-1"; 128 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 129 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 130 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 131 + }; 132 + 133 + uart0_fctl: uart0-fctl { 134 + samsung,pins = "gpa0-2", "gpa0-3"; 135 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 136 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 137 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 138 + }; 139 + 140 + uart1_data: uart1-data { 141 + samsung,pins = "gpa0-4", "gpa0-5"; 142 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 143 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 144 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 145 + }; 146 + 147 + uart1_fctl: uart1-fctl { 148 + samsung,pins = "gpa0-6", "gpa0-7"; 149 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 150 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 151 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 152 + }; 153 + 154 + i2c2_bus: i2c2-bus { 155 + samsung,pins = "gpa0-6", "gpa0-7"; 156 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 157 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 158 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 159 + }; 160 + 161 + uart2_data: uart2-data { 162 + samsung,pins = "gpa1-0", "gpa1-1"; 163 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 164 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 165 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 166 + }; 167 + 168 + uart2_fctl: uart2-fctl { 169 + samsung,pins = "gpa1-2", "gpa1-3"; 170 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 171 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 172 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 173 + }; 174 + 175 + uart_audio_a: uart-audio-a { 176 + samsung,pins = "gpa1-0", "gpa1-1"; 177 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 178 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 179 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 180 + }; 181 + 182 + i2c3_bus: i2c3-bus { 183 + samsung,pins = "gpa1-2", "gpa1-3"; 184 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 185 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 186 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 187 + }; 188 + 189 + uart3_data: uart3-data { 190 + samsung,pins = "gpa1-4", "gpa1-5"; 191 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 192 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 193 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 194 + }; 195 + 196 + uart_audio_b: uart-audio-b { 197 + samsung,pins = "gpa1-4", "gpa1-5"; 198 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 199 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 200 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 201 + }; 202 + 203 + spi0_bus: spi0-bus { 204 + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; 205 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 206 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 207 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 208 + }; 209 + 210 + i2c4_bus: i2c4-bus { 211 + samsung,pins = "gpb-0", "gpb-1"; 212 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 213 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 214 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 215 + }; 216 + 217 + spi1_bus: spi1-bus { 218 + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; 219 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 220 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 221 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 222 + }; 223 + 224 + i2c5_bus: i2c5-bus { 225 + samsung,pins = "gpb-2", "gpb-3"; 226 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 227 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 228 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 229 + }; 230 + 231 + i2s1_bus: i2s1-bus { 232 + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 233 + "gpc0-4"; 234 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 235 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 236 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 237 + }; 238 + 239 + pcm1_bus: pcm1-bus { 240 + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 241 + "gpc0-4"; 242 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 243 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 244 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 245 + }; 246 + 247 + ac97_bus: ac97-bus { 248 + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", 249 + "gpc0-4"; 250 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 251 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 252 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 253 + }; 254 + 255 + i2s2_bus: i2s2-bus { 256 + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", 257 + "gpc1-4"; 258 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 259 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 260 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 261 + }; 262 + 263 + pcm2_bus: pcm2-bus { 264 + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", 265 + "gpc1-4"; 266 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 267 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 268 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 269 + }; 270 + 271 + spdif_bus: spdif-bus { 272 + samsung,pins = "gpc1-0", "gpc1-1"; 273 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 274 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 275 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 276 + }; 277 + 278 + i2c6_bus: i2c6-bus { 279 + samsung,pins = "gpc1-3", "gpc1-4"; 280 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 281 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 282 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 283 + }; 284 + 285 + spi2_bus: spi2-bus { 286 + samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; 287 + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; 288 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 289 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 290 + }; 291 + 292 + pwm0_out: pwm0-out { 293 + samsung,pins = "gpd0-0"; 294 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 295 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 296 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 297 + }; 298 + 299 + pwm1_out: pwm1-out { 300 + samsung,pins = "gpd0-1"; 301 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 302 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 303 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 304 + }; 305 + 306 + lcd_ctrl: lcd-ctrl { 307 + samsung,pins = "gpd0-0", "gpd0-1"; 308 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 309 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 310 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 311 + }; 312 + 313 + i2c7_bus: i2c7-bus { 314 + samsung,pins = "gpd0-2", "gpd0-3"; 315 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 316 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 317 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 318 + }; 319 + 320 + pwm2_out: pwm2-out { 321 + samsung,pins = "gpd0-2"; 322 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 323 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 324 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 325 + }; 326 + 327 + pwm3_out: pwm3-out { 328 + samsung,pins = "gpd0-3"; 329 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 330 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 331 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 332 + }; 333 + 334 + i2c0_bus: i2c0-bus { 335 + samsung,pins = "gpd1-0", "gpd1-1"; 336 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 337 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 338 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 339 + }; 340 + 341 + mipi0_clk: mipi0-clk { 342 + samsung,pins = "gpd1-0", "gpd1-1"; 343 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 344 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 345 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 346 + }; 347 + 348 + i2c1_bus: i2c1-bus { 349 + samsung,pins = "gpd1-2", "gpd1-3"; 350 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 351 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 352 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 353 + }; 354 + 355 + mipi1_clk: mipi1-clk { 356 + samsung,pins = "gpd1-2", "gpd1-3"; 357 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 358 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 359 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 360 + }; 361 + 362 + lcd_clk: lcd-clk { 363 + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; 364 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 365 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 366 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 367 + }; 368 + 369 + lcd_data16: lcd-data-width16 { 370 + samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", 371 + "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", 372 + "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", 373 + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; 374 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 375 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 376 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 377 + }; 378 + 379 + lcd_data18: lcd-data-width18 { 380 + samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", 381 + "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", 382 + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", 383 + "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", 384 + "gpf3-2", "gpf3-3"; 385 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 386 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 387 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 388 + }; 389 + 390 + lcd_data24: lcd-data-width24 { 391 + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", 392 + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", 393 + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", 394 + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", 395 + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", 396 + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; 397 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 398 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 399 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 400 + }; 401 + 402 + lcd_ldi: lcd-ldi { 403 + samsung,pins = "gpf3-4"; 404 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 405 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 406 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 407 + }; 408 + 409 + cam_port_a_io: cam-port-a-io { 410 + samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", 411 + "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", 412 + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; 413 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 414 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 415 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 416 + }; 417 + 418 + cam_port_a_clk_active: cam-port-a-clk-active { 419 + samsung,pins = "gpj1-3"; 420 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 421 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 422 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 423 + }; 424 + 425 + cam_port_a_clk_idle: cam-port-a-clk-idle { 426 + samsung,pins = "gpj1-3"; 427 + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 428 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 429 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 430 + }; 431 + }; 432 + 433 + &pinctrl_1 { 434 + gpk0: gpk0 { 435 + gpio-controller; 436 + #gpio-cells = <2>; 437 + 438 + interrupt-controller; 439 + #interrupt-cells = <2>; 440 + }; 441 + 442 + gpk1: gpk1 { 443 + gpio-controller; 444 + #gpio-cells = <2>; 445 + 446 + interrupt-controller; 447 + #interrupt-cells = <2>; 448 + }; 449 + 450 + gpk2: gpk2 { 451 + gpio-controller; 452 + #gpio-cells = <2>; 453 + 454 + interrupt-controller; 455 + #interrupt-cells = <2>; 456 + }; 457 + 458 + gpk3: gpk3 { 459 + gpio-controller; 460 + #gpio-cells = <2>; 461 + 462 + interrupt-controller; 463 + #interrupt-cells = <2>; 464 + }; 465 + 466 + gpl0: gpl0 { 467 + gpio-controller; 468 + #gpio-cells = <2>; 469 + 470 + interrupt-controller; 471 + #interrupt-cells = <2>; 472 + }; 473 + 474 + gpl1: gpl1 { 475 + gpio-controller; 476 + #gpio-cells = <2>; 477 + 478 + interrupt-controller; 479 + #interrupt-cells = <2>; 480 + }; 481 + 482 + gpl2: gpl2 { 483 + gpio-controller; 484 + #gpio-cells = <2>; 485 + 486 + interrupt-controller; 487 + #interrupt-cells = <2>; 488 + }; 489 + 490 + gpm0: gpm0 { 491 + gpio-controller; 492 + #gpio-cells = <2>; 493 + 494 + interrupt-controller; 495 + #interrupt-cells = <2>; 496 + }; 497 + 498 + gpm1: gpm1 { 499 + gpio-controller; 500 + #gpio-cells = <2>; 501 + 502 + interrupt-controller; 503 + #interrupt-cells = <2>; 504 + }; 505 + 506 + gpm2: gpm2 { 507 + gpio-controller; 508 + #gpio-cells = <2>; 509 + 510 + interrupt-controller; 511 + #interrupt-cells = <2>; 512 + }; 513 + 514 + gpm3: gpm3 { 515 + gpio-controller; 516 + #gpio-cells = <2>; 517 + 518 + interrupt-controller; 519 + #interrupt-cells = <2>; 520 + }; 521 + 522 + gpm4: gpm4 { 523 + gpio-controller; 524 + #gpio-cells = <2>; 525 + 526 + interrupt-controller; 527 + #interrupt-cells = <2>; 528 + }; 529 + 530 + gpy0: gpy0 { 531 + gpio-controller; 532 + #gpio-cells = <2>; 533 + }; 534 + 535 + gpy1: gpy1 { 536 + gpio-controller; 537 + #gpio-cells = <2>; 538 + }; 539 + 540 + gpy2: gpy2 { 541 + gpio-controller; 542 + #gpio-cells = <2>; 543 + }; 544 + 545 + gpy3: gpy3 { 546 + gpio-controller; 547 + #gpio-cells = <2>; 548 + }; 549 + 550 + gpy4: gpy4 { 551 + gpio-controller; 552 + #gpio-cells = <2>; 553 + }; 554 + 555 + gpy5: gpy5 { 556 + gpio-controller; 557 + #gpio-cells = <2>; 558 + }; 559 + 560 + gpy6: gpy6 { 561 + gpio-controller; 562 + #gpio-cells = <2>; 563 + }; 564 + 565 + gpx0: gpx0 { 566 + gpio-controller; 567 + #gpio-cells = <2>; 568 + 569 + interrupt-controller; 570 + interrupt-parent = <&gic>; 571 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575 + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578 + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 579 + #interrupt-cells = <2>; 580 + }; 581 + 582 + gpx1: gpx1 { 583 + gpio-controller; 584 + #gpio-cells = <2>; 585 + 586 + interrupt-controller; 587 + interrupt-parent = <&gic>; 588 + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 589 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 590 + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 591 + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 592 + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 593 + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 594 + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 595 + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 596 + #interrupt-cells = <2>; 597 + }; 598 + 599 + gpx2: gpx2 { 600 + gpio-controller; 601 + #gpio-cells = <2>; 602 + 603 + interrupt-controller; 604 + #interrupt-cells = <2>; 605 + }; 606 + 607 + gpx3: gpx3 { 608 + gpio-controller; 609 + #gpio-cells = <2>; 610 + 611 + interrupt-controller; 612 + #interrupt-cells = <2>; 613 + }; 614 + 615 + sd0_clk: sd0-clk { 616 + samsung,pins = "gpk0-0"; 617 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 618 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 619 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 620 + }; 621 + 622 + sd0_cmd: sd0-cmd { 623 + samsung,pins = "gpk0-1"; 624 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 625 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 626 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 627 + }; 628 + 629 + sd0_cd: sd0-cd { 630 + samsung,pins = "gpk0-2"; 631 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 632 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 633 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 634 + }; 635 + 636 + sd0_bus1: sd0-bus-width1 { 637 + samsung,pins = "gpk0-3"; 638 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 639 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 640 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 641 + }; 642 + 643 + sd0_bus4: sd0-bus-width4 { 644 + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 645 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 646 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 647 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 648 + }; 649 + 650 + sd0_bus8: sd0-bus-width8 { 651 + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 652 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 653 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 654 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 655 + }; 656 + 657 + sd4_clk: sd4-clk { 658 + samsung,pins = "gpk0-0"; 659 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 660 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 661 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 662 + }; 663 + 664 + sd4_cmd: sd4-cmd { 665 + samsung,pins = "gpk0-1"; 666 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 667 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 668 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 669 + }; 670 + 671 + sd4_cd: sd4-cd { 672 + samsung,pins = "gpk0-2"; 673 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 674 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 675 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 676 + }; 677 + 678 + sd4_bus1: sd4-bus-width1 { 679 + samsung,pins = "gpk0-3"; 680 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 681 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 682 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 683 + }; 684 + 685 + sd4_bus4: sd4-bus-width4 { 686 + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; 687 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 688 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 689 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 690 + }; 691 + 692 + sd4_bus8: sd4-bus-width8 { 693 + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 694 + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 695 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 696 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 697 + }; 698 + 699 + sd1_clk: sd1-clk { 700 + samsung,pins = "gpk1-0"; 701 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 702 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 703 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 704 + }; 705 + 706 + sd1_cmd: sd1-cmd { 707 + samsung,pins = "gpk1-1"; 708 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 709 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 710 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 711 + }; 712 + 713 + sd1_cd: sd1-cd { 714 + samsung,pins = "gpk1-2"; 715 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 716 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 717 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 718 + }; 719 + 720 + sd1_bus1: sd1-bus-width1 { 721 + samsung,pins = "gpk1-3"; 722 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 723 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 724 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 725 + }; 726 + 727 + sd1_bus4: sd1-bus-width4 { 728 + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 729 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 730 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 731 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 732 + }; 733 + 734 + sd2_clk: sd2-clk { 735 + samsung,pins = "gpk2-0"; 736 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 737 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 738 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 739 + }; 740 + 741 + sd2_cmd: sd2-cmd { 742 + samsung,pins = "gpk2-1"; 743 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 744 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 745 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 746 + }; 747 + 748 + sd2_cd: sd2-cd { 749 + samsung,pins = "gpk2-2"; 750 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 751 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 752 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 753 + }; 754 + 755 + sd2_bus1: sd2-bus-width1 { 756 + samsung,pins = "gpk2-3"; 757 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 758 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 759 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 760 + }; 761 + 762 + sd2_bus4: sd2-bus-width4 { 763 + samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; 764 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 765 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 766 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 767 + }; 768 + 769 + sd2_bus8: sd2-bus-width8 { 770 + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 771 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 772 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 773 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 774 + }; 775 + 776 + sd3_clk: sd3-clk { 777 + samsung,pins = "gpk3-0"; 778 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 779 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 780 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 781 + }; 782 + 783 + sd3_cmd: sd3-cmd { 784 + samsung,pins = "gpk3-1"; 785 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 786 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 787 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 788 + }; 789 + 790 + sd3_cd: sd3-cd { 791 + samsung,pins = "gpk3-2"; 792 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 793 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 794 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 795 + }; 796 + 797 + sd3_bus1: sd3-bus-width1 { 798 + samsung,pins = "gpk3-3"; 799 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 800 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 801 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 802 + }; 803 + 804 + sd3_bus4: sd3-bus-width4 { 805 + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; 806 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 807 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 808 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 809 + }; 810 + 811 + cam_port_b_io: cam-port-b-io { 812 + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", 813 + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", 814 + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; 815 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 816 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 817 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 818 + }; 819 + 820 + cam_port_b_clk_active: cam-port-b-clk-active { 821 + samsung,pins = "gpm2-2"; 822 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 823 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 824 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 825 + }; 826 + 827 + cam_port_b_clk_idle: cam-port-b-clk-idle { 828 + samsung,pins = "gpm2-2"; 829 + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 830 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 831 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 832 + }; 833 + 834 + eint0: ext-int0 { 835 + samsung,pins = "gpx0-0"; 836 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 837 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 838 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 839 + }; 840 + 841 + eint8: ext-int8 { 842 + samsung,pins = "gpx1-0"; 843 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 844 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 845 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 846 + }; 847 + 848 + eint15: ext-int15 { 849 + samsung,pins = "gpx1-7"; 850 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 851 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 852 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 853 + }; 854 + 855 + eint16: ext-int16 { 856 + samsung,pins = "gpx2-0"; 857 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 858 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 859 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 860 + }; 861 + 862 + eint31: ext-int31 { 863 + samsung,pins = "gpx3-7"; 864 + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 865 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 866 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 867 + }; 868 + 869 + fimc_is_i2c0: fimc-is-i2c0 { 870 + samsung,pins = "gpm4-0", "gpm4-1"; 871 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 872 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 873 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 874 + }; 875 + 876 + fimc_is_i2c1: fimc-is-i2c1 { 877 + samsung,pins = "gpm4-2", "gpm4-3"; 878 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 879 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 880 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 881 + }; 882 + 883 + fimc_is_uart: fimc-is-uart { 884 + samsung,pins = "gpm3-5", "gpm3-7"; 885 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 886 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 887 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 888 + }; 889 + 890 + hdmi_cec: hdmi-cec { 891 + samsung,pins = "gpx3-6"; 892 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 893 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 894 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 895 + }; 896 + }; 897 + 898 + &pinctrl_2 { 899 + gpz: gpz { 900 + gpio-controller; 901 + #gpio-cells = <2>; 902 + 903 + interrupt-controller; 904 + #interrupt-cells = <2>; 905 + }; 906 + 907 + i2s0_bus: i2s0-bus { 908 + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", 909 + "gpz-4", "gpz-5", "gpz-6"; 910 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 911 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 912 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 913 + }; 914 + 915 + pcm0_bus: pcm0-bus { 916 + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", 917 + "gpz-4"; 918 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 919 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 920 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 921 + }; 922 + }; 923 + 924 + &pinctrl_3 { 925 + gpv0: gpv0 { 926 + gpio-controller; 927 + #gpio-cells = <2>; 928 + 929 + interrupt-controller; 930 + #interrupt-cells = <2>; 931 + }; 932 + 933 + gpv1: gpv1 { 934 + gpio-controller; 935 + #gpio-cells = <2>; 936 + 937 + interrupt-controller; 938 + #interrupt-cells = <2>; 939 + }; 940 + 941 + gpv2: gpv2 { 942 + gpio-controller; 943 + #gpio-cells = <2>; 944 + 945 + interrupt-controller; 946 + #interrupt-cells = <2>; 947 + }; 948 + 949 + gpv3: gpv3 { 950 + gpio-controller; 951 + #gpio-cells = <2>; 952 + 953 + interrupt-controller; 954 + #interrupt-cells = <2>; 955 + }; 956 + 957 + gpv4: gpv4 { 958 + gpio-controller; 959 + #gpio-cells = <2>; 960 + 961 + interrupt-controller; 962 + #interrupt-cells = <2>; 963 + }; 964 + 965 + c2c_bus: c2c-bus { 966 + samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", 967 + "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", 968 + "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", 969 + "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", 970 + "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", 971 + "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", 972 + "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", 973 + "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", 974 + "gpv4-0", "gpv4-1"; 975 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 976 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 977 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 980 978 }; 981 979 };
+2 -5
arch/arm/boot/dts/exynos4412-tiny4412.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * FriendlyARM's Exynos4412 based TINY4412 board device tree source 3 4 * ··· 6 5 * 7 6 * Device tree source file for FriendlyARM's TINY4412 board which is based on 8 7 * Samsung's Exynos4412 SoC. 9 - * 10 - * This program is free software; you can redistribute it and/or modify 11 - * it under the terms of the GNU General Public License version 2 as 12 - * published by the Free Software Foundation. 13 - */ 8 + */ 14 9 15 10 /dts-v1/; 16 11 #include "exynos4412.dtsi"
+1 -5
arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * Device tree sources for Exynos4412 TMU sensor configuration 3 4 * 4 5 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> 5 - * 6 - * This program is free software; you can redistribute it and/or modify 7 - * it under the terms of the GNU General Public License version 2 as 8 - * published by the Free Software Foundation. 9 - * 10 6 */ 11 7 12 8 #include <dt-bindings/thermal/thermal_exynos.h>
+4 -1392
arch/arm/boot/dts/exynos4412-trats2.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * Samsung's Exynos4412 based Trats 2 board device tree source 3 4 * ··· 7 6 * 8 7 * Device tree source file for Samsung's Trats 2 board which is based on 9 8 * Samsung's Exynos4412 SoC. 10 - * 11 - * This program is free software; you can redistribute it and/or modify 12 - * it under the terms of the GNU General Public License version 2 as 13 - * published by the Free Software Foundation. 14 - */ 9 + */ 15 10 16 11 /dts-v1/; 17 - #include "exynos4412.dtsi" 18 - #include "exynos4412-ppmu-common.dtsi" 19 - #include <dt-bindings/gpio/gpio.h> 20 - #include <dt-bindings/interrupt-controller/irq.h> 21 - #include <dt-bindings/clock/maxim,max77686.h> 22 - #include <dt-bindings/pinctrl/samsung.h> 12 + #include "exynos4412-galaxy-s3.dtsi" 23 13 24 14 / { 25 15 model = "Samsung Trats 2 based on Exynos4412"; 26 - compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; 27 - 28 - aliases { 29 - i2c9 = &i2c_ak8975; 30 - i2c10 = &i2c_cm36651; 31 - i2c11 = &i2c_max77693; 32 - i2c12 = &i2c_max77693_fuel; 33 - }; 16 + compatible = "samsung,trats2", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; 34 17 35 18 memory@40000000 { 36 19 device_type = "memory"; ··· 23 38 24 39 chosen { 25 40 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; 26 - stdout-path = &serial_2; 27 41 }; 28 - 29 - firmware@204f000 { 30 - compatible = "samsung,secure-firmware"; 31 - reg = <0x0204F000 0x1000>; 32 - }; 33 - 34 - fixed-rate-clocks { 35 - xxti { 36 - compatible = "samsung,clock-xxti", "fixed-clock"; 37 - clock-frequency = <0>; 38 - }; 39 - 40 - xusbxti { 41 - compatible = "samsung,clock-xusbxti", "fixed-clock"; 42 - clock-frequency = <24000000>; 43 - }; 44 - }; 45 - 46 - regulators { 47 - compatible = "simple-bus"; 48 - #address-cells = <1>; 49 - #size-cells = <0>; 50 - 51 - cam_io_reg: voltage-regulator-1 { 52 - compatible = "regulator-fixed"; 53 - regulator-name = "CAM_SENSOR_A"; 54 - regulator-min-microvolt = <2800000>; 55 - regulator-max-microvolt = <2800000>; 56 - gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; 57 - enable-active-high; 58 - }; 59 - 60 - lcd_vdd3_reg: voltage-regulator-2 { 61 - compatible = "regulator-fixed"; 62 - regulator-name = "LCD_VDD_2.2V"; 63 - regulator-min-microvolt = <2200000>; 64 - regulator-max-microvolt = <2200000>; 65 - gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; 66 - enable-active-high; 67 - }; 68 - 69 - cam_af_reg: voltage-regulator-3 { 70 - compatible = "regulator-fixed"; 71 - regulator-name = "CAM_AF"; 72 - regulator-min-microvolt = <2800000>; 73 - regulator-max-microvolt = <2800000>; 74 - gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; 75 - enable-active-high; 76 - }; 77 - 78 - ps_als_reg: voltage-regulator-5 { 79 - compatible = "regulator-fixed"; 80 - regulator-name = "LED_A_3.0V"; 81 - regulator-min-microvolt = <3000000>; 82 - regulator-max-microvolt = <3000000>; 83 - gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; 84 - enable-active-high; 85 - }; 86 - 87 - vsil12: voltage-regulator-6 { 88 - compatible = "regulator-fixed"; 89 - regulator-name = "VSIL_1.2V"; 90 - regulator-min-microvolt = <1200000>; 91 - regulator-max-microvolt = <1200000>; 92 - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; 93 - enable-active-high; 94 - vin-supply = <&buck7_reg>; 95 - }; 96 - 97 - vcc33mhl: voltage-regulator-7 { 98 - compatible = "regulator-fixed"; 99 - regulator-name = "VCC_3.3_MHL"; 100 - regulator-min-microvolt = <3300000>; 101 - regulator-max-microvolt = <3300000>; 102 - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; 103 - enable-active-high; 104 - }; 105 - 106 - vcc18mhl: voltage-regulator-8 { 107 - compatible = "regulator-fixed"; 108 - regulator-name = "VCC_1.8_MHL"; 109 - regulator-min-microvolt = <1800000>; 110 - regulator-max-microvolt = <1800000>; 111 - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; 112 - enable-active-high; 113 - }; 114 - }; 115 - 116 - gpio-keys { 117 - compatible = "gpio-keys"; 118 - 119 - key-down { 120 - gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; 121 - linux,code = <114>; 122 - label = "volume down"; 123 - debounce-interval = <10>; 124 - }; 125 - 126 - key-up { 127 - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; 128 - linux,code = <115>; 129 - label = "volume up"; 130 - debounce-interval = <10>; 131 - }; 132 - 133 - key-power { 134 - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; 135 - linux,code = <116>; 136 - label = "power"; 137 - debounce-interval = <10>; 138 - wakeup-source; 139 - }; 140 - 141 - key-ok { 142 - gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; 143 - linux,code = <139>; 144 - label = "ok"; 145 - debounce-inteval = <10>; 146 - wakeup-source; 147 - }; 148 - }; 149 - 150 - i2c_max77693: i2c-gpio-1 { 151 - compatible = "i2c-gpio"; 152 - gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; 153 - i2c-gpio,delay-us = <2>; 154 - #address-cells = <1>; 155 - #size-cells = <0>; 156 - status = "okay"; 157 - 158 - max77693@66 { 159 - compatible = "maxim,max77693"; 160 - interrupt-parent = <&gpx1>; 161 - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 162 - reg = <0x66>; 163 - 164 - regulators { 165 - esafeout1_reg: ESAFEOUT1 { 166 - regulator-name = "ESAFEOUT1"; 167 - }; 168 - esafeout2_reg: ESAFEOUT2 { 169 - regulator-name = "ESAFEOUT2"; 170 - }; 171 - charger_reg: CHARGER { 172 - regulator-name = "CHARGER"; 173 - regulator-min-microamp = <60000>; 174 - regulator-max-microamp = <2580000>; 175 - }; 176 - }; 177 - 178 - max77693_haptic { 179 - compatible = "maxim,max77693-haptic"; 180 - haptic-supply = <&ldo26_reg>; 181 - pwms = <&pwm 0 38022 0>; 182 - }; 183 - 184 - charger { 185 - compatible = "maxim,max77693-charger"; 186 - 187 - maxim,constant-microvolt = <4350000>; 188 - maxim,min-system-microvolt = <3600000>; 189 - maxim,thermal-regulation-celsius = <100>; 190 - maxim,battery-overcurrent-microamp = <3500000>; 191 - maxim,charge-input-threshold-microvolt = <4300000>; 192 - }; 193 - }; 194 - }; 195 - 196 - i2c_max77693_fuel: i2c-gpio-3 { 197 - compatible = "i2c-gpio"; 198 - gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>; 199 - i2c-gpio,delay-us = <2>; 200 - #address-cells = <1>; 201 - #size-cells = <0>; 202 - status = "okay"; 203 - 204 - max77693-fuel-gauge@36 { 205 - compatible = "maxim,max17047"; 206 - interrupt-parent = <&gpx2>; 207 - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 208 - reg = <0x36>; 209 - 210 - maxim,over-heat-temp = <700>; 211 - maxim,over-volt = <4500>; 212 - }; 213 - }; 214 - 215 - i2c_ak8975: i2c-gpio-0 { 216 - compatible = "i2c-gpio"; 217 - gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; 218 - i2c-gpio,delay-us = <2>; 219 - #address-cells = <1>; 220 - #size-cells = <0>; 221 - status = "okay"; 222 - 223 - ak8975@c { 224 - compatible = "asahi-kasei,ak8975"; 225 - reg = <0x0c>; 226 - gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; 227 - }; 228 - }; 229 - 230 - i2c_cm36651: i2c-gpio-2 { 231 - compatible = "i2c-gpio"; 232 - gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; 233 - i2c-gpio,delay-us = <2>; 234 - #address-cells = <1>; 235 - #size-cells = <0>; 236 - 237 - cm36651@18 { 238 - compatible = "capella,cm36651"; 239 - reg = <0x18>; 240 - interrupt-parent = <&gpx0>; 241 - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 242 - vled-supply = <&ps_als_reg>; 243 - }; 244 - }; 245 - 246 - i2c-mhl { 247 - compatible = "i2c-gpio"; 248 - gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; 249 - i2c-gpio,delay-us = <100>; 250 - #address-cells = <1>; 251 - #size-cells = <0>; 252 - 253 - pinctrl-0 = <&i2c_mhl_bus>; 254 - pinctrl-names = "default"; 255 - status = "okay"; 256 - 257 - sii9234: hdmi-bridge@39 { 258 - compatible = "sil,sii9234"; 259 - avcc33-supply = <&vcc33mhl>; 260 - iovcc18-supply = <&vcc18mhl>; 261 - avcc12-supply = <&vsil12>; 262 - cvcc12-supply = <&vsil12>; 263 - reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; 264 - interrupt-parent = <&gpf3>; 265 - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 266 - reg = <0x39>; 267 - 268 - port { 269 - mhl_to_hdmi: endpoint { 270 - remote-endpoint = <&hdmi_to_mhl>; 271 - }; 272 - }; 273 - }; 274 - }; 275 - 276 - camera: camera { 277 - pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; 278 - pinctrl-names = "default"; 279 - status = "okay"; 280 - assigned-clocks = <&clock CLK_MOUT_CAM0>, 281 - <&clock CLK_MOUT_CAM1>; 282 - assigned-clock-parents = <&clock CLK_XUSBXTI>, 283 - <&clock CLK_XUSBXTI>; 284 - 285 - 286 - }; 287 - 288 - wlan_pwrseq: sdhci3-pwrseq { 289 - compatible = "mmc-pwrseq-simple"; 290 - reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>; 291 - clocks = <&max77686 MAX77686_CLK_PMIC>; 292 - clock-names = "ext_clock"; 293 - }; 294 - 295 - sound { 296 - compatible = "samsung,trats2-audio"; 297 - samsung,i2s-controller = <&i2s0>; 298 - samsung,model = "Trats2"; 299 - samsung,audio-codec = <&wm1811>; 300 - samsung,audio-routing = 301 - "SPK", "SPKOUTLN", 302 - "SPK", "SPKOUTLP", 303 - "SPK", "SPKOUTRN", 304 - "SPK", "SPKOUTRP"; 305 - }; 306 - 307 - thermistor-ap { 308 - compatible = "murata,ncp15wb473"; 309 - pullup-uv = <1800000>; /* VCC_1.8V_AP */ 310 - pullup-ohm = <100000>; /* 100K */ 311 - pulldown-ohm = <100000>; /* 100K */ 312 - io-channels = <&adc 1>; /* AP temperature */ 313 - }; 314 - 315 - thermistor-battery { 316 - compatible = "murata,ncp15wb473"; 317 - pullup-uv = <1800000>; /* VCC_1.8V_AP */ 318 - pullup-ohm = <100000>; /* 100K */ 319 - pulldown-ohm = <100000>; /* 100K */ 320 - io-channels = <&adc 2>; /* Battery temperature */ 321 - }; 322 - 323 - thermal-zones { 324 - cpu_thermal: cpu-thermal { 325 - cooling-maps { 326 - map0 { 327 - /* Corresponds to 800MHz at freq_table */ 328 - cooling-device = <&cpu0 7 7>; 329 - }; 330 - map1 { 331 - /* Corresponds to 200MHz at freq_table */ 332 - cooling-device = <&cpu0 13 13>; 333 - }; 334 - }; 335 - }; 336 - }; 337 - }; 338 - 339 - &adc { 340 - vdd-supply = <&ldo3_reg>; 341 - status = "okay"; 342 - }; 343 - 344 - &bus_dmc { 345 - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; 346 - vdd-supply = <&buck1_reg>; 347 - status = "okay"; 348 - }; 349 - 350 - &bus_acp { 351 - devfreq = <&bus_dmc>; 352 - status = "okay"; 353 - }; 354 - 355 - &bus_c2c { 356 - devfreq = <&bus_dmc>; 357 - status = "okay"; 358 - }; 359 - 360 - &bus_leftbus { 361 - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; 362 - vdd-supply = <&buck3_reg>; 363 - status = "okay"; 364 - }; 365 - 366 - &bus_rightbus { 367 - devfreq = <&bus_leftbus>; 368 - status = "okay"; 369 - }; 370 - 371 - &bus_display { 372 - devfreq = <&bus_leftbus>; 373 - status = "okay"; 374 - }; 375 - 376 - &bus_fsys { 377 - devfreq = <&bus_leftbus>; 378 - status = "okay"; 379 - }; 380 - 381 - &bus_peri { 382 - devfreq = <&bus_leftbus>; 383 - status = "okay"; 384 - }; 385 - 386 - &bus_mfc { 387 - devfreq = <&bus_leftbus>; 388 - status = "okay"; 389 - }; 390 - 391 - &cpu0 { 392 - cpu0-supply = <&buck2_reg>; 393 - }; 394 - 395 - &csis_0 { 396 - status = "okay"; 397 - vddcore-supply = <&ldo8_reg>; 398 - vddio-supply = <&ldo10_reg>; 399 - assigned-clocks = <&clock CLK_MOUT_CSIS0>, 400 - <&clock CLK_SCLK_CSIS0>; 401 - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 402 - assigned-clock-rates = <0>, <176000000>; 403 - 404 - /* Camera C (3) MIPI CSI-2 (CSIS0) */ 405 - port@3 { 406 - reg = <3>; 407 - csis0_ep: endpoint { 408 - remote-endpoint = <&s5c73m3_ep>; 409 - data-lanes = <1 2 3 4>; 410 - samsung,csis-hs-settle = <12>; 411 - }; 412 - }; 413 - }; 414 - 415 - &csis_1 { 416 - status = "okay"; 417 - vddcore-supply = <&ldo8_reg>; 418 - vddio-supply = <&ldo10_reg>; 419 - assigned-clocks = <&clock CLK_MOUT_CSIS1>, 420 - <&clock CLK_SCLK_CSIS1>; 421 - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 422 - assigned-clock-rates = <0>, <176000000>; 423 - 424 - /* Camera D (4) MIPI CSI-2 (CSIS1) */ 425 - port@4 { 426 - reg = <4>; 427 - csis1_ep: endpoint { 428 - remote-endpoint = <&is_s5k6a3_ep>; 429 - data-lanes = <1>; 430 - samsung,csis-hs-settle = <18>; 431 - samsung,csis-wclk; 432 - }; 433 - }; 434 - }; 435 - 436 - &dsi_0 { 437 - vddcore-supply = <&ldo8_reg>; 438 - vddio-supply = <&ldo10_reg>; 439 - samsung,burst-clock-frequency = <500000000>; 440 - samsung,esc-clock-frequency = <20000000>; 441 - samsung,pll-clock-frequency = <24000000>; 442 - status = "okay"; 443 - 444 - panel@0 { 445 - compatible = "samsung,s6e8aa0"; 446 - reg = <0>; 447 - vdd3-supply = <&lcd_vdd3_reg>; 448 - vci-supply = <&ldo25_reg>; 449 - reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; 450 - power-on-delay= <50>; 451 - reset-delay = <100>; 452 - init-delay = <100>; 453 - flip-horizontal; 454 - flip-vertical; 455 - panel-width-mm = <58>; 456 - panel-height-mm = <103>; 457 - 458 - display-timings { 459 - timing-0 { 460 - clock-frequency = <57153600>; 461 - hactive = <720>; 462 - vactive = <1280>; 463 - hfront-porch = <5>; 464 - hback-porch = <5>; 465 - hsync-len = <5>; 466 - vfront-porch = <13>; 467 - vback-porch = <1>; 468 - vsync-len = <2>; 469 - }; 470 - }; 471 - }; 472 - }; 473 - 474 - &exynos_usbphy { 475 - vbus-supply = <&esafeout1_reg>; 476 - status = "okay"; 477 - }; 478 - 479 - &fimc_0 { 480 - status = "okay"; 481 - assigned-clocks = <&clock CLK_MOUT_FIMC0>, 482 - <&clock CLK_SCLK_FIMC0>; 483 - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 484 - assigned-clock-rates = <0>, <176000000>; 485 - }; 486 - 487 - &fimc_1 { 488 - status = "okay"; 489 - assigned-clocks = <&clock CLK_MOUT_FIMC1>, 490 - <&clock CLK_SCLK_FIMC1>; 491 - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 492 - assigned-clock-rates = <0>, <176000000>; 493 - }; 494 - 495 - &fimc_2 { 496 - status = "okay"; 497 - assigned-clocks = <&clock CLK_MOUT_FIMC2>, 498 - <&clock CLK_SCLK_FIMC2>; 499 - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 500 - assigned-clock-rates = <0>, <176000000>; 501 - }; 502 - 503 - &fimc_3 { 504 - status = "okay"; 505 - assigned-clocks = <&clock CLK_MOUT_FIMC3>, 506 - <&clock CLK_SCLK_FIMC3>; 507 - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 508 - assigned-clock-rates = <0>, <176000000>; 509 - }; 510 - 511 - &fimc_is { 512 - pinctrl-0 = <&fimc_is_uart>; 513 - pinctrl-names = "default"; 514 - status = "okay"; 515 - 516 - i2c1_isp: i2c-isp@12140000 { 517 - pinctrl-0 = <&fimc_is_i2c1>; 518 - pinctrl-names = "default"; 519 - 520 - s5k6a3@10 { 521 - compatible = "samsung,s5k6a3"; 522 - reg = <0x10>; 523 - svdda-supply = <&cam_io_reg>; 524 - svddio-supply = <&ldo19_reg>; 525 - afvdd-supply = <&ldo19_reg>; 526 - clock-frequency = <24000000>; 527 - /* CAM_B_CLKOUT */ 528 - clocks = <&camera 1>; 529 - clock-names = "extclk"; 530 - samsung,camclk-out = <1>; 531 - gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; 532 - 533 - port { 534 - is_s5k6a3_ep: endpoint { 535 - remote-endpoint = <&csis1_ep>; 536 - data-lanes = <1>; 537 - }; 538 - }; 539 - }; 540 - }; 541 - }; 542 - 543 - &fimc_lite_0 { 544 - status = "okay"; 545 - }; 546 - 547 - &fimc_lite_1 { 548 - status = "okay"; 549 - }; 550 - 551 - &fimd { 552 - status = "okay"; 553 - }; 554 - 555 - &hdmi { 556 - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; 557 - pinctrl-names = "default"; 558 - pinctrl-0 = <&hdmi_hpd>; 559 - vdd-supply = <&ldo3_reg>; 560 - vdd_osc-supply = <&ldo4_reg>; 561 - vdd_pll-supply = <&ldo3_reg>; 562 - ddc = <&i2c_5>; 563 - status = "okay"; 564 - 565 - ports { 566 - #address-cells = <1>; 567 - #size-cells = <0>; 568 - 569 - port@1 { 570 - reg = <1>; 571 - hdmi_to_mhl: endpoint { 572 - remote-endpoint = <&mhl_to_hdmi>; 573 - }; 574 - }; 575 - }; 576 - }; 577 - 578 - &hsotg { 579 - vusb_d-supply = <&ldo15_reg>; 580 - vusb_a-supply = <&ldo12_reg>; 581 - dr_mode = "peripheral"; 582 - status = "okay"; 583 - }; 584 - 585 - &i2c_0 { 586 - samsung,i2c-sda-delay = <100>; 587 - samsung,i2c-slave-addr = <0x10>; 588 - samsung,i2c-max-bus-freq = <400000>; 589 - pinctrl-0 = <&i2c0_bus>; 590 - pinctrl-names = "default"; 591 - status = "okay"; 592 - 593 - s5c73m3@3c { 594 - compatible = "samsung,s5c73m3"; 595 - reg = <0x3c>; 596 - standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ 597 - xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ 598 - vdd-int-supply = <&buck9_reg>; 599 - vddio-cis-supply = <&ldo9_reg>; 600 - vdda-supply = <&ldo17_reg>; 601 - vddio-host-supply = <&ldo18_reg>; 602 - vdd-af-supply = <&cam_af_reg>; 603 - vdd-reg-supply = <&cam_io_reg>; 604 - clock-frequency = <24000000>; 605 - /* CAM_A_CLKOUT */ 606 - clocks = <&camera 0>; 607 - clock-names = "cis_extclk"; 608 - port { 609 - s5c73m3_ep: endpoint { 610 - remote-endpoint = <&csis0_ep>; 611 - data-lanes = <1 2 3 4>; 612 - }; 613 - }; 614 - }; 615 - }; 616 - 617 - &i2c_3 { 618 - samsung,i2c-sda-delay = <100>; 619 - samsung,i2c-slave-addr = <0x10>; 620 - samsung,i2c-max-bus-freq = <400000>; 621 - pinctrl-0 = <&i2c3_bus>; 622 - pinctrl-names = "default"; 623 - status = "okay"; 624 - 625 - mms114-touchscreen@48 { 626 - compatible = "melfas,mms114"; 627 - reg = <0x48>; 628 - interrupt-parent = <&gpm2>; 629 - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 630 - x-size = <720>; 631 - y-size = <1280>; 632 - avdd-supply = <&ldo23_reg>; 633 - vdd-supply = <&ldo24_reg>; 634 - }; 635 - }; 636 - 637 - &i2c_4 { 638 - samsung,i2c-sda-delay = <100>; 639 - samsung,i2c-slave-addr = <0x10>; 640 - samsung,i2c-max-bus-freq = <100000>; 641 - pinctrl-0 = <&i2c4_bus>; 642 - pinctrl-names = "default"; 643 - status = "okay"; 644 - 645 - wm1811: wm1811@1a { 646 - compatible = "wlf,wm1811"; 647 - reg = <0x1a>; 648 - clocks = <&pmu_system_controller 0>; 649 - clock-names = "MCLK1"; 650 - DCVDD-supply = <&ldo3_reg>; 651 - DBVDD1-supply = <&ldo3_reg>; 652 - wlf,ldo1ena = <&gpj0 4 0>; 653 - }; 654 - }; 655 - 656 - &i2c_5 { 657 - status = "okay"; 658 - }; 659 - 660 - &i2c_7 { 661 - samsung,i2c-sda-delay = <100>; 662 - samsung,i2c-slave-addr = <0x10>; 663 - samsung,i2c-max-bus-freq = <100000>; 664 - pinctrl-0 = <&i2c7_bus>; 665 - pinctrl-names = "default"; 666 - status = "okay"; 667 - 668 - max77686: max77686_pmic@9 { 669 - compatible = "maxim,max77686"; 670 - interrupt-parent = <&gpx0>; 671 - interrupts = <7 IRQ_TYPE_NONE>; 672 - reg = <0x09>; 673 - #clock-cells = <1>; 674 - 675 - voltage-regulators { 676 - ldo1_reg: LDO1 { 677 - regulator-name = "VALIVE_1.0V_AP"; 678 - regulator-min-microvolt = <1000000>; 679 - regulator-max-microvolt = <1000000>; 680 - regulator-always-on; 681 - }; 682 - 683 - ldo2_reg: LDO2 { 684 - regulator-name = "VM1M2_1.2V_AP"; 685 - regulator-min-microvolt = <1200000>; 686 - regulator-max-microvolt = <1200000>; 687 - regulator-always-on; 688 - regulator-state-mem { 689 - regulator-on-in-suspend; 690 - }; 691 - }; 692 - 693 - ldo3_reg: LDO3 { 694 - regulator-name = "VCC_1.8V_AP"; 695 - regulator-min-microvolt = <1800000>; 696 - regulator-max-microvolt = <1800000>; 697 - regulator-always-on; 698 - }; 699 - 700 - ldo4_reg: LDO4 { 701 - regulator-name = "VCC_2.8V_AP"; 702 - regulator-min-microvolt = <2800000>; 703 - regulator-max-microvolt = <2800000>; 704 - regulator-always-on; 705 - }; 706 - 707 - ldo5_reg: LDO5 { 708 - regulator-name = "VCC_1.8V_IO"; 709 - regulator-min-microvolt = <1800000>; 710 - regulator-max-microvolt = <1800000>; 711 - regulator-always-on; 712 - }; 713 - 714 - ldo6_reg: LDO6 { 715 - regulator-name = "VMPLL_1.0V_AP"; 716 - regulator-min-microvolt = <1000000>; 717 - regulator-max-microvolt = <1000000>; 718 - regulator-always-on; 719 - regulator-state-mem { 720 - regulator-on-in-suspend; 721 - }; 722 - }; 723 - 724 - ldo7_reg: LDO7 { 725 - regulator-name = "VPLL_1.0V_AP"; 726 - regulator-min-microvolt = <1000000>; 727 - regulator-max-microvolt = <1000000>; 728 - regulator-always-on; 729 - regulator-state-mem { 730 - regulator-on-in-suspend; 731 - }; 732 - }; 733 - 734 - ldo8_reg: LDO8 { 735 - regulator-name = "VMIPI_1.0V"; 736 - regulator-min-microvolt = <1000000>; 737 - regulator-max-microvolt = <1000000>; 738 - regulator-state-mem { 739 - regulator-off-in-suspend; 740 - }; 741 - }; 742 - 743 - ldo9_reg: LDO9 { 744 - regulator-name = "CAM_ISP_MIPI_1.2V"; 745 - regulator-min-microvolt = <1200000>; 746 - regulator-max-microvolt = <1200000>; 747 - }; 748 - 749 - ldo10_reg: LDO10 { 750 - regulator-name = "VMIPI_1.8V"; 751 - regulator-min-microvolt = <1800000>; 752 - regulator-max-microvolt = <1800000>; 753 - regulator-state-mem { 754 - regulator-off-in-suspend; 755 - }; 756 - }; 757 - 758 - ldo11_reg: LDO11 { 759 - regulator-name = "VABB1_1.95V"; 760 - regulator-min-microvolt = <1950000>; 761 - regulator-max-microvolt = <1950000>; 762 - regulator-always-on; 763 - regulator-state-mem { 764 - regulator-off-in-suspend; 765 - }; 766 - }; 767 - 768 - ldo12_reg: LDO12 { 769 - regulator-name = "VUOTG_3.0V"; 770 - regulator-min-microvolt = <3000000>; 771 - regulator-max-microvolt = <3000000>; 772 - regulator-state-mem { 773 - regulator-off-in-suspend; 774 - }; 775 - }; 776 - 777 - ldo13_reg: LDO13 { 778 - regulator-name = "NFC_AVDD_1.8V"; 779 - regulator-min-microvolt = <1800000>; 780 - regulator-max-microvolt = <1800000>; 781 - }; 782 - 783 - ldo14_reg: LDO14 { 784 - regulator-name = "VABB2_1.95V"; 785 - regulator-min-microvolt = <1950000>; 786 - regulator-max-microvolt = <1950000>; 787 - regulator-always-on; 788 - regulator-state-mem { 789 - regulator-off-in-suspend; 790 - }; 791 - }; 792 - 793 - ldo15_reg: LDO15 { 794 - regulator-name = "VHSIC_1.0V"; 795 - regulator-min-microvolt = <1000000>; 796 - regulator-max-microvolt = <1000000>; 797 - regulator-state-mem { 798 - regulator-on-in-suspend; 799 - }; 800 - }; 801 - 802 - ldo16_reg: LDO16 { 803 - regulator-name = "VHSIC_1.8V"; 804 - regulator-min-microvolt = <1800000>; 805 - regulator-max-microvolt = <1800000>; 806 - regulator-state-mem { 807 - regulator-on-in-suspend; 808 - }; 809 - }; 810 - 811 - ldo17_reg: LDO17 { 812 - regulator-name = "CAM_SENSOR_CORE_1.2V"; 813 - regulator-min-microvolt = <1200000>; 814 - regulator-max-microvolt = <1200000>; 815 - }; 816 - 817 - ldo18_reg: LDO18 { 818 - regulator-name = "CAM_ISP_SEN_IO_1.8V"; 819 - regulator-min-microvolt = <1800000>; 820 - regulator-max-microvolt = <1800000>; 821 - }; 822 - 823 - ldo19_reg: LDO19 { 824 - regulator-name = "VT_CAM_1.8V"; 825 - regulator-min-microvolt = <1800000>; 826 - regulator-max-microvolt = <1800000>; 827 - }; 828 - 829 - ldo20_reg: LDO20 { 830 - regulator-name = "VDDQ_PRE_1.8V"; 831 - regulator-min-microvolt = <1800000>; 832 - regulator-max-microvolt = <1800000>; 833 - }; 834 - 835 - ldo21_reg: LDO21 { 836 - regulator-name = "VTF_2.8V"; 837 - regulator-min-microvolt = <2800000>; 838 - regulator-max-microvolt = <2800000>; 839 - maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; 840 - }; 841 - 842 - ldo22_reg: LDO22 { 843 - regulator-name = "VMEM_VDD_2.8V"; 844 - regulator-min-microvolt = <2800000>; 845 - regulator-max-microvolt = <2800000>; 846 - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; 847 - }; 848 - 849 - ldo23_reg: LDO23 { 850 - regulator-name = "TSP_AVDD_3.3V"; 851 - regulator-min-microvolt = <3300000>; 852 - regulator-max-microvolt = <3300000>; 853 - }; 854 - 855 - ldo24_reg: LDO24 { 856 - regulator-name = "TSP_VDD_1.8V"; 857 - regulator-min-microvolt = <1800000>; 858 - regulator-max-microvolt = <1800000>; 859 - }; 860 - 861 - ldo25_reg: LDO25 { 862 - regulator-name = "LCD_VCC_3.3V"; 863 - regulator-min-microvolt = <2800000>; 864 - regulator-max-microvolt = <2800000>; 865 - }; 866 - 867 - ldo26_reg: LDO26 { 868 - regulator-name = "MOTOR_VCC_3.0V"; 869 - regulator-min-microvolt = <3000000>; 870 - regulator-max-microvolt = <3000000>; 871 - }; 872 - 873 - buck1_reg: BUCK1 { 874 - regulator-name = "vdd_mif"; 875 - regulator-min-microvolt = <850000>; 876 - regulator-max-microvolt = <1100000>; 877 - regulator-always-on; 878 - regulator-boot-on; 879 - regulator-state-mem { 880 - regulator-off-in-suspend; 881 - }; 882 - }; 883 - 884 - buck2_reg: BUCK2 { 885 - regulator-name = "vdd_arm"; 886 - regulator-min-microvolt = <850000>; 887 - regulator-max-microvolt = <1500000>; 888 - regulator-always-on; 889 - regulator-boot-on; 890 - regulator-state-mem { 891 - regulator-on-in-suspend; 892 - }; 893 - }; 894 - 895 - buck3_reg: BUCK3 { 896 - regulator-name = "vdd_int"; 897 - regulator-min-microvolt = <850000>; 898 - regulator-max-microvolt = <1150000>; 899 - regulator-always-on; 900 - regulator-boot-on; 901 - regulator-state-mem { 902 - regulator-off-in-suspend; 903 - }; 904 - }; 905 - 906 - buck4_reg: BUCK4 { 907 - regulator-name = "vdd_g3d"; 908 - regulator-min-microvolt = <850000>; 909 - regulator-max-microvolt = <1150000>; 910 - regulator-boot-on; 911 - regulator-state-mem { 912 - regulator-off-in-suspend; 913 - }; 914 - }; 915 - 916 - buck5_reg: BUCK5 { 917 - regulator-name = "VMEM_1.2V_AP"; 918 - regulator-min-microvolt = <1200000>; 919 - regulator-max-microvolt = <1200000>; 920 - regulator-always-on; 921 - }; 922 - 923 - buck6_reg: BUCK6 { 924 - regulator-name = "VCC_SUB_1.35V"; 925 - regulator-min-microvolt = <1350000>; 926 - regulator-max-microvolt = <1350000>; 927 - regulator-always-on; 928 - }; 929 - 930 - buck7_reg: BUCK7 { 931 - regulator-name = "VCC_SUB_2.0V"; 932 - regulator-min-microvolt = <2000000>; 933 - regulator-max-microvolt = <2000000>; 934 - regulator-always-on; 935 - }; 936 - 937 - buck8_reg: BUCK8 { 938 - regulator-name = "VMEM_VDDF_3.0V"; 939 - regulator-min-microvolt = <2850000>; 940 - regulator-max-microvolt = <2850000>; 941 - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; 942 - }; 943 - 944 - buck9_reg: BUCK9 { 945 - regulator-name = "CAM_ISP_CORE_1.2V"; 946 - regulator-min-microvolt = <1000000>; 947 - regulator-max-microvolt = <1200000>; 948 - maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; 949 - }; 950 - }; 951 - }; 952 - }; 953 - 954 - &i2c_8 { 955 - status = "okay"; 956 - }; 957 - 958 - &i2s0 { 959 - pinctrl-0 = <&i2s0_bus>; 960 - pinctrl-names = "default"; 961 - status = "okay"; 962 - }; 963 - 964 - &mixer { 965 - status = "okay"; 966 - }; 967 - 968 - &mshc_0 { 969 - broken-cd; 970 - non-removable; 971 - card-detect-delay = <200>; 972 - vmmc-supply = <&ldo22_reg>; 973 - clock-frequency = <400000000>; 974 - samsung,dw-mshc-ciu-div = <0>; 975 - samsung,dw-mshc-sdr-timing = <2 3>; 976 - samsung,dw-mshc-ddr-timing = <1 2>; 977 - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 978 - pinctrl-names = "default"; 979 - status = "okay"; 980 - bus-width = <8>; 981 - cap-mmc-highspeed; 982 - }; 983 - 984 - &pmu_system_controller { 985 - assigned-clocks = <&pmu_system_controller 0>; 986 - assigned-clock-parents = <&clock CLK_XUSBXTI>; 987 - }; 988 - 989 - &pinctrl_0 { 990 - pinctrl-names = "default"; 991 - pinctrl-0 = <&sleep0>; 992 - 993 - mhl_int: mhl-int { 994 - samsung,pins = "gpf3-5"; 995 - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 996 - }; 997 - 998 - i2c_mhl_bus: i2c-mhl-bus { 999 - samsung,pins = "gpf0-4", "gpf0-6"; 1000 - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 1001 - samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 1002 - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 1003 - }; 1004 - 1005 - sleep0: sleep-states { 1006 - PIN_SLP(gpa0-0, INPUT, NONE); 1007 - PIN_SLP(gpa0-1, OUT0, NONE); 1008 - PIN_SLP(gpa0-2, INPUT, NONE); 1009 - PIN_SLP(gpa0-3, INPUT, UP); 1010 - PIN_SLP(gpa0-4, INPUT, NONE); 1011 - PIN_SLP(gpa0-5, INPUT, DOWN); 1012 - PIN_SLP(gpa0-6, INPUT, DOWN); 1013 - PIN_SLP(gpa0-7, INPUT, UP); 1014 - 1015 - PIN_SLP(gpa1-0, INPUT, DOWN); 1016 - PIN_SLP(gpa1-1, INPUT, DOWN); 1017 - PIN_SLP(gpa1-2, INPUT, DOWN); 1018 - PIN_SLP(gpa1-3, INPUT, DOWN); 1019 - PIN_SLP(gpa1-4, INPUT, DOWN); 1020 - PIN_SLP(gpa1-5, INPUT, DOWN); 1021 - 1022 - PIN_SLP(gpb-0, INPUT, NONE); 1023 - PIN_SLP(gpb-1, INPUT, NONE); 1024 - PIN_SLP(gpb-2, INPUT, NONE); 1025 - PIN_SLP(gpb-3, INPUT, NONE); 1026 - PIN_SLP(gpb-4, INPUT, DOWN); 1027 - PIN_SLP(gpb-5, INPUT, UP); 1028 - PIN_SLP(gpb-6, INPUT, DOWN); 1029 - PIN_SLP(gpb-7, INPUT, DOWN); 1030 - 1031 - PIN_SLP(gpc0-0, INPUT, DOWN); 1032 - PIN_SLP(gpc0-1, INPUT, DOWN); 1033 - PIN_SLP(gpc0-2, INPUT, DOWN); 1034 - PIN_SLP(gpc0-3, INPUT, DOWN); 1035 - PIN_SLP(gpc0-4, INPUT, DOWN); 1036 - 1037 - PIN_SLP(gpc1-0, INPUT, NONE); 1038 - PIN_SLP(gpc1-1, PREV, NONE); 1039 - PIN_SLP(gpc1-2, INPUT, NONE); 1040 - PIN_SLP(gpc1-3, INPUT, NONE); 1041 - PIN_SLP(gpc1-4, INPUT, NONE); 1042 - 1043 - PIN_SLP(gpd0-0, INPUT, DOWN); 1044 - PIN_SLP(gpd0-1, INPUT, DOWN); 1045 - PIN_SLP(gpd0-2, INPUT, NONE); 1046 - PIN_SLP(gpd0-3, INPUT, NONE); 1047 - 1048 - PIN_SLP(gpd1-0, INPUT, DOWN); 1049 - PIN_SLP(gpd1-1, INPUT, DOWN); 1050 - PIN_SLP(gpd1-2, INPUT, NONE); 1051 - PIN_SLP(gpd1-3, INPUT, NONE); 1052 - 1053 - PIN_SLP(gpf0-0, INPUT, NONE); 1054 - PIN_SLP(gpf0-1, INPUT, NONE); 1055 - PIN_SLP(gpf0-2, INPUT, DOWN); 1056 - PIN_SLP(gpf0-3, INPUT, DOWN); 1057 - PIN_SLP(gpf0-4, INPUT, NONE); 1058 - PIN_SLP(gpf0-5, INPUT, DOWN); 1059 - PIN_SLP(gpf0-6, INPUT, NONE); 1060 - PIN_SLP(gpf0-7, INPUT, DOWN); 1061 - 1062 - PIN_SLP(gpf1-0, INPUT, DOWN); 1063 - PIN_SLP(gpf1-1, INPUT, DOWN); 1064 - PIN_SLP(gpf1-2, INPUT, DOWN); 1065 - PIN_SLP(gpf1-3, INPUT, DOWN); 1066 - PIN_SLP(gpf1-4, INPUT, NONE); 1067 - PIN_SLP(gpf1-5, INPUT, NONE); 1068 - PIN_SLP(gpf1-6, INPUT, DOWN); 1069 - PIN_SLP(gpf1-7, PREV, NONE); 1070 - 1071 - PIN_SLP(gpf2-0, PREV, NONE); 1072 - PIN_SLP(gpf2-1, INPUT, DOWN); 1073 - PIN_SLP(gpf2-2, INPUT, DOWN); 1074 - PIN_SLP(gpf2-3, INPUT, DOWN); 1075 - PIN_SLP(gpf2-4, INPUT, DOWN); 1076 - PIN_SLP(gpf2-5, INPUT, DOWN); 1077 - PIN_SLP(gpf2-6, INPUT, NONE); 1078 - PIN_SLP(gpf2-7, INPUT, NONE); 1079 - 1080 - PIN_SLP(gpf3-0, INPUT, NONE); 1081 - PIN_SLP(gpf3-1, PREV, NONE); 1082 - PIN_SLP(gpf3-2, PREV, NONE); 1083 - PIN_SLP(gpf3-3, PREV, NONE); 1084 - PIN_SLP(gpf3-4, OUT1, NONE); 1085 - PIN_SLP(gpf3-5, INPUT, DOWN); 1086 - 1087 - PIN_SLP(gpj0-0, PREV, NONE); 1088 - PIN_SLP(gpj0-1, PREV, NONE); 1089 - PIN_SLP(gpj0-2, PREV, NONE); 1090 - PIN_SLP(gpj0-3, INPUT, DOWN); 1091 - PIN_SLP(gpj0-4, PREV, NONE); 1092 - PIN_SLP(gpj0-5, PREV, NONE); 1093 - PIN_SLP(gpj0-6, INPUT, DOWN); 1094 - PIN_SLP(gpj0-7, INPUT, DOWN); 1095 - 1096 - PIN_SLP(gpj1-0, INPUT, DOWN); 1097 - PIN_SLP(gpj1-1, PREV, NONE); 1098 - PIN_SLP(gpj1-2, PREV, NONE); 1099 - PIN_SLP(gpj1-3, INPUT, DOWN); 1100 - PIN_SLP(gpj1-4, INPUT, DOWN); 1101 - }; 1102 - }; 1103 - 1104 - &pinctrl_1 { 1105 - pinctrl-names = "default"; 1106 - pinctrl-0 = <&sleep1>; 1107 - 1108 - hdmi_hpd: hdmi-hpd { 1109 - samsung,pins = "gpx3-7"; 1110 - samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 1111 - }; 1112 - 1113 - sleep1: sleep-states { 1114 - PIN_SLP(gpk0-0, PREV, NONE); 1115 - PIN_SLP(gpk0-1, PREV, NONE); 1116 - PIN_SLP(gpk0-2, OUT0, NONE); 1117 - PIN_SLP(gpk0-3, PREV, NONE); 1118 - PIN_SLP(gpk0-4, PREV, NONE); 1119 - PIN_SLP(gpk0-5, PREV, NONE); 1120 - PIN_SLP(gpk0-6, PREV, NONE); 1121 - 1122 - PIN_SLP(gpk1-0, INPUT, DOWN); 1123 - PIN_SLP(gpk1-1, INPUT, DOWN); 1124 - PIN_SLP(gpk1-2, INPUT, DOWN); 1125 - PIN_SLP(gpk1-3, PREV, NONE); 1126 - PIN_SLP(gpk1-4, PREV, NONE); 1127 - PIN_SLP(gpk1-5, PREV, NONE); 1128 - PIN_SLP(gpk1-6, PREV, NONE); 1129 - 1130 - PIN_SLP(gpk2-0, INPUT, DOWN); 1131 - PIN_SLP(gpk2-1, INPUT, DOWN); 1132 - PIN_SLP(gpk2-2, INPUT, DOWN); 1133 - PIN_SLP(gpk2-3, INPUT, DOWN); 1134 - PIN_SLP(gpk2-4, INPUT, DOWN); 1135 - PIN_SLP(gpk2-5, INPUT, DOWN); 1136 - PIN_SLP(gpk2-6, INPUT, DOWN); 1137 - 1138 - PIN_SLP(gpk3-0, OUT0, NONE); 1139 - PIN_SLP(gpk3-1, INPUT, NONE); 1140 - PIN_SLP(gpk3-2, INPUT, DOWN); 1141 - PIN_SLP(gpk3-3, INPUT, NONE); 1142 - PIN_SLP(gpk3-4, INPUT, NONE); 1143 - PIN_SLP(gpk3-5, INPUT, NONE); 1144 - PIN_SLP(gpk3-6, INPUT, NONE); 1145 - 1146 - PIN_SLP(gpl0-0, INPUT, DOWN); 1147 - PIN_SLP(gpl0-1, INPUT, DOWN); 1148 - PIN_SLP(gpl0-2, INPUT, DOWN); 1149 - PIN_SLP(gpl0-3, INPUT, DOWN); 1150 - PIN_SLP(gpl0-4, PREV, NONE); 1151 - PIN_SLP(gpl0-6, PREV, NONE); 1152 - 1153 - PIN_SLP(gpl1-0, INPUT, DOWN); 1154 - PIN_SLP(gpl1-1, INPUT, DOWN); 1155 - PIN_SLP(gpl2-0, INPUT, DOWN); 1156 - PIN_SLP(gpl2-1, INPUT, DOWN); 1157 - PIN_SLP(gpl2-2, INPUT, DOWN); 1158 - PIN_SLP(gpl2-3, INPUT, DOWN); 1159 - PIN_SLP(gpl2-4, INPUT, DOWN); 1160 - PIN_SLP(gpl2-5, INPUT, DOWN); 1161 - PIN_SLP(gpl2-6, PREV, NONE); 1162 - PIN_SLP(gpl2-7, INPUT, DOWN); 1163 - 1164 - PIN_SLP(gpm0-0, INPUT, DOWN); 1165 - PIN_SLP(gpm0-1, INPUT, DOWN); 1166 - PIN_SLP(gpm0-2, INPUT, DOWN); 1167 - PIN_SLP(gpm0-3, INPUT, DOWN); 1168 - PIN_SLP(gpm0-4, INPUT, DOWN); 1169 - PIN_SLP(gpm0-5, INPUT, DOWN); 1170 - PIN_SLP(gpm0-6, INPUT, DOWN); 1171 - PIN_SLP(gpm0-7, INPUT, DOWN); 1172 - 1173 - PIN_SLP(gpm1-0, INPUT, DOWN); 1174 - PIN_SLP(gpm1-1, INPUT, DOWN); 1175 - PIN_SLP(gpm1-2, INPUT, NONE); 1176 - PIN_SLP(gpm1-3, INPUT, NONE); 1177 - PIN_SLP(gpm1-4, INPUT, NONE); 1178 - PIN_SLP(gpm1-5, INPUT, NONE); 1179 - PIN_SLP(gpm1-6, INPUT, DOWN); 1180 - 1181 - PIN_SLP(gpm2-0, INPUT, NONE); 1182 - PIN_SLP(gpm2-1, INPUT, NONE); 1183 - PIN_SLP(gpm2-2, INPUT, DOWN); 1184 - PIN_SLP(gpm2-3, INPUT, DOWN); 1185 - PIN_SLP(gpm2-4, INPUT, DOWN); 1186 - 1187 - PIN_SLP(gpm3-0, PREV, NONE); 1188 - PIN_SLP(gpm3-1, PREV, NONE); 1189 - PIN_SLP(gpm3-2, PREV, NONE); 1190 - PIN_SLP(gpm3-3, OUT1, NONE); 1191 - PIN_SLP(gpm3-4, INPUT, DOWN); 1192 - PIN_SLP(gpm3-5, INPUT, DOWN); 1193 - PIN_SLP(gpm3-6, INPUT, DOWN); 1194 - PIN_SLP(gpm3-7, INPUT, DOWN); 1195 - 1196 - PIN_SLP(gpm4-0, INPUT, DOWN); 1197 - PIN_SLP(gpm4-1, INPUT, DOWN); 1198 - PIN_SLP(gpm4-2, INPUT, DOWN); 1199 - PIN_SLP(gpm4-3, INPUT, DOWN); 1200 - PIN_SLP(gpm4-4, INPUT, DOWN); 1201 - PIN_SLP(gpm4-5, INPUT, DOWN); 1202 - PIN_SLP(gpm4-6, INPUT, DOWN); 1203 - PIN_SLP(gpm4-7, INPUT, DOWN); 1204 - 1205 - PIN_SLP(gpy0-0, INPUT, DOWN); 1206 - PIN_SLP(gpy0-1, INPUT, DOWN); 1207 - PIN_SLP(gpy0-2, INPUT, DOWN); 1208 - PIN_SLP(gpy0-3, INPUT, DOWN); 1209 - PIN_SLP(gpy0-4, INPUT, DOWN); 1210 - PIN_SLP(gpy0-5, INPUT, DOWN); 1211 - 1212 - PIN_SLP(gpy1-0, INPUT, DOWN); 1213 - PIN_SLP(gpy1-1, INPUT, DOWN); 1214 - PIN_SLP(gpy1-2, INPUT, DOWN); 1215 - PIN_SLP(gpy1-3, INPUT, DOWN); 1216 - 1217 - PIN_SLP(gpy2-0, PREV, NONE); 1218 - PIN_SLP(gpy2-1, INPUT, DOWN); 1219 - PIN_SLP(gpy2-2, INPUT, NONE); 1220 - PIN_SLP(gpy2-3, INPUT, NONE); 1221 - PIN_SLP(gpy2-4, INPUT, NONE); 1222 - PIN_SLP(gpy2-5, INPUT, NONE); 1223 - 1224 - PIN_SLP(gpy3-0, INPUT, DOWN); 1225 - PIN_SLP(gpy3-1, INPUT, DOWN); 1226 - PIN_SLP(gpy3-2, INPUT, DOWN); 1227 - PIN_SLP(gpy3-3, INPUT, DOWN); 1228 - PIN_SLP(gpy3-4, INPUT, DOWN); 1229 - PIN_SLP(gpy3-5, INPUT, DOWN); 1230 - PIN_SLP(gpy3-6, INPUT, DOWN); 1231 - PIN_SLP(gpy3-7, INPUT, DOWN); 1232 - 1233 - PIN_SLP(gpy4-0, INPUT, DOWN); 1234 - PIN_SLP(gpy4-1, INPUT, DOWN); 1235 - PIN_SLP(gpy4-2, INPUT, DOWN); 1236 - PIN_SLP(gpy4-3, INPUT, DOWN); 1237 - PIN_SLP(gpy4-4, INPUT, DOWN); 1238 - PIN_SLP(gpy4-5, INPUT, DOWN); 1239 - PIN_SLP(gpy4-6, INPUT, DOWN); 1240 - PIN_SLP(gpy4-7, INPUT, DOWN); 1241 - 1242 - PIN_SLP(gpy5-0, INPUT, DOWN); 1243 - PIN_SLP(gpy5-1, INPUT, DOWN); 1244 - PIN_SLP(gpy5-2, INPUT, DOWN); 1245 - PIN_SLP(gpy5-3, INPUT, DOWN); 1246 - PIN_SLP(gpy5-4, INPUT, DOWN); 1247 - PIN_SLP(gpy5-5, INPUT, DOWN); 1248 - PIN_SLP(gpy5-6, INPUT, DOWN); 1249 - PIN_SLP(gpy5-7, INPUT, DOWN); 1250 - 1251 - PIN_SLP(gpy6-0, INPUT, DOWN); 1252 - PIN_SLP(gpy6-1, INPUT, DOWN); 1253 - PIN_SLP(gpy6-2, INPUT, DOWN); 1254 - PIN_SLP(gpy6-3, INPUT, DOWN); 1255 - PIN_SLP(gpy6-4, INPUT, DOWN); 1256 - PIN_SLP(gpy6-5, INPUT, DOWN); 1257 - PIN_SLP(gpy6-6, INPUT, DOWN); 1258 - PIN_SLP(gpy6-7, INPUT, DOWN); 1259 - }; 1260 - }; 1261 - 1262 - &pinctrl_2 { 1263 - pinctrl-names = "default"; 1264 - pinctrl-0 = <&sleep2>; 1265 - 1266 - sleep2: sleep-states { 1267 - PIN_SLP(gpz-0, INPUT, DOWN); 1268 - PIN_SLP(gpz-1, INPUT, DOWN); 1269 - PIN_SLP(gpz-2, INPUT, DOWN); 1270 - PIN_SLP(gpz-3, INPUT, DOWN); 1271 - PIN_SLP(gpz-4, INPUT, DOWN); 1272 - PIN_SLP(gpz-5, INPUT, DOWN); 1273 - PIN_SLP(gpz-6, INPUT, DOWN); 1274 - }; 1275 - }; 1276 - 1277 - &pinctrl_3 { 1278 - pinctrl-names = "default"; 1279 - pinctrl-0 = <&sleep3>; 1280 - 1281 - sleep3: sleep-states { 1282 - PIN_SLP(gpv0-0, INPUT, DOWN); 1283 - PIN_SLP(gpv0-1, INPUT, DOWN); 1284 - PIN_SLP(gpv0-2, INPUT, DOWN); 1285 - PIN_SLP(gpv0-3, INPUT, DOWN); 1286 - PIN_SLP(gpv0-4, INPUT, DOWN); 1287 - PIN_SLP(gpv0-5, INPUT, DOWN); 1288 - PIN_SLP(gpv0-6, INPUT, DOWN); 1289 - PIN_SLP(gpv0-7, INPUT, DOWN); 1290 - 1291 - PIN_SLP(gpv1-0, INPUT, DOWN); 1292 - PIN_SLP(gpv1-1, INPUT, DOWN); 1293 - PIN_SLP(gpv1-2, INPUT, DOWN); 1294 - PIN_SLP(gpv1-3, INPUT, DOWN); 1295 - PIN_SLP(gpv1-4, INPUT, DOWN); 1296 - PIN_SLP(gpv1-5, INPUT, DOWN); 1297 - PIN_SLP(gpv1-6, INPUT, DOWN); 1298 - PIN_SLP(gpv1-7, INPUT, DOWN); 1299 - 1300 - PIN_SLP(gpv2-0, INPUT, DOWN); 1301 - PIN_SLP(gpv2-1, INPUT, DOWN); 1302 - PIN_SLP(gpv2-2, INPUT, DOWN); 1303 - PIN_SLP(gpv2-3, INPUT, DOWN); 1304 - PIN_SLP(gpv2-4, INPUT, DOWN); 1305 - PIN_SLP(gpv2-5, INPUT, DOWN); 1306 - PIN_SLP(gpv2-6, INPUT, DOWN); 1307 - PIN_SLP(gpv2-7, INPUT, DOWN); 1308 - 1309 - PIN_SLP(gpv3-0, INPUT, DOWN); 1310 - PIN_SLP(gpv3-1, INPUT, DOWN); 1311 - PIN_SLP(gpv3-2, INPUT, DOWN); 1312 - PIN_SLP(gpv3-3, INPUT, DOWN); 1313 - PIN_SLP(gpv3-4, INPUT, DOWN); 1314 - PIN_SLP(gpv3-5, INPUT, DOWN); 1315 - PIN_SLP(gpv3-6, INPUT, DOWN); 1316 - PIN_SLP(gpv3-7, INPUT, DOWN); 1317 - 1318 - PIN_SLP(gpv4-0, INPUT, DOWN); 1319 - }; 1320 - }; 1321 - 1322 - &pwm { 1323 - pinctrl-0 = <&pwm0_out>; 1324 - pinctrl-names = "default"; 1325 - samsung,pwm-outputs = <0>; 1326 - status = "okay"; 1327 - }; 1328 - 1329 - &rtc { 1330 - status = "okay"; 1331 - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; 1332 - clock-names = "rtc", "rtc_src"; 1333 - }; 1334 - 1335 - &sdhci_2 { 1336 - bus-width = <4>; 1337 - cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; 1338 - cd-inverted; 1339 - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; 1340 - pinctrl-names = "default"; 1341 - vmmc-supply = <&ldo21_reg>; 1342 - status = "okay"; 1343 - }; 1344 - 1345 - &sdhci_3 { 1346 - #address-cells = <1>; 1347 - #size-cells = <0>; 1348 - non-removable; 1349 - bus-width = <4>; 1350 - 1351 - mmc-pwrseq = <&wlan_pwrseq>; 1352 - pinctrl-names = "default"; 1353 - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; 1354 - status = "okay"; 1355 - 1356 - brcmf: wifi@1 { 1357 - reg = <1>; 1358 - compatible = "brcm,bcm4329-fmac"; 1359 - interrupt-parent = <&gpx2>; 1360 - interrupts = <5 IRQ_TYPE_NONE>; 1361 - interrupt-names = "host-wake"; 1362 - }; 1363 - }; 1364 - 1365 - &serial_0 { 1366 - status = "okay"; 1367 - }; 1368 - 1369 - &serial_1 { 1370 - status = "okay"; 1371 - }; 1372 - 1373 - &serial_2 { 1374 - status = "okay"; 1375 - }; 1376 - 1377 - &serial_3 { 1378 - status = "okay"; 1379 - }; 1380 - 1381 - &spi_1 { 1382 - pinctrl-names = "default"; 1383 - pinctrl-0 = <&spi1_bus>; 1384 - cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; 1385 - status = "okay"; 1386 - 1387 - s5c73m3_spi: s5c73m3@0 { 1388 - compatible = "samsung,s5c73m3"; 1389 - spi-max-frequency = <50000000>; 1390 - reg = <0>; 1391 - controller-data { 1392 - samsung,spi-feedback-delay = <2>; 1393 - }; 1394 - }; 1395 - }; 1396 - 1397 - &tmu { 1398 - vtmu-supply = <&ldo10_reg>; 1399 - status = "okay"; 1400 42 };
+448 -442
arch/arm/boot/dts/exynos4412.dtsi
··· 15 15 */ 16 16 17 17 #include "exynos4.dtsi" 18 - #include "exynos4412-pinctrl.dtsi" 18 + 19 19 #include "exynos4-cpu-thermal.dtsi" 20 20 21 21 / { ··· 42 42 clocks = <&clock CLK_ARM_CLK>; 43 43 clock-names = "cpu"; 44 44 operating-points-v2 = <&cpu0_opp_table>; 45 - cooling-min-level = <13>; 46 - cooling-max-level = <7>; 47 45 #cooling-cells = <2>; /* min followed by max */ 48 46 }; 49 47 ··· 145 147 }; 146 148 }; 147 149 148 - sysram@2020000 { 149 - compatible = "mmio-sram"; 150 - reg = <0x02020000 0x40000>; 151 - #address-cells = <1>; 152 - #size-cells = <1>; 153 - ranges = <0 0x02020000 0x40000>; 154 150 155 - smp-sysram@0 { 156 - compatible = "samsung,exynos4210-sysram"; 157 - reg = <0x0 0x1000>; 151 + soc: soc { 152 + 153 + pinctrl_0: pinctrl@11400000 { 154 + compatible = "samsung,exynos4x12-pinctrl"; 155 + reg = <0x11400000 0x1000>; 156 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 158 157 }; 159 158 160 - smp-sysram@2f000 { 161 - compatible = "samsung,exynos4210-sysram-ns"; 162 - reg = <0x2f000 0x1000>; 159 + pinctrl_1: pinctrl@11000000 { 160 + compatible = "samsung,exynos4x12-pinctrl"; 161 + reg = <0x11000000 0x1000>; 162 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 163 + 164 + wakup_eint: wakeup-interrupt-controller { 165 + compatible = "samsung,exynos4210-wakeup-eint"; 166 + interrupt-parent = <&gic>; 167 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 168 + }; 163 169 }; 164 - }; 165 170 166 - pd_isp: isp-power-domain@10023ca0 { 167 - compatible = "samsung,exynos4210-pd"; 168 - reg = <0x10023CA0 0x20>; 169 - #power-domain-cells = <0>; 170 - label = "ISP"; 171 - }; 171 + pinctrl_2: pinctrl@3860000 { 172 + compatible = "samsung,exynos4x12-pinctrl"; 173 + reg = <0x03860000 0x1000>; 174 + interrupt-parent = <&combiner>; 175 + interrupts = <10 0>; 176 + }; 172 177 173 - l2c: l2-cache-controller@10502000 { 174 - compatible = "arm,pl310-cache"; 175 - reg = <0x10502000 0x1000>; 176 - cache-unified; 177 - cache-level = <2>; 178 - arm,tag-latency = <2 2 1>; 179 - arm,data-latency = <3 2 1>; 180 - arm,double-linefill = <1>; 181 - arm,double-linefill-incr = <0>; 182 - arm,double-linefill-wrap = <1>; 183 - arm,prefetch-drop = <1>; 184 - arm,prefetch-offset = <7>; 185 - }; 178 + pinctrl_3: pinctrl@106e0000 { 179 + compatible = "samsung,exynos4x12-pinctrl"; 180 + reg = <0x106E0000 0x1000>; 181 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 182 + }; 186 183 187 - clock: clock-controller@10030000 { 188 - compatible = "samsung,exynos4412-clock"; 189 - reg = <0x10030000 0x18000>; 190 - #clock-cells = <1>; 191 - }; 184 + sysram@2020000 { 185 + compatible = "mmio-sram"; 186 + reg = <0x02020000 0x40000>; 187 + #address-cells = <1>; 188 + #size-cells = <1>; 189 + ranges = <0 0x02020000 0x40000>; 192 190 193 - isp_clock: clock-controller@10048000 { 194 - compatible = "samsung,exynos4412-isp-clock"; 195 - reg = <0x10048000 0x1000>; 196 - #clock-cells = <1>; 197 - power-domains = <&pd_isp>; 198 - clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; 199 - clock-names = "aclk200", "aclk400_mcuisp"; 200 - }; 191 + smp-sysram@0 { 192 + compatible = "samsung,exynos4210-sysram"; 193 + reg = <0x0 0x1000>; 194 + }; 201 195 202 - mct@10050000 { 203 - compatible = "samsung,exynos4412-mct"; 204 - reg = <0x10050000 0x800>; 205 - interrupt-parent = <&mct_map>; 206 - interrupts = <0>, <1>, <2>, <3>, <4>; 207 - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 208 - clock-names = "fin_pll", "mct"; 196 + smp-sysram@2f000 { 197 + compatible = "samsung,exynos4210-sysram-ns"; 198 + reg = <0x2f000 0x1000>; 199 + }; 200 + }; 209 201 210 - mct_map: mct-map { 211 - #interrupt-cells = <1>; 212 - #address-cells = <0>; 213 - #size-cells = <0>; 214 - interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 202 + pd_isp: isp-power-domain@10023ca0 { 203 + compatible = "samsung,exynos4210-pd"; 204 + reg = <0x10023CA0 0x20>; 205 + #power-domain-cells = <0>; 206 + label = "ISP"; 207 + }; 208 + 209 + l2c: l2-cache-controller@10502000 { 210 + compatible = "arm,pl310-cache"; 211 + reg = <0x10502000 0x1000>; 212 + cache-unified; 213 + cache-level = <2>; 214 + arm,tag-latency = <2 2 1>; 215 + arm,data-latency = <3 2 1>; 216 + arm,double-linefill = <1>; 217 + arm,double-linefill-incr = <0>; 218 + arm,double-linefill-wrap = <1>; 219 + arm,prefetch-drop = <1>; 220 + arm,prefetch-offset = <7>; 221 + }; 222 + 223 + clock: clock-controller@10030000 { 224 + compatible = "samsung,exynos4412-clock"; 225 + reg = <0x10030000 0x18000>; 226 + #clock-cells = <1>; 227 + }; 228 + 229 + isp_clock: clock-controller@10048000 { 230 + compatible = "samsung,exynos4412-isp-clock"; 231 + reg = <0x10048000 0x1000>; 232 + #clock-cells = <1>; 233 + power-domains = <&pd_isp>; 234 + clocks = <&clock CLK_ACLK200>, 235 + <&clock CLK_ACLK400_MCUISP>; 236 + clock-names = "aclk200", "aclk400_mcuisp"; 237 + }; 238 + 239 + mct@10050000 { 240 + compatible = "samsung,exynos4412-mct"; 241 + reg = <0x10050000 0x800>; 242 + interrupt-parent = <&mct_map>; 243 + interrupts = <0>, <1>, <2>, <3>, <4>; 244 + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 245 + clock-names = "fin_pll", "mct"; 246 + 247 + mct_map: mct-map { 248 + #interrupt-cells = <1>; 249 + #address-cells = <0>; 250 + #size-cells = <0>; 251 + interrupt-map = 252 + <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 215 253 <1 &combiner 12 5>, 216 254 <2 &combiner 12 6>, 217 255 <3 &combiner 12 7>, 218 256 <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; 257 + }; 219 258 }; 220 - }; 221 259 222 - watchdog: watchdog@10060000 { 223 - compatible = "samsung,exynos5250-wdt"; 224 - reg = <0x10060000 0x100>; 225 - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 226 - clocks = <&clock CLK_WDT>; 227 - clock-names = "watchdog"; 228 - samsung,syscon-phandle = <&pmu_system_controller>; 229 - }; 260 + watchdog: watchdog@10060000 { 261 + compatible = "samsung,exynos5250-wdt"; 262 + reg = <0x10060000 0x100>; 263 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 264 + clocks = <&clock CLK_WDT>; 265 + clock-names = "watchdog"; 266 + samsung,syscon-phandle = <&pmu_system_controller>; 267 + }; 230 268 231 - adc: adc@126c0000 { 232 - compatible = "samsung,exynos-adc-v1"; 233 - reg = <0x126C0000 0x100>; 234 - interrupt-parent = <&combiner>; 235 - interrupts = <10 3>; 236 - clocks = <&clock CLK_TSADC>; 237 - clock-names = "adc"; 238 - #io-channel-cells = <1>; 239 - io-channel-ranges; 240 - samsung,syscon-phandle = <&pmu_system_controller>; 241 - status = "disabled"; 242 - }; 243 - 244 - g2d: g2d@10800000 { 245 - compatible = "samsung,exynos4212-g2d"; 246 - reg = <0x10800000 0x1000>; 247 - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 248 - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 249 - clock-names = "sclk_fimg2d", "fimg2d"; 250 - iommus = <&sysmmu_g2d>; 251 - }; 252 - 253 - camera { 254 - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 255 - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 256 - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 257 - 258 - /* fimc_[0-3] are configured outside, under phandles */ 259 - fimc_lite_0: fimc-lite@12390000 { 260 - compatible = "samsung,exynos4212-fimc-lite"; 261 - reg = <0x12390000 0x1000>; 262 - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 263 - power-domains = <&pd_isp>; 264 - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; 265 - clock-names = "flite"; 266 - iommus = <&sysmmu_fimc_lite0>; 269 + adc: adc@126c0000 { 270 + compatible = "samsung,exynos-adc-v1"; 271 + reg = <0x126C0000 0x100>; 272 + interrupt-parent = <&combiner>; 273 + interrupts = <10 3>; 274 + clocks = <&clock CLK_TSADC>; 275 + clock-names = "adc"; 276 + #io-channel-cells = <1>; 277 + io-channel-ranges; 278 + samsung,syscon-phandle = <&pmu_system_controller>; 267 279 status = "disabled"; 268 280 }; 269 281 270 - fimc_lite_1: fimc-lite@123a0000 { 271 - compatible = "samsung,exynos4212-fimc-lite"; 272 - reg = <0x123A0000 0x1000>; 273 - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 274 - power-domains = <&pd_isp>; 275 - clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; 276 - clock-names = "flite"; 277 - iommus = <&sysmmu_fimc_lite1>; 278 - status = "disabled"; 282 + g2d: g2d@10800000 { 283 + compatible = "samsung,exynos4212-g2d"; 284 + reg = <0x10800000 0x1000>; 285 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 286 + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 287 + clock-names = "sclk_fimg2d", "fimg2d"; 288 + iommus = <&sysmmu_g2d>; 279 289 }; 280 290 281 - fimc_is: fimc-is@12000000 { 282 - compatible = "samsung,exynos4212-fimc-is"; 283 - reg = <0x12000000 0x260000>; 284 - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 285 - <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 286 - power-domains = <&pd_isp>; 287 - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, 288 - <&isp_clock CLK_ISP_FIMC_LITE1>, 289 - <&isp_clock CLK_ISP_PPMUISPX>, 290 - <&isp_clock CLK_ISP_PPMUISPMX>, 291 - <&isp_clock CLK_ISP_FIMC_ISP>, 292 - <&isp_clock CLK_ISP_FIMC_DRC>, 293 - <&isp_clock CLK_ISP_FIMC_FD>, 294 - <&isp_clock CLK_ISP_MCUISP>, 295 - <&isp_clock CLK_ISP_GICISP>, 296 - <&isp_clock CLK_ISP_MCUCTL_ISP>, 297 - <&isp_clock CLK_ISP_PWM_ISP>, 298 - <&isp_clock CLK_ISP_DIV_ISP0>, 299 - <&isp_clock CLK_ISP_DIV_ISP1>, 300 - <&isp_clock CLK_ISP_DIV_MCUISP0>, 301 - <&isp_clock CLK_ISP_DIV_MCUISP1>, 302 - <&clock CLK_MOUT_MPLL_USER_T>, 303 - <&clock CLK_ACLK200>, 304 - <&clock CLK_ACLK400_MCUISP>, 305 - <&clock CLK_DIV_ACLK200>, 306 - <&clock CLK_DIV_ACLK400_MCUISP>, 307 - <&clock CLK_UART_ISP_SCLK>; 308 - clock-names = "lite0", "lite1", "ppmuispx", 309 - "ppmuispmx", "isp", 310 - "drc", "fd", "mcuisp", 311 - "gicisp", "mcuctl_isp", "pwm_isp", 312 - "ispdiv0", "ispdiv1", "mcuispdiv0", 313 - "mcuispdiv1", "mpll", "aclk200", 314 - "aclk400mcuisp", "div_aclk200", 315 - "div_aclk400mcuisp", "uart"; 316 - iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, 317 - <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; 318 - iommu-names = "isp", "drc", "fd", "mcuctl"; 291 + mshc_0: mmc@12550000 { 292 + compatible = "samsung,exynos4412-dw-mshc"; 293 + reg = <0x12550000 0x1000>; 294 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 319 295 #address-cells = <1>; 320 - #size-cells = <1>; 321 - ranges; 296 + #size-cells = <0>; 297 + fifo-depth = <0x80>; 298 + clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; 299 + clock-names = "biu", "ciu"; 322 300 status = "disabled"; 301 + }; 323 302 324 - pmu@10020000 { 325 - reg = <0x10020000 0x3000>; 303 + sysmmu_g2d: sysmmu@10A40000{ 304 + compatible = "samsung,exynos-sysmmu"; 305 + reg = <0x10A40000 0x1000>; 306 + interrupt-parent = <&combiner>; 307 + interrupts = <4 7>; 308 + clock-names = "sysmmu", "master"; 309 + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 310 + #iommu-cells = <0>; 311 + }; 312 + 313 + sysmmu_fimc_isp: sysmmu@12260000 { 314 + compatible = "samsung,exynos-sysmmu"; 315 + reg = <0x12260000 0x1000>; 316 + interrupt-parent = <&combiner>; 317 + interrupts = <16 2>; 318 + power-domains = <&pd_isp>; 319 + clock-names = "sysmmu"; 320 + clocks = <&isp_clock CLK_ISP_SMMU_ISP>; 321 + #iommu-cells = <0>; 322 + }; 323 + 324 + sysmmu_fimc_drc: sysmmu@12270000 { 325 + compatible = "samsung,exynos-sysmmu"; 326 + reg = <0x12270000 0x1000>; 327 + interrupt-parent = <&combiner>; 328 + interrupts = <16 3>; 329 + power-domains = <&pd_isp>; 330 + clock-names = "sysmmu"; 331 + clocks = <&isp_clock CLK_ISP_SMMU_DRC>; 332 + #iommu-cells = <0>; 333 + }; 334 + 335 + sysmmu_fimc_fd: sysmmu@122a0000 { 336 + compatible = "samsung,exynos-sysmmu"; 337 + reg = <0x122A0000 0x1000>; 338 + interrupt-parent = <&combiner>; 339 + interrupts = <16 4>; 340 + power-domains = <&pd_isp>; 341 + clock-names = "sysmmu"; 342 + clocks = <&isp_clock CLK_ISP_SMMU_FD>; 343 + #iommu-cells = <0>; 344 + }; 345 + 346 + sysmmu_fimc_mcuctl: sysmmu@122b0000 { 347 + compatible = "samsung,exynos-sysmmu"; 348 + reg = <0x122B0000 0x1000>; 349 + interrupt-parent = <&combiner>; 350 + interrupts = <16 5>; 351 + power-domains = <&pd_isp>; 352 + clock-names = "sysmmu"; 353 + clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; 354 + #iommu-cells = <0>; 355 + }; 356 + 357 + sysmmu_fimc_lite0: sysmmu@123b0000 { 358 + compatible = "samsung,exynos-sysmmu"; 359 + reg = <0x123B0000 0x1000>; 360 + interrupt-parent = <&combiner>; 361 + interrupts = <16 0>; 362 + power-domains = <&pd_isp>; 363 + clock-names = "sysmmu", "master"; 364 + clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, 365 + <&isp_clock CLK_ISP_FIMC_LITE0>; 366 + #iommu-cells = <0>; 367 + }; 368 + 369 + sysmmu_fimc_lite1: sysmmu@123c0000 { 370 + compatible = "samsung,exynos-sysmmu"; 371 + reg = <0x123C0000 0x1000>; 372 + interrupt-parent = <&combiner>; 373 + interrupts = <16 1>; 374 + power-domains = <&pd_isp>; 375 + clock-names = "sysmmu", "master"; 376 + clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, 377 + <&isp_clock CLK_ISP_FIMC_LITE1>; 378 + #iommu-cells = <0>; 379 + }; 380 + 381 + bus_dmc: bus_dmc { 382 + compatible = "samsung,exynos-bus"; 383 + clocks = <&clock CLK_DIV_DMC>; 384 + clock-names = "bus"; 385 + operating-points-v2 = <&bus_dmc_opp_table>; 386 + status = "disabled"; 387 + }; 388 + 389 + bus_acp: bus_acp { 390 + compatible = "samsung,exynos-bus"; 391 + clocks = <&clock CLK_DIV_ACP>; 392 + clock-names = "bus"; 393 + operating-points-v2 = <&bus_acp_opp_table>; 394 + status = "disabled"; 395 + }; 396 + 397 + bus_c2c: bus_c2c { 398 + compatible = "samsung,exynos-bus"; 399 + clocks = <&clock CLK_DIV_C2C>; 400 + clock-names = "bus"; 401 + operating-points-v2 = <&bus_dmc_opp_table>; 402 + status = "disabled"; 403 + }; 404 + 405 + bus_dmc_opp_table: opp_table1 { 406 + compatible = "operating-points-v2"; 407 + opp-shared; 408 + 409 + opp-100000000 { 410 + opp-hz = /bits/ 64 <100000000>; 411 + opp-microvolt = <900000>; 326 412 }; 327 - 328 - i2c1_isp: i2c-isp@12140000 { 329 - compatible = "samsung,exynos4212-i2c-isp"; 330 - reg = <0x12140000 0x100>; 331 - clocks = <&isp_clock CLK_ISP_I2C1_ISP>; 332 - clock-names = "i2c_isp"; 333 - #address-cells = <1>; 334 - #size-cells = <0>; 413 + opp-134000000 { 414 + opp-hz = /bits/ 64 <134000000>; 415 + opp-microvolt = <900000>; 416 + }; 417 + opp-160000000 { 418 + opp-hz = /bits/ 64 <160000000>; 419 + opp-microvolt = <900000>; 420 + }; 421 + opp-267000000 { 422 + opp-hz = /bits/ 64 <267000000>; 423 + opp-microvolt = <950000>; 424 + }; 425 + opp-400000000 { 426 + opp-hz = /bits/ 64 <400000000>; 427 + opp-microvolt = <1050000>; 335 428 }; 336 429 }; 337 - }; 338 430 339 - mshc_0: mmc@12550000 { 340 - compatible = "samsung,exynos4412-dw-mshc"; 341 - reg = <0x12550000 0x1000>; 342 - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 343 - #address-cells = <1>; 344 - #size-cells = <0>; 345 - fifo-depth = <0x80>; 346 - clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; 347 - clock-names = "biu", "ciu"; 348 - status = "disabled"; 349 - }; 431 + bus_acp_opp_table: opp_table2 { 432 + compatible = "operating-points-v2"; 433 + opp-shared; 350 434 351 - sysmmu_g2d: sysmmu@10A40000{ 352 - compatible = "samsung,exynos-sysmmu"; 353 - reg = <0x10A40000 0x1000>; 354 - interrupt-parent = <&combiner>; 355 - interrupts = <4 7>; 356 - clock-names = "sysmmu", "master"; 357 - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 358 - #iommu-cells = <0>; 359 - }; 360 - 361 - sysmmu_fimc_isp: sysmmu@12260000 { 362 - compatible = "samsung,exynos-sysmmu"; 363 - reg = <0x12260000 0x1000>; 364 - interrupt-parent = <&combiner>; 365 - interrupts = <16 2>; 366 - power-domains = <&pd_isp>; 367 - clock-names = "sysmmu"; 368 - clocks = <&isp_clock CLK_ISP_SMMU_ISP>; 369 - #iommu-cells = <0>; 370 - }; 371 - 372 - sysmmu_fimc_drc: sysmmu@12270000 { 373 - compatible = "samsung,exynos-sysmmu"; 374 - reg = <0x12270000 0x1000>; 375 - interrupt-parent = <&combiner>; 376 - interrupts = <16 3>; 377 - power-domains = <&pd_isp>; 378 - clock-names = "sysmmu"; 379 - clocks = <&isp_clock CLK_ISP_SMMU_DRC>; 380 - #iommu-cells = <0>; 381 - }; 382 - 383 - sysmmu_fimc_fd: sysmmu@122a0000 { 384 - compatible = "samsung,exynos-sysmmu"; 385 - reg = <0x122A0000 0x1000>; 386 - interrupt-parent = <&combiner>; 387 - interrupts = <16 4>; 388 - power-domains = <&pd_isp>; 389 - clock-names = "sysmmu"; 390 - clocks = <&isp_clock CLK_ISP_SMMU_FD>; 391 - #iommu-cells = <0>; 392 - }; 393 - 394 - sysmmu_fimc_mcuctl: sysmmu@122b0000 { 395 - compatible = "samsung,exynos-sysmmu"; 396 - reg = <0x122B0000 0x1000>; 397 - interrupt-parent = <&combiner>; 398 - interrupts = <16 5>; 399 - power-domains = <&pd_isp>; 400 - clock-names = "sysmmu"; 401 - clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; 402 - #iommu-cells = <0>; 403 - }; 404 - 405 - sysmmu_fimc_lite0: sysmmu@123b0000 { 406 - compatible = "samsung,exynos-sysmmu"; 407 - reg = <0x123B0000 0x1000>; 408 - interrupt-parent = <&combiner>; 409 - interrupts = <16 0>; 410 - power-domains = <&pd_isp>; 411 - clock-names = "sysmmu", "master"; 412 - clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, 413 - <&isp_clock CLK_ISP_FIMC_LITE0>; 414 - #iommu-cells = <0>; 415 - }; 416 - 417 - sysmmu_fimc_lite1: sysmmu@123c0000 { 418 - compatible = "samsung,exynos-sysmmu"; 419 - reg = <0x123C0000 0x1000>; 420 - interrupt-parent = <&combiner>; 421 - interrupts = <16 1>; 422 - power-domains = <&pd_isp>; 423 - clock-names = "sysmmu", "master"; 424 - clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, 425 - <&isp_clock CLK_ISP_FIMC_LITE1>; 426 - #iommu-cells = <0>; 427 - }; 428 - 429 - bus_dmc: bus_dmc { 430 - compatible = "samsung,exynos-bus"; 431 - clocks = <&clock CLK_DIV_DMC>; 432 - clock-names = "bus"; 433 - operating-points-v2 = <&bus_dmc_opp_table>; 434 - status = "disabled"; 435 - }; 436 - 437 - bus_acp: bus_acp { 438 - compatible = "samsung,exynos-bus"; 439 - clocks = <&clock CLK_DIV_ACP>; 440 - clock-names = "bus"; 441 - operating-points-v2 = <&bus_acp_opp_table>; 442 - status = "disabled"; 443 - }; 444 - 445 - bus_c2c: bus_c2c { 446 - compatible = "samsung,exynos-bus"; 447 - clocks = <&clock CLK_DIV_C2C>; 448 - clock-names = "bus"; 449 - operating-points-v2 = <&bus_dmc_opp_table>; 450 - status = "disabled"; 451 - }; 452 - 453 - bus_dmc_opp_table: opp_table1 { 454 - compatible = "operating-points-v2"; 455 - opp-shared; 456 - 457 - opp-100000000 { 458 - opp-hz = /bits/ 64 <100000000>; 459 - opp-microvolt = <900000>; 435 + opp-100000000 { 436 + opp-hz = /bits/ 64 <100000000>; 437 + }; 438 + opp-134000000 { 439 + opp-hz = /bits/ 64 <134000000>; 440 + }; 441 + opp-160000000 { 442 + opp-hz = /bits/ 64 <160000000>; 443 + }; 444 + opp-267000000 { 445 + opp-hz = /bits/ 64 <267000000>; 446 + }; 460 447 }; 461 - opp-134000000 { 462 - opp-hz = /bits/ 64 <134000000>; 463 - opp-microvolt = <900000>; 464 - }; 465 - opp-160000000 { 466 - opp-hz = /bits/ 64 <160000000>; 467 - opp-microvolt = <900000>; 468 - }; 469 - opp-267000000 { 470 - opp-hz = /bits/ 64 <267000000>; 471 - opp-microvolt = <950000>; 472 - }; 473 - opp-400000000 { 474 - opp-hz = /bits/ 64 <400000000>; 475 - opp-microvolt = <1050000>; 476 - }; 477 - }; 478 448 479 - bus_acp_opp_table: opp_table2 { 480 - compatible = "operating-points-v2"; 481 - opp-shared; 482 - 483 - opp-100000000 { 484 - opp-hz = /bits/ 64 <100000000>; 449 + bus_leftbus: bus_leftbus { 450 + compatible = "samsung,exynos-bus"; 451 + clocks = <&clock CLK_DIV_GDL>; 452 + clock-names = "bus"; 453 + operating-points-v2 = <&bus_leftbus_opp_table>; 454 + status = "disabled"; 485 455 }; 486 - opp-134000000 { 487 - opp-hz = /bits/ 64 <134000000>; 456 + 457 + bus_rightbus: bus_rightbus { 458 + compatible = "samsung,exynos-bus"; 459 + clocks = <&clock CLK_DIV_GDR>; 460 + clock-names = "bus"; 461 + operating-points-v2 = <&bus_leftbus_opp_table>; 462 + status = "disabled"; 488 463 }; 489 - opp-160000000 { 490 - opp-hz = /bits/ 64 <160000000>; 464 + 465 + bus_display: bus_display { 466 + compatible = "samsung,exynos-bus"; 467 + clocks = <&clock CLK_ACLK160>; 468 + clock-names = "bus"; 469 + operating-points-v2 = <&bus_display_opp_table>; 470 + status = "disabled"; 491 471 }; 492 - opp-267000000 { 493 - opp-hz = /bits/ 64 <267000000>; 472 + 473 + bus_fsys: bus_fsys { 474 + compatible = "samsung,exynos-bus"; 475 + clocks = <&clock CLK_ACLK133>; 476 + clock-names = "bus"; 477 + operating-points-v2 = <&bus_fsys_opp_table>; 478 + status = "disabled"; 494 479 }; 495 - }; 496 480 497 - bus_leftbus: bus_leftbus { 498 - compatible = "samsung,exynos-bus"; 499 - clocks = <&clock CLK_DIV_GDL>; 500 - clock-names = "bus"; 501 - operating-points-v2 = <&bus_leftbus_opp_table>; 502 - status = "disabled"; 503 - }; 504 - 505 - bus_rightbus: bus_rightbus { 506 - compatible = "samsung,exynos-bus"; 507 - clocks = <&clock CLK_DIV_GDR>; 508 - clock-names = "bus"; 509 - operating-points-v2 = <&bus_leftbus_opp_table>; 510 - status = "disabled"; 511 - }; 512 - 513 - bus_display: bus_display { 514 - compatible = "samsung,exynos-bus"; 515 - clocks = <&clock CLK_ACLK160>; 516 - clock-names = "bus"; 517 - operating-points-v2 = <&bus_display_opp_table>; 518 - status = "disabled"; 519 - }; 520 - 521 - bus_fsys: bus_fsys { 522 - compatible = "samsung,exynos-bus"; 523 - clocks = <&clock CLK_ACLK133>; 524 - clock-names = "bus"; 525 - operating-points-v2 = <&bus_fsys_opp_table>; 526 - status = "disabled"; 527 - }; 528 - 529 - bus_peri: bus_peri { 530 - compatible = "samsung,exynos-bus"; 531 - clocks = <&clock CLK_ACLK100>; 532 - clock-names = "bus"; 533 - operating-points-v2 = <&bus_peri_opp_table>; 534 - status = "disabled"; 535 - }; 536 - 537 - bus_mfc: bus_mfc { 538 - compatible = "samsung,exynos-bus"; 539 - clocks = <&clock CLK_SCLK_MFC>; 540 - clock-names = "bus"; 541 - operating-points-v2 = <&bus_leftbus_opp_table>; 542 - status = "disabled"; 543 - }; 544 - 545 - bus_leftbus_opp_table: opp_table3 { 546 - compatible = "operating-points-v2"; 547 - opp-shared; 548 - 549 - opp-100000000 { 550 - opp-hz = /bits/ 64 <100000000>; 551 - opp-microvolt = <900000>; 481 + bus_peri: bus_peri { 482 + compatible = "samsung,exynos-bus"; 483 + clocks = <&clock CLK_ACLK100>; 484 + clock-names = "bus"; 485 + operating-points-v2 = <&bus_peri_opp_table>; 486 + status = "disabled"; 552 487 }; 553 - opp-134000000 { 554 - opp-hz = /bits/ 64 <134000000>; 555 - opp-microvolt = <925000>; 556 - }; 557 - opp-160000000 { 558 - opp-hz = /bits/ 64 <160000000>; 559 - opp-microvolt = <950000>; 560 - }; 561 - opp-200000000 { 562 - opp-hz = /bits/ 64 <200000000>; 563 - opp-microvolt = <1000000>; 564 - }; 565 - }; 566 488 567 - bus_display_opp_table: opp_table4 { 568 - compatible = "operating-points-v2"; 569 - opp-shared; 570 - 571 - opp-160000000 { 572 - opp-hz = /bits/ 64 <160000000>; 489 + bus_mfc: bus_mfc { 490 + compatible = "samsung,exynos-bus"; 491 + clocks = <&clock CLK_SCLK_MFC>; 492 + clock-names = "bus"; 493 + operating-points-v2 = <&bus_leftbus_opp_table>; 494 + status = "disabled"; 573 495 }; 574 - opp-200000000 { 575 - opp-hz = /bits/ 64 <200000000>; 576 - }; 577 - }; 578 496 579 - bus_fsys_opp_table: opp_table5 { 580 - compatible = "operating-points-v2"; 581 - opp-shared; 497 + bus_leftbus_opp_table: opp_table3 { 498 + compatible = "operating-points-v2"; 499 + opp-shared; 582 500 583 - opp-100000000 { 584 - opp-hz = /bits/ 64 <100000000>; 501 + opp-100000000 { 502 + opp-hz = /bits/ 64 <100000000>; 503 + opp-microvolt = <900000>; 504 + }; 505 + opp-134000000 { 506 + opp-hz = /bits/ 64 <134000000>; 507 + opp-microvolt = <925000>; 508 + }; 509 + opp-160000000 { 510 + opp-hz = /bits/ 64 <160000000>; 511 + opp-microvolt = <950000>; 512 + }; 513 + opp-200000000 { 514 + opp-hz = /bits/ 64 <200000000>; 515 + opp-microvolt = <1000000>; 516 + }; 585 517 }; 586 - opp-134000000 { 587 - opp-hz = /bits/ 64 <134000000>; 588 - }; 589 - }; 590 518 591 - bus_peri_opp_table: opp_table6 { 592 - compatible = "operating-points-v2"; 593 - opp-shared; 519 + bus_display_opp_table: opp_table4 { 520 + compatible = "operating-points-v2"; 521 + opp-shared; 594 522 595 - opp-50000000 { 596 - opp-hz = /bits/ 64 <50000000>; 523 + opp-160000000 { 524 + opp-hz = /bits/ 64 <160000000>; 525 + }; 526 + opp-200000000 { 527 + opp-hz = /bits/ 64 <200000000>; 528 + }; 597 529 }; 598 - opp-100000000 { 599 - opp-hz = /bits/ 64 <100000000>; 600 - }; 601 - }; 602 530 603 - pmu { 604 - interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 531 + bus_fsys_opp_table: opp_table5 { 532 + compatible = "operating-points-v2"; 533 + opp-shared; 534 + 535 + opp-100000000 { 536 + opp-hz = /bits/ 64 <100000000>; 537 + }; 538 + opp-134000000 { 539 + opp-hz = /bits/ 64 <134000000>; 540 + }; 541 + }; 542 + 543 + bus_peri_opp_table: opp_table6 { 544 + compatible = "operating-points-v2"; 545 + opp-shared; 546 + 547 + opp-50000000 { 548 + opp-hz = /bits/ 64 <50000000>; 549 + }; 550 + opp-100000000 { 551 + opp-hz = /bits/ 64 <100000000>; 552 + }; 553 + }; 605 554 }; 606 555 }; 607 556 ··· 574 629 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 575 630 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 576 631 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 632 + }; 633 + 634 + &camera { 635 + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 636 + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 637 + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 638 + 639 + /* fimc_[0-3] are configured outside, under phandles */ 640 + fimc_lite_0: fimc-lite@12390000 { 641 + compatible = "samsung,exynos4212-fimc-lite"; 642 + reg = <0x12390000 0x1000>; 643 + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 644 + power-domains = <&pd_isp>; 645 + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; 646 + clock-names = "flite"; 647 + iommus = <&sysmmu_fimc_lite0>; 648 + status = "disabled"; 649 + }; 650 + 651 + fimc_lite_1: fimc-lite@123a0000 { 652 + compatible = "samsung,exynos4212-fimc-lite"; 653 + reg = <0x123A0000 0x1000>; 654 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 655 + power-domains = <&pd_isp>; 656 + clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; 657 + clock-names = "flite"; 658 + iommus = <&sysmmu_fimc_lite1>; 659 + status = "disabled"; 660 + }; 661 + 662 + fimc_is: fimc-is@12000000 { 663 + compatible = "samsung,exynos4212-fimc-is"; 664 + reg = <0x12000000 0x260000>; 665 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 666 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 667 + power-domains = <&pd_isp>; 668 + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, 669 + <&isp_clock CLK_ISP_FIMC_LITE1>, 670 + <&isp_clock CLK_ISP_PPMUISPX>, 671 + <&isp_clock CLK_ISP_PPMUISPMX>, 672 + <&isp_clock CLK_ISP_FIMC_ISP>, 673 + <&isp_clock CLK_ISP_FIMC_DRC>, 674 + <&isp_clock CLK_ISP_FIMC_FD>, 675 + <&isp_clock CLK_ISP_MCUISP>, 676 + <&isp_clock CLK_ISP_GICISP>, 677 + <&isp_clock CLK_ISP_MCUCTL_ISP>, 678 + <&isp_clock CLK_ISP_PWM_ISP>, 679 + <&isp_clock CLK_ISP_DIV_ISP0>, 680 + <&isp_clock CLK_ISP_DIV_ISP1>, 681 + <&isp_clock CLK_ISP_DIV_MCUISP0>, 682 + <&isp_clock CLK_ISP_DIV_MCUISP1>, 683 + <&clock CLK_MOUT_MPLL_USER_T>, 684 + <&clock CLK_ACLK200>, 685 + <&clock CLK_ACLK400_MCUISP>, 686 + <&clock CLK_DIV_ACLK200>, 687 + <&clock CLK_DIV_ACLK400_MCUISP>, 688 + <&clock CLK_UART_ISP_SCLK>; 689 + clock-names = "lite0", "lite1", "ppmuispx", 690 + "ppmuispmx", "isp", 691 + "drc", "fd", "mcuisp", 692 + "gicisp", "mcuctl_isp", "pwm_isp", 693 + "ispdiv0", "ispdiv1", "mcuispdiv0", 694 + "mcuispdiv1", "mpll", "aclk200", 695 + "aclk400mcuisp", "div_aclk200", 696 + "div_aclk400mcuisp", "uart"; 697 + iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, 698 + <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; 699 + iommu-names = "isp", "drc", "fd", "mcuctl"; 700 + #address-cells = <1>; 701 + #size-cells = <1>; 702 + ranges; 703 + status = "disabled"; 704 + 705 + pmu@10020000 { 706 + reg = <0x10020000 0x3000>; 707 + }; 708 + 709 + i2c1_isp: i2c-isp@12140000 { 710 + compatible = "samsung,exynos4212-i2c-isp"; 711 + reg = <0x12140000 0x100>; 712 + clocks = <&isp_clock CLK_ISP_I2C1_ISP>; 713 + clock-names = "i2c_isp"; 714 + #address-cells = <1>; 715 + #size-cells = <0>; 716 + }; 717 + }; 577 718 }; 578 719 579 720 &exynos_usbphy { ··· 724 693 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; 725 694 }; 726 695 727 - &pinctrl_0 { 728 - compatible = "samsung,exynos4x12-pinctrl"; 729 - reg = <0x11400000 0x1000>; 730 - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 731 - }; 732 - 733 - &pinctrl_1 { 734 - compatible = "samsung,exynos4x12-pinctrl"; 735 - reg = <0x11000000 0x1000>; 736 - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 737 - 738 - wakup_eint: wakeup-interrupt-controller { 739 - compatible = "samsung,exynos4210-wakeup-eint"; 740 - interrupt-parent = <&gic>; 741 - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 742 - }; 743 - }; 744 - 745 - &pinctrl_2 { 746 - compatible = "samsung,exynos4x12-pinctrl"; 747 - reg = <0x03860000 0x1000>; 748 - interrupt-parent = <&combiner>; 749 - interrupts = <10 0>; 750 - }; 751 - 752 - &pinctrl_3 { 753 - compatible = "samsung,exynos4x12-pinctrl"; 754 - reg = <0x106E0000 0x1000>; 755 - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 696 + &pmu { 697 + interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 756 698 }; 757 699 758 700 &pmu_system_controller { ··· 747 743 clock-names = "tmu_apbif"; 748 744 status = "disabled"; 749 745 }; 746 + 747 + #include "exynos4412-pinctrl.dtsi"
+4 -6
arch/arm/boot/dts/exynos5250.dtsi
··· 77 77 300000 937500 78 78 200000 925000 79 79 >; 80 - cooling-min-level = <15>; 81 - cooling-max-level = <9>; 82 80 #cooling-cells = <2>; /* min followed by max */ 83 81 }; 84 82 cpu@1 { ··· 653 655 power-domains = <&pd_gsc>; 654 656 clocks = <&clock CLK_GSCL0>; 655 657 clock-names = "gscl"; 656 - iommu = <&sysmmu_gsc0>; 658 + iommus = <&sysmmu_gsc0>; 657 659 }; 658 660 659 661 gsc_1: gsc@13e10000 { ··· 663 665 power-domains = <&pd_gsc>; 664 666 clocks = <&clock CLK_GSCL1>; 665 667 clock-names = "gscl"; 666 - iommu = <&sysmmu_gsc1>; 668 + iommus = <&sysmmu_gsc1>; 667 669 }; 668 670 669 671 gsc_2: gsc@13e20000 { ··· 673 675 power-domains = <&pd_gsc>; 674 676 clocks = <&clock CLK_GSCL2>; 675 677 clock-names = "gscl"; 676 - iommu = <&sysmmu_gsc2>; 678 + iommus = <&sysmmu_gsc2>; 677 679 }; 678 680 679 681 gsc_3: gsc@13e30000 { ··· 683 685 power-domains = <&pd_gsc>; 684 686 clocks = <&clock CLK_GSCL3>; 685 687 clock-names = "gscl"; 686 - iommu = <&sysmmu_gsc3>; 688 + iommus = <&sysmmu_gsc3>; 687 689 }; 688 690 689 691 hdmi: hdmi@14530000 {
-1
arch/arm/boot/dts/exynos5260-xyref5260.dts
··· 65 65 &mmc_0 { 66 66 status = "okay"; 67 67 broken-cd; 68 - bypass-smu; 69 68 cap-mmc-highspeed; 70 69 supports-hs200-mode; /* 200 MHz */ 71 70 card-detect-delay = <200>;
+4 -5
arch/arm/boot/dts/exynos5410.dtsi
··· 11 11 */ 12 12 13 13 #include "exynos54xx.dtsi" 14 - #include "exynos-syscon-restart.dtsi" 15 14 #include <dt-bindings/clock/exynos5410.h> 16 15 #include <dt-bindings/clock/exynos-audss-clk.h> 17 16 #include <dt-bindings/interrupt-controller/arm-gic.h> ··· 196 197 interrupt-parent = <&gic>; 197 198 ranges; 198 199 199 - pdma0: pdma@12680000 { 200 + pdma0: pdma@121a0000 { 200 201 compatible = "arm,pl330", "arm,primecell"; 201 - reg = <0x121A0000 0x1000>; 202 + reg = <0x121a0000 0x1000>; 202 203 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 203 204 clocks = <&clock CLK_PDMA0>; 204 205 clock-names = "apb_pclk"; ··· 207 208 #dma-requests = <32>; 208 209 }; 209 210 210 - pdma1: pdma@12690000 { 211 + pdma1: pdma@121b0000 { 211 212 compatible = "arm,pl330", "arm,primecell"; 212 - reg = <0x121B0000 0x1000>; 213 + reg = <0x121b0000 0x1000>; 213 214 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 214 215 clocks = <&clock CLK_PDMA1>; 215 216 clock-names = "apb_pclk";
-16
arch/arm/boot/dts/exynos5420-cpus.dtsi
··· 30 30 clock-frequency = <1800000000>; 31 31 cci-control-port = <&cci_control1>; 32 32 operating-points-v2 = <&cluster_a15_opp_table>; 33 - cooling-min-level = <0>; 34 - cooling-max-level = <11>; 35 33 #cooling-cells = <2>; /* min followed by max */ 36 34 capacity-dmips-mhz = <1024>; 37 35 }; ··· 41 43 clock-frequency = <1800000000>; 42 44 cci-control-port = <&cci_control1>; 43 45 operating-points-v2 = <&cluster_a15_opp_table>; 44 - cooling-min-level = <0>; 45 - cooling-max-level = <11>; 46 46 #cooling-cells = <2>; /* min followed by max */ 47 47 capacity-dmips-mhz = <1024>; 48 48 }; ··· 52 56 clock-frequency = <1800000000>; 53 57 cci-control-port = <&cci_control1>; 54 58 operating-points-v2 = <&cluster_a15_opp_table>; 55 - cooling-min-level = <0>; 56 - cooling-max-level = <11>; 57 59 #cooling-cells = <2>; /* min followed by max */ 58 60 capacity-dmips-mhz = <1024>; 59 61 }; ··· 63 69 clock-frequency = <1800000000>; 64 70 cci-control-port = <&cci_control1>; 65 71 operating-points-v2 = <&cluster_a15_opp_table>; 66 - cooling-min-level = <0>; 67 - cooling-max-level = <11>; 68 72 #cooling-cells = <2>; /* min followed by max */ 69 73 capacity-dmips-mhz = <1024>; 70 74 }; ··· 75 83 clock-frequency = <1000000000>; 76 84 cci-control-port = <&cci_control0>; 77 85 operating-points-v2 = <&cluster_a7_opp_table>; 78 - cooling-min-level = <0>; 79 - cooling-max-level = <7>; 80 86 #cooling-cells = <2>; /* min followed by max */ 81 87 capacity-dmips-mhz = <539>; 82 88 }; ··· 86 96 clock-frequency = <1000000000>; 87 97 cci-control-port = <&cci_control0>; 88 98 operating-points-v2 = <&cluster_a7_opp_table>; 89 - cooling-min-level = <0>; 90 - cooling-max-level = <7>; 91 99 #cooling-cells = <2>; /* min followed by max */ 92 100 capacity-dmips-mhz = <539>; 93 101 }; ··· 97 109 clock-frequency = <1000000000>; 98 110 cci-control-port = <&cci_control0>; 99 111 operating-points-v2 = <&cluster_a7_opp_table>; 100 - cooling-min-level = <0>; 101 - cooling-max-level = <7>; 102 112 #cooling-cells = <2>; /* min followed by max */ 103 113 capacity-dmips-mhz = <539>; 104 114 }; ··· 108 122 clock-frequency = <1000000000>; 109 123 cci-control-port = <&cci_control0>; 110 124 operating-points-v2 = <&cluster_a7_opp_table>; 111 - cooling-min-level = <0>; 112 - cooling-max-level = <7>; 113 125 #cooling-cells = <2>; /* min followed by max */ 114 126 capacity-dmips-mhz = <539>; 115 127 };
-16
arch/arm/boot/dts/exynos5422-cpus.dtsi
··· 29 29 clock-frequency = <1000000000>; 30 30 cci-control-port = <&cci_control0>; 31 31 operating-points-v2 = <&cluster_a7_opp_table>; 32 - cooling-min-level = <0>; 33 - cooling-max-level = <11>; 34 32 #cooling-cells = <2>; /* min followed by max */ 35 33 capacity-dmips-mhz = <539>; 36 34 }; ··· 40 42 clock-frequency = <1000000000>; 41 43 cci-control-port = <&cci_control0>; 42 44 operating-points-v2 = <&cluster_a7_opp_table>; 43 - cooling-min-level = <0>; 44 - cooling-max-level = <11>; 45 45 #cooling-cells = <2>; /* min followed by max */ 46 46 capacity-dmips-mhz = <539>; 47 47 }; ··· 51 55 clock-frequency = <1000000000>; 52 56 cci-control-port = <&cci_control0>; 53 57 operating-points-v2 = <&cluster_a7_opp_table>; 54 - cooling-min-level = <0>; 55 - cooling-max-level = <11>; 56 58 #cooling-cells = <2>; /* min followed by max */ 57 59 capacity-dmips-mhz = <539>; 58 60 }; ··· 62 68 clock-frequency = <1000000000>; 63 69 cci-control-port = <&cci_control0>; 64 70 operating-points-v2 = <&cluster_a7_opp_table>; 65 - cooling-min-level = <0>; 66 - cooling-max-level = <11>; 67 71 #cooling-cells = <2>; /* min followed by max */ 68 72 capacity-dmips-mhz = <539>; 69 73 }; ··· 74 82 clock-frequency = <1800000000>; 75 83 cci-control-port = <&cci_control1>; 76 84 operating-points-v2 = <&cluster_a15_opp_table>; 77 - cooling-min-level = <0>; 78 - cooling-max-level = <15>; 79 85 #cooling-cells = <2>; /* min followed by max */ 80 86 capacity-dmips-mhz = <1024>; 81 87 }; ··· 85 95 clock-frequency = <1800000000>; 86 96 cci-control-port = <&cci_control1>; 87 97 operating-points-v2 = <&cluster_a15_opp_table>; 88 - cooling-min-level = <0>; 89 - cooling-max-level = <15>; 90 98 #cooling-cells = <2>; /* min followed by max */ 91 99 capacity-dmips-mhz = <1024>; 92 100 }; ··· 96 108 clock-frequency = <1800000000>; 97 109 cci-control-port = <&cci_control1>; 98 110 operating-points-v2 = <&cluster_a15_opp_table>; 99 - cooling-min-level = <0>; 100 - cooling-max-level = <15>; 101 111 #cooling-cells = <2>; /* min followed by max */ 102 112 capacity-dmips-mhz = <1024>; 103 113 }; ··· 107 121 clock-frequency = <1800000000>; 108 122 cci-control-port = <&cci_control1>; 109 123 operating-points-v2 = <&cluster_a15_opp_table>; 110 - cooling-min-level = <0>; 111 - cooling-max-level = <15>; 112 124 #cooling-cells = <2>; /* min followed by max */ 113 125 capacity-dmips-mhz = <1024>; 114 126 };
+277 -269
arch/arm/boot/dts/exynos5440.dtsi
··· 26 26 tmuctrl2 = &tmuctrl_2; 27 27 }; 28 28 29 - clock: clock-controller@160000 { 30 - compatible = "samsung,exynos5440-clock"; 31 - reg = <0x160000 0x1000>; 32 - #clock-cells = <1>; 33 - }; 34 - 35 - gic: interrupt-controller@2e0000 { 36 - compatible = "arm,cortex-a15-gic"; 37 - #interrupt-cells = <3>; 38 - interrupt-controller; 39 - reg = <0x2E1000 0x1000>, 40 - <0x2E2000 0x2000>, 41 - <0x2E4000 0x2000>, 42 - <0x2E6000 0x2000>; 43 - interrupts = <GIC_PPI 9 44 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 45 - }; 46 - 47 29 cpus { 48 30 #address-cells = <1>; 49 31 #size-cells = <0>; ··· 52 70 }; 53 71 }; 54 72 55 - arm-pmu { 56 - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; 57 - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 58 - <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 59 - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 60 - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 61 - }; 62 - 63 - timer { 64 - compatible = "arm,cortex-a15-timer", 65 - "arm,armv7-timer"; 66 - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 67 - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 68 - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 70 - clock-frequency = <50000000>; 71 - }; 72 - 73 - cpufreq@160000 { 74 - compatible = "samsung,exynos5440-cpufreq"; 75 - reg = <0x160000 0x1000>; 76 - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 77 - operating-points = < 78 - /* KHz uV */ 79 - 1500000 1100000 80 - 1400000 1075000 81 - 1300000 1050000 82 - 1200000 1025000 83 - 1100000 1000000 84 - 1000000 975000 85 - 900000 950000 86 - 800000 925000 87 - >; 88 - }; 89 - 90 - serial_0: serial@b0000 { 91 - compatible = "samsung,exynos4210-uart"; 92 - reg = <0xB0000 0x1000>; 93 - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 94 - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; 95 - clock-names = "uart", "clk_uart_baud0"; 96 - }; 97 - 98 - serial_1: serial@c0000 { 99 - compatible = "samsung,exynos4210-uart"; 100 - reg = <0xC0000 0x1000>; 101 - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 102 - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; 103 - clock-names = "uart", "clk_uart_baud0"; 104 - }; 105 - 106 - spi_0: spi@d0000 { 107 - compatible = "samsung,exynos5440-spi"; 108 - reg = <0xD0000 0x100>; 109 - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 110 - #address-cells = <1>; 111 - #size-cells = <0>; 112 - samsung,spi-src-clk = <0>; 113 - num-cs = <1>; 114 - clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; 115 - clock-names = "spi", "spi_busclk0"; 116 - }; 117 - 118 - pin_ctrl: pinctrl@e0000 { 119 - compatible = "samsung,exynos5440-pinctrl"; 120 - reg = <0xE0000 0x1000>; 121 - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 122 - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 123 - <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 124 - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 125 - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 126 - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 127 - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 128 - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 129 - interrupt-controller; 130 - #interrupt-cells = <2>; 131 - #gpio-cells = <2>; 132 - 133 - fan: fan { 134 - samsung,exynos5440-pin-function = <1>; 135 - }; 136 - 137 - hdd_led0: hdd_led0 { 138 - samsung,exynos5440-pin-function = <2>; 139 - }; 140 - 141 - hdd_led1: hdd_led1 { 142 - samsung,exynos5440-pin-function = <3>; 143 - }; 144 - 145 - uart1: uart1 { 146 - samsung,exynos5440-pin-function = <4>; 147 - }; 148 - }; 149 - 150 - i2c@f0000 { 151 - compatible = "samsung,exynos5440-i2c"; 152 - reg = <0xF0000 0x1000>; 153 - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 154 - #address-cells = <1>; 155 - #size-cells = <0>; 156 - clocks = <&clock CLK_B_125>; 157 - clock-names = "i2c"; 158 - }; 159 - 160 - i2c@100000 { 161 - compatible = "samsung,exynos5440-i2c"; 162 - reg = <0x100000 0x1000>; 163 - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 164 - #address-cells = <1>; 165 - #size-cells = <0>; 166 - clocks = <&clock CLK_B_125>; 167 - clock-names = "i2c"; 168 - }; 169 - 170 - watchdog@110000 { 171 - compatible = "samsung,s3c6410-wdt"; 172 - reg = <0x110000 0x1000>; 173 - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 174 - clocks = <&clock CLK_B_125>; 175 - clock-names = "watchdog"; 176 - }; 177 - 178 - gmac: ethernet@230000 { 179 - compatible = "snps,dwmac-3.70a", "snps,dwmac"; 180 - reg = <0x00230000 0x8000>; 181 - interrupt-parent = <&gic>; 182 - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 183 - interrupt-names = "macirq"; 184 - phy-mode = "sgmii"; 185 - clocks = <&clock CLK_GMAC0>; 186 - clock-names = "stmmaceth"; 187 - }; 188 - 189 - amba { 73 + soc: soc { 74 + compatible = "simple-bus"; 190 75 #address-cells = <1>; 191 76 #size-cells = <1>; 192 - compatible = "simple-bus"; 193 - interrupt-parent = <&gic>; 194 77 ranges; 195 - }; 196 78 197 - rtc@130000 { 198 - compatible = "samsung,s3c6410-rtc"; 199 - reg = <0x130000 0x1000>; 200 - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 201 - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 202 - clocks = <&clock CLK_B_125>; 203 - clock-names = "rtc"; 204 - }; 79 + clock: clock-controller@160000 { 80 + compatible = "samsung,exynos5440-clock"; 81 + reg = <0x160000 0x1000>; 82 + #clock-cells = <1>; 83 + }; 205 84 206 - tmuctrl_0: tmuctrl@160118 { 207 - compatible = "samsung,exynos5440-tmu"; 208 - reg = <0x160118 0x230>, <0x160368 0x10>; 209 - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 210 - clocks = <&clock CLK_B_125>; 211 - clock-names = "tmu_apbif"; 212 - #include "exynos5440-tmu-sensor-conf.dtsi" 213 - }; 85 + gic: interrupt-controller@2e0000 { 86 + compatible = "arm,cortex-a15-gic"; 87 + #interrupt-cells = <3>; 88 + interrupt-controller; 89 + reg = <0x2E1000 0x1000>, 90 + <0x2E2000 0x2000>, 91 + <0x2E4000 0x2000>, 92 + <0x2E6000 0x2000>; 93 + interrupts = <GIC_PPI 9 94 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 95 + }; 214 96 215 - tmuctrl_1: tmuctrl@16011c { 216 - compatible = "samsung,exynos5440-tmu"; 217 - reg = <0x16011C 0x230>, <0x160368 0x10>; 218 - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 219 - clocks = <&clock CLK_B_125>; 220 - clock-names = "tmu_apbif"; 221 - #include "exynos5440-tmu-sensor-conf.dtsi" 222 - }; 223 97 224 - tmuctrl_2: tmuctrl@160120 { 225 - compatible = "samsung,exynos5440-tmu"; 226 - reg = <0x160120 0x230>, <0x160368 0x10>; 227 - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 228 - clocks = <&clock CLK_B_125>; 229 - clock-names = "tmu_apbif"; 230 - #include "exynos5440-tmu-sensor-conf.dtsi" 98 + arm-pmu { 99 + compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; 100 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 101 + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 102 + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 103 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 104 + }; 105 + 106 + timer { 107 + compatible = "arm,cortex-a15-timer", 108 + "arm,armv7-timer"; 109 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 110 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 111 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 112 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 113 + clock-frequency = <50000000>; 114 + }; 115 + 116 + cpufreq@160000 { 117 + compatible = "samsung,exynos5440-cpufreq"; 118 + reg = <0x160000 0x1000>; 119 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 120 + operating-points = < 121 + /* KHz uV */ 122 + 1500000 1100000 123 + 1400000 1075000 124 + 1300000 1050000 125 + 1200000 1025000 126 + 1100000 1000000 127 + 1000000 975000 128 + 900000 950000 129 + 800000 925000 130 + >; 131 + }; 132 + 133 + serial_0: serial@b0000 { 134 + compatible = "samsung,exynos4210-uart"; 135 + reg = <0xB0000 0x1000>; 136 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 137 + clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; 138 + clock-names = "uart", "clk_uart_baud0"; 139 + }; 140 + 141 + serial_1: serial@c0000 { 142 + compatible = "samsung,exynos4210-uart"; 143 + reg = <0xC0000 0x1000>; 144 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 145 + clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; 146 + clock-names = "uart", "clk_uart_baud0"; 147 + }; 148 + 149 + spi_0: spi@d0000 { 150 + compatible = "samsung,exynos5440-spi"; 151 + reg = <0xD0000 0x100>; 152 + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 153 + #address-cells = <1>; 154 + #size-cells = <0>; 155 + samsung,spi-src-clk = <0>; 156 + num-cs = <1>; 157 + clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; 158 + clock-names = "spi", "spi_busclk0"; 159 + }; 160 + 161 + pin_ctrl: pinctrl@e0000 { 162 + compatible = "samsung,exynos5440-pinctrl"; 163 + reg = <0xE0000 0x1000>; 164 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 165 + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 166 + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 167 + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 168 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 169 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 170 + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 171 + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 172 + interrupt-controller; 173 + #interrupt-cells = <2>; 174 + #gpio-cells = <2>; 175 + 176 + fan: fan { 177 + samsung,exynos5440-pin-function = <1>; 178 + }; 179 + 180 + hdd_led0: hdd_led0 { 181 + samsung,exynos5440-pin-function = <2>; 182 + }; 183 + 184 + hdd_led1: hdd_led1 { 185 + samsung,exynos5440-pin-function = <3>; 186 + }; 187 + 188 + uart1: uart1 { 189 + samsung,exynos5440-pin-function = <4>; 190 + }; 191 + }; 192 + 193 + i2c@f0000 { 194 + compatible = "samsung,exynos5440-i2c"; 195 + reg = <0xF0000 0x1000>; 196 + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 197 + #address-cells = <1>; 198 + #size-cells = <0>; 199 + clocks = <&clock CLK_B_125>; 200 + clock-names = "i2c"; 201 + }; 202 + 203 + i2c@100000 { 204 + compatible = "samsung,exynos5440-i2c"; 205 + reg = <0x100000 0x1000>; 206 + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 207 + #address-cells = <1>; 208 + #size-cells = <0>; 209 + clocks = <&clock CLK_B_125>; 210 + clock-names = "i2c"; 211 + }; 212 + 213 + watchdog@110000 { 214 + compatible = "samsung,s3c6410-wdt"; 215 + reg = <0x110000 0x1000>; 216 + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 217 + clocks = <&clock CLK_B_125>; 218 + clock-names = "watchdog"; 219 + }; 220 + 221 + gmac: ethernet@230000 { 222 + compatible = "snps,dwmac-3.70a", "snps,dwmac"; 223 + reg = <0x00230000 0x8000>; 224 + interrupt-parent = <&gic>; 225 + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 226 + interrupt-names = "macirq"; 227 + phy-mode = "sgmii"; 228 + clocks = <&clock CLK_GMAC0>; 229 + clock-names = "stmmaceth"; 230 + }; 231 + 232 + amba { 233 + #address-cells = <1>; 234 + #size-cells = <1>; 235 + compatible = "simple-bus"; 236 + interrupt-parent = <&gic>; 237 + ranges; 238 + }; 239 + 240 + rtc@130000 { 241 + compatible = "samsung,s3c6410-rtc"; 242 + reg = <0x130000 0x1000>; 243 + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 244 + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 245 + clocks = <&clock CLK_B_125>; 246 + clock-names = "rtc"; 247 + }; 248 + 249 + tmuctrl_0: tmuctrl@160118 { 250 + compatible = "samsung,exynos5440-tmu"; 251 + reg = <0x160118 0x230>, <0x160368 0x10>; 252 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 253 + clocks = <&clock CLK_B_125>; 254 + clock-names = "tmu_apbif"; 255 + #include "exynos5440-tmu-sensor-conf.dtsi" 256 + }; 257 + 258 + tmuctrl_1: tmuctrl@16011c { 259 + compatible = "samsung,exynos5440-tmu"; 260 + reg = <0x16011C 0x230>, <0x160368 0x10>; 261 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 262 + clocks = <&clock CLK_B_125>; 263 + clock-names = "tmu_apbif"; 264 + #include "exynos5440-tmu-sensor-conf.dtsi" 265 + }; 266 + 267 + tmuctrl_2: tmuctrl@160120 { 268 + compatible = "samsung,exynos5440-tmu"; 269 + reg = <0x160120 0x230>, <0x160368 0x10>; 270 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 271 + clocks = <&clock CLK_B_125>; 272 + clock-names = "tmu_apbif"; 273 + #include "exynos5440-tmu-sensor-conf.dtsi" 274 + }; 275 + 276 + sata@210000 { 277 + compatible = "snps,exynos5440-ahci"; 278 + reg = <0x210000 0x10000>; 279 + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 280 + clocks = <&clock CLK_SATA>; 281 + clock-names = "sata"; 282 + }; 283 + 284 + ohci@220000 { 285 + compatible = "samsung,exynos5440-ohci"; 286 + reg = <0x220000 0x1000>; 287 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 288 + clocks = <&clock CLK_USB>; 289 + clock-names = "usbhost"; 290 + }; 291 + 292 + ehci@221000 { 293 + compatible = "samsung,exynos5440-ehci"; 294 + reg = <0x221000 0x1000>; 295 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 296 + clocks = <&clock CLK_USB>; 297 + clock-names = "usbhost"; 298 + }; 299 + 300 + pcie_phy0: pcie-phy@270000 { 301 + #phy-cells = <0>; 302 + compatible = "samsung,exynos5440-pcie-phy"; 303 + reg = <0x270000 0x1000>, <0x271000 0x40>; 304 + }; 305 + 306 + pcie_phy1: pcie-phy@272000 { 307 + #phy-cells = <0>; 308 + compatible = "samsung,exynos5440-pcie-phy"; 309 + reg = <0x272000 0x1000>, <0x271040 0x40>; 310 + }; 311 + 312 + pcie_0: pcie@290000 { 313 + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; 314 + reg = <0x290000 0x1000>, <0x40000000 0x1000>; 315 + reg-names = "elbi", "config"; 316 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 317 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 318 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 319 + clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; 320 + clock-names = "pcie", "pcie_bus"; 321 + #address-cells = <3>; 322 + #size-cells = <2>; 323 + device_type = "pci"; 324 + phys = <&pcie_phy0>; 325 + ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ 326 + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ 327 + bus-range = <0x00 0xff>; 328 + #interrupt-cells = <1>; 329 + interrupt-map-mask = <0 0 0 0>; 330 + interrupt-map = <0x0 0 &gic 53>; 331 + num-lanes = <4>; 332 + status = "disabled"; 333 + }; 334 + 335 + pcie_1: pcie@2a0000 { 336 + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; 337 + reg = <0x2a0000 0x1000>, <0x60000000 0x1000>; 338 + reg-names = "elbi", "config"; 339 + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 340 + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 341 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 342 + clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; 343 + clock-names = "pcie", "pcie_bus"; 344 + #address-cells = <3>; 345 + #size-cells = <2>; 346 + device_type = "pci"; 347 + phys = <&pcie_phy1>; 348 + ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ 349 + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ 350 + bus-range = <0x00 0xff>; 351 + #interrupt-cells = <1>; 352 + interrupt-map-mask = <0 0 0 0>; 353 + interrupt-map = <0x0 0 &gic 56>; 354 + num-lanes = <4>; 355 + status = "disabled"; 356 + }; 231 357 }; 232 358 233 359 thermal-zones { ··· 351 261 thermal-sensors = <&tmuctrl_2>; 352 262 #include "exynos5440-trip-points.dtsi" 353 263 }; 354 - }; 355 - 356 - sata@210000 { 357 - compatible = "snps,exynos5440-ahci"; 358 - reg = <0x210000 0x10000>; 359 - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 360 - clocks = <&clock CLK_SATA>; 361 - clock-names = "sata"; 362 - }; 363 - 364 - ohci@220000 { 365 - compatible = "samsung,exynos5440-ohci"; 366 - reg = <0x220000 0x1000>; 367 - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 368 - clocks = <&clock CLK_USB>; 369 - clock-names = "usbhost"; 370 - }; 371 - 372 - ehci@221000 { 373 - compatible = "samsung,exynos5440-ehci"; 374 - reg = <0x221000 0x1000>; 375 - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 376 - clocks = <&clock CLK_USB>; 377 - clock-names = "usbhost"; 378 - }; 379 - 380 - pcie_phy0: pcie-phy@270000 { 381 - #phy-cells = <0>; 382 - compatible = "samsung,exynos5440-pcie-phy"; 383 - reg = <0x270000 0x1000>, <0x271000 0x40>; 384 - }; 385 - 386 - pcie_phy1: pcie-phy@272000 { 387 - #phy-cells = <0>; 388 - compatible = "samsung,exynos5440-pcie-phy"; 389 - reg = <0x272000 0x1000>, <0x271040 0x40>; 390 - }; 391 - 392 - pcie_0: pcie@290000 { 393 - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; 394 - reg = <0x290000 0x1000>, <0x40000000 0x1000>; 395 - reg-names = "elbi", "config"; 396 - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 397 - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 398 - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 399 - clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; 400 - clock-names = "pcie", "pcie_bus"; 401 - #address-cells = <3>; 402 - #size-cells = <2>; 403 - device_type = "pci"; 404 - phys = <&pcie_phy0>; 405 - ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ 406 - 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ 407 - bus-range = <0x00 0xff>; 408 - #interrupt-cells = <1>; 409 - interrupt-map-mask = <0 0 0 0>; 410 - interrupt-map = <0x0 0 &gic 53>; 411 - num-lanes = <4>; 412 - status = "disabled"; 413 - }; 414 - 415 - pcie_1: pcie@2a0000 { 416 - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; 417 - reg = <0x2a0000 0x1000>, <0x60000000 0x1000>; 418 - reg-names = "elbi", "config"; 419 - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 420 - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 421 - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 422 - clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; 423 - clock-names = "pcie", "pcie_bus"; 424 - #address-cells = <3>; 425 - #size-cells = <2>; 426 - device_type = "pci"; 427 - phys = <&pcie_phy1>; 428 - ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ 429 - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ 430 - bus-range = <0x00 0xff>; 431 - #interrupt-cells = <1>; 432 - interrupt-map-mask = <0 0 0 0>; 433 - interrupt-map = <0x0 0 &gic 56>; 434 - num-lanes = <4>; 435 - status = "disabled"; 436 264 }; 437 265 };
+1 -4
arch/arm/boot/dts/exynos5800-peach-pi.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * Google Peach Pi Rev 10+ board device tree source 3 4 * 4 5 * Copyright (c) 2014 Google, Inc 5 - * 6 - * This program is free software; you can redistribute it and/or modify 7 - * it under the terms of the GNU General Public License version 2 as 8 - * published by the Free Software Foundation. 9 6 */ 10 7 11 8 /dts-v1/;
+1 -4
arch/arm/boot/dts/exynos5800.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * SAMSUNG EXYNOS5800 SoC device tree source 3 4 * ··· 8 7 * SAMSUNG EXYNOS5800 SoC device nodes are listed in this file. 9 8 * EXYNOS5800 based board files can include this file and provide 10 9 * values for board specfic bindings. 11 - * 12 - * This program is free software; you can redistribute it and/or modify 13 - * it under the terms of the GNU General Public License version 2 as 14 - * published by the Free Software Foundation. 15 10 */ 16 11 17 12 #include "exynos5420.dtsi"
-68
arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Timings and Geometry for Samsung K3PE0E000B memory part 4 - */ 5 - 6 - / { 7 - samsung_K3PE0E000B: lpddr2 { 8 - compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4"; 9 - density = <4096>; 10 - io-width = <32>; 11 - 12 - tRPab-min-tck = <3>; 13 - tRCD-min-tck = <3>; 14 - tWR-min-tck = <3>; 15 - tRASmin-min-tck = <3>; 16 - tRRD-min-tck = <2>; 17 - tWTR-min-tck = <2>; 18 - tXP-min-tck = <2>; 19 - tRTP-min-tck = <2>; 20 - tCKE-min-tck = <3>; 21 - tCKESR-min-tck = <3>; 22 - tFAW-min-tck = <8>; 23 - 24 - timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 { 25 - compatible = "jedec,lpddr2-timings"; 26 - min-freq = <10000000>; 27 - max-freq = <533333333>; 28 - tRPab = <21000>; 29 - tRCD = <18000>; 30 - tWR = <15000>; 31 - tRAS-min = <42000>; 32 - tRRD = <10000>; 33 - tWTR = <7500>; 34 - tXP = <7500>; 35 - tRTP = <7500>; 36 - tCKESR = <15000>; 37 - tDQSCK-max = <5500>; 38 - tFAW = <50000>; 39 - tZQCS = <90000>; 40 - tZQCL = <360000>; 41 - tZQinit = <1000000>; 42 - tRAS-max-ns = <70000>; 43 - tDQSCK-max-derated = <6000>; 44 - }; 45 - 46 - timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 { 47 - compatible = "jedec,lpddr2-timings"; 48 - min-freq = <10000000>; 49 - max-freq = <266666666>; 50 - tRPab = <21000>; 51 - tRCD = <18000>; 52 - tWR = <15000>; 53 - tRAS-min = <42000>; 54 - tRRD = <10000>; 55 - tWTR = <7500>; 56 - tXP = <7500>; 57 - tRTP = <7500>; 58 - tCKESR = <15000>; 59 - tDQSCK-max = <5500>; 60 - tFAW = <50000>; 61 - tZQCS = <90000>; 62 - tZQCL = <360000>; 63 - tZQinit = <1000000>; 64 - tRAS-max-ns = <70000>; 65 - tDQSCK-max-derated = <6000>; 66 - }; 67 - }; 68 - };