tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/dp: switch drm_dp_downstream_*() helpers to struct drm_edid

Prefer struct drm_edid where possible. With limited users for the
drm_dp_downstream_*() helpers, this is fairly straightforward.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231004162149.2802113-1-jani.nikula@intel.com

Jani Nikula e2272bfb 9586e240

+31 -33
+21 -18
drivers/gpu/drm/display/drm_dp_helper.c
··· 746 746 } 747 747 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status); 748 748 749 - static bool is_edid_digital_input_dp(const struct edid *edid) 749 + static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid) 750 750 { 751 + /* FIXME: get rid of drm_edid_raw() */ 752 + const struct edid *edid = drm_edid_raw(drm_edid); 753 + 751 754 return edid && edid->revision >= 4 && 752 755 edid->input & DRM_EDID_INPUT_DIGITAL && 753 756 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; ··· 782 779 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? 783 780 * @dpcd: DisplayPort configuration data 784 781 * @port_cap: port capabilities 785 - * @edid: EDID 782 + * @drm_edid: EDID 786 783 * 787 784 * Returns: whether the downstream facing port is TMDS (HDMI/DVI). 788 785 */ 789 786 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 790 787 const u8 port_cap[4], 791 - const struct edid *edid) 788 + const struct drm_edid *drm_edid) 792 789 { 793 790 if (dpcd[DP_DPCD_REV] < 0x11) { 794 791 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { ··· 801 798 802 799 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 803 800 case DP_DS_PORT_TYPE_DP_DUALMODE: 804 - if (is_edid_digital_input_dp(edid)) 801 + if (is_edid_digital_input_dp(drm_edid)) 805 802 return false; 806 803 fallthrough; 807 804 case DP_DS_PORT_TYPE_DVI: ··· 1039 1036 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock 1040 1037 * @dpcd: DisplayPort configuration data 1041 1038 * @port_cap: port capabilities 1042 - * @edid: EDID 1039 + * @drm_edid: EDID 1043 1040 * 1044 1041 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success, 1045 1042 * or 0 if max TMDS clock not defined 1046 1043 */ 1047 1044 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1048 1045 const u8 port_cap[4], 1049 - const struct edid *edid) 1046 + const struct drm_edid *drm_edid) 1050 1047 { 1051 1048 if (!drm_dp_is_branch(dpcd)) 1052 1049 return 0; ··· 1062 1059 1063 1060 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1064 1061 case DP_DS_PORT_TYPE_DP_DUALMODE: 1065 - if (is_edid_digital_input_dp(edid)) 1062 + if (is_edid_digital_input_dp(drm_edid)) 1066 1063 return 0; 1067 1064 /* 1068 1065 * It's left up to the driver to check the ··· 1104 1101 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock 1105 1102 * @dpcd: DisplayPort configuration data 1106 1103 * @port_cap: port capabilities 1107 - * @edid: EDID 1104 + * @drm_edid: EDID 1108 1105 * 1109 1106 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success, 1110 1107 * or 0 if max TMDS clock not defined 1111 1108 */ 1112 1109 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1113 1110 const u8 port_cap[4], 1114 - const struct edid *edid) 1111 + const struct drm_edid *drm_edid) 1115 1112 { 1116 1113 if (!drm_dp_is_branch(dpcd)) 1117 1114 return 0; ··· 1127 1124 1128 1125 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1129 1126 case DP_DS_PORT_TYPE_DP_DUALMODE: 1130 - if (is_edid_digital_input_dp(edid)) 1127 + if (is_edid_digital_input_dp(drm_edid)) 1131 1128 return 0; 1132 1129 fallthrough; 1133 1130 case DP_DS_PORT_TYPE_DVI: ··· 1148 1145 * bits per component 1149 1146 * @dpcd: DisplayPort configuration data 1150 1147 * @port_cap: downstream facing port capabilities 1151 - * @edid: EDID 1148 + * @drm_edid: EDID 1152 1149 * 1153 1150 * Returns: Max bpc on success or 0 if max bpc not defined 1154 1151 */ 1155 1152 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1156 1153 const u8 port_cap[4], 1157 - const struct edid *edid) 1154 + const struct drm_edid *drm_edid) 1158 1155 { 1159 1156 if (!drm_dp_is_branch(dpcd)) 1160 1157 return 0; ··· 1172 1169 case DP_DS_PORT_TYPE_DP: 1173 1170 return 0; 1174 1171 case DP_DS_PORT_TYPE_DP_DUALMODE: 1175 - if (is_edid_digital_input_dp(edid)) 1172 + if (is_edid_digital_input_dp(drm_edid)) 1176 1173 return 0; 1177 1174 fallthrough; 1178 1175 case DP_DS_PORT_TYPE_HDMI: ··· 1365 1362 * @m: pointer for debugfs file 1366 1363 * @dpcd: DisplayPort configuration data 1367 1364 * @port_cap: port capabilities 1368 - * @edid: EDID 1365 + * @drm_edid: EDID 1369 1366 * @aux: DisplayPort AUX channel 1370 1367 * 1371 1368 */ 1372 1369 void drm_dp_downstream_debug(struct seq_file *m, 1373 1370 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1374 1371 const u8 port_cap[4], 1375 - const struct edid *edid, 1372 + const struct drm_edid *drm_edid, 1376 1373 struct drm_dp_aux *aux) 1377 1374 { 1378 1375 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & ··· 1435 1432 if (clk > 0) 1436 1433 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 1437 1434 1438 - clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid); 1435 + clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid); 1439 1436 if (clk > 0) 1440 1437 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 1441 1438 1442 - clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid); 1439 + clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid); 1443 1440 if (clk > 0) 1444 1441 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk); 1445 1442 1446 - bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid); 1443 + bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid); 1447 1444 1448 1445 if (bpc > 0) 1449 1446 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
+1 -2
drivers/gpu/drm/i915/display/intel_display_debugfs.c
··· 233 233 { 234 234 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 235 235 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 236 - const struct edid *edid = drm_edid_raw(connector->detect_edid); 237 236 238 237 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 239 238 seq_printf(m, "\taudio support: %s\n", 240 239 str_yes_no(connector->base.display_info.has_audio)); 241 240 242 241 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, 243 - edid, &intel_dp->aux); 242 + connector->detect_edid, &intel_dp->aux); 244 243 } 245 244 246 245 static void intel_dp_mst_info(struct seq_file *m,
+3 -7
drivers/gpu/drm/i915/display/intel_dp.c
··· 4708 4708 { 4709 4709 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4710 4710 struct intel_connector *connector = intel_dp->attached_connector; 4711 - const struct edid *edid; 4712 - 4713 - /* FIXME: Get rid of drm_edid_raw() */ 4714 - edid = drm_edid_raw(drm_edid); 4715 4711 4716 4712 intel_dp->dfp.max_bpc = 4717 4713 drm_dp_downstream_max_bpc(intel_dp->dpcd, 4718 - intel_dp->downstream_ports, edid); 4714 + intel_dp->downstream_ports, drm_edid); 4719 4715 4720 4716 intel_dp->dfp.max_dotclock = 4721 4717 drm_dp_downstream_max_dotclock(intel_dp->dpcd, ··· 4720 4724 intel_dp->dfp.min_tmds_clock = 4721 4725 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 4722 4726 intel_dp->downstream_ports, 4723 - edid); 4727 + drm_edid); 4724 4728 intel_dp->dfp.max_tmds_clock = 4725 4729 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 4726 4730 intel_dp->downstream_ports, 4727 - edid); 4731 + drm_edid); 4728 4732 4729 4733 intel_dp->dfp.pcon_max_frl_bw = 4730 4734 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
+6 -6
include/drm/display/drm_dp_helper.h
··· 272 272 }; 273 273 274 274 struct cec_adapter; 275 - struct edid; 276 275 struct drm_connector; 276 + struct drm_edid; 277 277 278 278 /** 279 279 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX ··· 507 507 const u8 port_cap[4], u8 type); 508 508 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 509 509 const u8 port_cap[4], 510 - const struct edid *edid); 510 + const struct drm_edid *drm_edid); 511 511 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 512 512 const u8 port_cap[4]); 513 513 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 514 514 const u8 port_cap[4], 515 - const struct edid *edid); 515 + const struct drm_edid *drm_edid); 516 516 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 517 517 const u8 port_cap[4], 518 - const struct edid *edid); 518 + const struct drm_edid *drm_edid); 519 519 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 520 520 const u8 port_cap[4], 521 - const struct edid *edid); 521 + const struct drm_edid *drm_edid); 522 522 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 523 523 const u8 port_cap[4]); 524 524 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], ··· 530 530 void drm_dp_downstream_debug(struct seq_file *m, 531 531 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 532 532 const u8 port_cap[4], 533 - const struct edid *edid, 533 + const struct drm_edid *drm_edid, 534 534 struct drm_dp_aux *aux); 535 535 enum drm_mode_subconnector 536 536 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],