Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch 'mlx4'

Amir Vadai says:

====================
net/mlx4: Mellanox driver update 07-11-2013

This patchset contains some enhancements and bug fixes for the mlx4_* drivers.
Patchset was applied and tested against commit: "9bb8ca8 virtio-net: switch to
use XPS to choose txq"
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

+383 -228
-6
drivers/infiniband/hw/mlx4/main.c
··· 526 526 if (IS_ERR(mailbox)) 527 527 return 0; 528 528 529 - memset(mailbox->buf, 0, 256); 530 529 memcpy(mailbox->buf, props->node_desc, 64); 531 530 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 532 531 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); ··· 545 546 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 546 547 if (IS_ERR(mailbox)) 547 548 return PTR_ERR(mailbox); 548 - 549 - memset(mailbox->buf, 0, 256); 550 549 551 550 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 552 551 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; ··· 876 879 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 877 880 struct mlx4_cmd_mailbox *mailbox; 878 881 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 879 - size_t rule_size = sizeof(struct mlx4_net_trans_rule_hw_ctrl) + 880 - (sizeof(struct _rule_hw) * flow_attr->num_of_specs); 881 882 882 883 static const u16 __mlx4_domain[] = { 883 884 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, ··· 900 905 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 901 906 if (IS_ERR(mailbox)) 902 907 return PTR_ERR(mailbox); 903 - memset(mailbox->buf, 0, rule_size); 904 908 ctrl = mailbox->buf; 905 909 906 910 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
+16 -20
drivers/net/ethernet/mellanox/mlx4/cmd.c
··· 1539 1539 return ret; 1540 1540 } 1541 1541 1542 - static int calculate_transition(u16 oper_vlan, u16 admin_vlan) 1543 - { 1544 - return (2 * (oper_vlan == MLX4_VGT) + (admin_vlan == MLX4_VGT)); 1545 - } 1546 - 1547 1542 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv, 1548 1543 int slave, int port) 1549 1544 { ··· 1548 1553 struct mlx4_dev *dev = &(priv->dev); 1549 1554 int err; 1550 1555 int admin_vlan_ix = NO_INDX; 1551 - enum mlx4_vlan_transition vlan_trans; 1552 1556 1553 1557 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 1554 1558 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; ··· 1557 1563 vp_oper->state.link_state == vp_admin->link_state) 1558 1564 return 0; 1559 1565 1560 - vlan_trans = calculate_transition(vp_oper->state.default_vlan, 1561 - vp_admin->default_vlan); 1562 - 1563 1566 if (!(priv->mfunc.master.slave_state[slave].active && 1564 - dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP && 1565 - vlan_trans == MLX4_VLAN_TRANSITION_VST_VST)) { 1567 + dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) { 1566 1568 /* even if the UPDATE_QP command isn't supported, we still want 1567 1569 * to set this VF link according to the admin directive 1568 1570 */ ··· 1576 1586 return -ENOMEM; 1577 1587 1578 1588 if (vp_oper->state.default_vlan != vp_admin->default_vlan) { 1579 - err = __mlx4_register_vlan(&priv->dev, port, 1580 - vp_admin->default_vlan, 1581 - &admin_vlan_ix); 1582 - if (err) { 1583 - kfree(work); 1584 - mlx4_warn((&priv->dev), 1585 - "No vlan resources slave %d, port %d\n", 1586 - slave, port); 1587 - return err; 1589 + if (MLX4_VGT != vp_admin->default_vlan) { 1590 + err = __mlx4_register_vlan(&priv->dev, port, 1591 + vp_admin->default_vlan, 1592 + &admin_vlan_ix); 1593 + if (err) { 1594 + kfree(work); 1595 + mlx4_warn((&priv->dev), 1596 + "No vlan resources slave %d, port %d\n", 1597 + slave, port); 1598 + return err; 1599 + } 1600 + } else { 1601 + admin_vlan_ix = NO_INDX; 1588 1602 } 1589 1603 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN; 1590 1604 mlx4_dbg((&(priv->dev)), ··· 2192 2198 kfree(mailbox); 2193 2199 return ERR_PTR(-ENOMEM); 2194 2200 } 2201 + 2202 + memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); 2195 2203 2196 2204 return mailbox; 2197 2205 }
-6
drivers/net/ethernet/mellanox/mlx4/cq.c
··· 128 128 return PTR_ERR(mailbox); 129 129 130 130 cq_context = mailbox->buf; 131 - memset(cq_context, 0, sizeof *cq_context); 132 - 133 131 cq_context->cq_max_count = cpu_to_be16(count); 134 132 cq_context->cq_period = cpu_to_be16(period); 135 133 ··· 151 153 return PTR_ERR(mailbox); 152 154 153 155 cq_context = mailbox->buf; 154 - memset(cq_context, 0, sizeof *cq_context); 155 - 156 156 cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24); 157 157 cq_context->log_page_size = mtt->page_shift - 12; 158 158 mtt_addr = mlx4_mtt_addr(dev, mtt); ··· 270 274 } 271 275 272 276 cq_context = mailbox->buf; 273 - memset(cq_context, 0, sizeof *cq_context); 274 - 275 277 cq_context->flags = cpu_to_be32(!!collapsed << 18); 276 278 if (timestamp_en) 277 279 cq_context->flags |= cpu_to_be32(1 << 19);
+36 -9
drivers/net/ethernet/mellanox/mlx4/en_cq.c
··· 44 44 45 45 46 46 int mlx4_en_create_cq(struct mlx4_en_priv *priv, 47 - struct mlx4_en_cq *cq, 48 - int entries, int ring, enum cq_type mode) 47 + struct mlx4_en_cq **pcq, 48 + int entries, int ring, enum cq_type mode, 49 + int node) 49 50 { 50 51 struct mlx4_en_dev *mdev = priv->mdev; 52 + struct mlx4_en_cq *cq; 51 53 int err; 54 + 55 + cq = kzalloc_node(sizeof(*cq), GFP_KERNEL, node); 56 + if (!cq) { 57 + cq = kzalloc(sizeof(*cq), GFP_KERNEL); 58 + if (!cq) { 59 + en_err(priv, "Failed to allocate CQ structure\n"); 60 + return -ENOMEM; 61 + } 62 + } 52 63 53 64 cq->size = entries; 54 65 cq->buf_size = cq->size * mdev->dev->caps.cqe_size; ··· 68 57 cq->is_tx = mode; 69 58 spin_lock_init(&cq->lock); 70 59 60 + /* Allocate HW buffers on provided NUMA node. 61 + * dev->numa_node is used in mtt range allocation flow. 62 + */ 63 + set_dev_node(&mdev->dev->pdev->dev, node); 71 64 err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres, 72 65 cq->buf_size, 2 * PAGE_SIZE); 66 + set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); 73 67 if (err) 74 - return err; 68 + goto err_cq; 75 69 76 70 err = mlx4_en_map_buffer(&cq->wqres.buf); 77 71 if (err) 78 - mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size); 79 - else 80 - cq->buf = (struct mlx4_cqe *) cq->wqres.buf.direct.buf; 72 + goto err_res; 81 73 74 + cq->buf = (struct mlx4_cqe *)cq->wqres.buf.direct.buf; 75 + *pcq = cq; 76 + 77 + return 0; 78 + 79 + err_res: 80 + mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size); 81 + err_cq: 82 + kfree(cq); 83 + *pcq = NULL; 82 84 return err; 83 85 } 84 86 ··· 141 117 struct mlx4_en_cq *rx_cq; 142 118 143 119 cq_idx = cq_idx % priv->rx_ring_num; 144 - rx_cq = &priv->rx_cq[cq_idx]; 120 + rx_cq = priv->rx_cq[cq_idx]; 145 121 cq->vector = rx_cq->vector; 146 122 } 147 123 148 124 if (!cq->is_tx) 149 - cq->size = priv->rx_ring[cq->ring].actual_size; 125 + cq->size = priv->rx_ring[cq->ring]->actual_size; 150 126 151 127 if ((cq->is_tx && priv->hwtstamp_config.tx_type) || 152 128 (!cq->is_tx && priv->hwtstamp_config.rx_filter)) ··· 170 146 return 0; 171 147 } 172 148 173 - void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq) 149 + void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq) 174 150 { 175 151 struct mlx4_en_dev *mdev = priv->mdev; 152 + struct mlx4_en_cq *cq = *pcq; 176 153 177 154 mlx4_en_unmap_buffer(&cq->wqres.buf); 178 155 mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size); ··· 182 157 cq->vector = 0; 183 158 cq->buf_size = 0; 184 159 cq->buf = NULL; 160 + kfree(cq); 161 + *pcq = NULL; 185 162 } 186 163 187 164 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
+18 -18
drivers/net/ethernet/mellanox/mlx4/en_ethtool.c
··· 51 51 int err = 0; 52 52 53 53 for (i = 0; i < priv->tx_ring_num; i++) { 54 - priv->tx_cq[i].moder_cnt = priv->tx_frames; 55 - priv->tx_cq[i].moder_time = priv->tx_usecs; 54 + priv->tx_cq[i]->moder_cnt = priv->tx_frames; 55 + priv->tx_cq[i]->moder_time = priv->tx_usecs; 56 56 if (priv->port_up) { 57 - err = mlx4_en_set_cq_moder(priv, &priv->tx_cq[i]); 57 + err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]); 58 58 if (err) 59 59 return err; 60 60 } ··· 64 64 return 0; 65 65 66 66 for (i = 0; i < priv->rx_ring_num; i++) { 67 - priv->rx_cq[i].moder_cnt = priv->rx_frames; 68 - priv->rx_cq[i].moder_time = priv->rx_usecs; 67 + priv->rx_cq[i]->moder_cnt = priv->rx_frames; 68 + priv->rx_cq[i]->moder_time = priv->rx_usecs; 69 69 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; 70 70 if (priv->port_up) { 71 - err = mlx4_en_set_cq_moder(priv, &priv->rx_cq[i]); 71 + err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]); 72 72 if (err) 73 73 return err; 74 74 } ··· 274 274 } 275 275 } 276 276 for (i = 0; i < priv->tx_ring_num; i++) { 277 - data[index++] = priv->tx_ring[i].packets; 278 - data[index++] = priv->tx_ring[i].bytes; 277 + data[index++] = priv->tx_ring[i]->packets; 278 + data[index++] = priv->tx_ring[i]->bytes; 279 279 } 280 280 for (i = 0; i < priv->rx_ring_num; i++) { 281 - data[index++] = priv->rx_ring[i].packets; 282 - data[index++] = priv->rx_ring[i].bytes; 281 + data[index++] = priv->rx_ring[i]->packets; 282 + data[index++] = priv->rx_ring[i]->bytes; 283 283 #ifdef CONFIG_NET_RX_BUSY_POLL 284 - data[index++] = priv->rx_ring[i].yields; 285 - data[index++] = priv->rx_ring[i].misses; 286 - data[index++] = priv->rx_ring[i].cleaned; 284 + data[index++] = priv->rx_ring[i]->yields; 285 + data[index++] = priv->rx_ring[i]->misses; 286 + data[index++] = priv->rx_ring[i]->cleaned; 287 287 #endif 288 288 } 289 289 spin_unlock_bh(&priv->stats_lock); ··· 510 510 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE); 511 511 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE); 512 512 513 - if (rx_size == (priv->port_up ? priv->rx_ring[0].actual_size : 514 - priv->rx_ring[0].size) && 515 - tx_size == priv->tx_ring[0].size) 513 + if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size : 514 + priv->rx_ring[0]->size) && 515 + tx_size == priv->tx_ring[0]->size) 516 516 return 0; 517 517 518 518 mutex_lock(&mdev->state_lock); ··· 553 553 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; 554 554 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; 555 555 param->rx_pending = priv->port_up ? 556 - priv->rx_ring[0].actual_size : priv->rx_ring[0].size; 557 - param->tx_pending = priv->tx_ring[0].size; 556 + priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size; 557 + param->tx_pending = priv->tx_ring[0]->size; 558 558 } 559 559 560 560 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
+92 -52
drivers/net/ethernet/mellanox/mlx4/en_netdev.c
··· 75 75 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); 76 76 struct net_device *dev = cq->dev; 77 77 struct mlx4_en_priv *priv = netdev_priv(dev); 78 - struct mlx4_en_rx_ring *rx_ring = &priv->rx_ring[cq->ring]; 78 + struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 79 79 int done; 80 80 81 81 if (!priv->port_up) ··· 102 102 struct list_head next; 103 103 struct work_struct work; 104 104 105 + u8 ip_proto; 105 106 __be32 src_ip; 106 107 __be32 dst_ip; 107 108 __be16 src_port; ··· 121 120 122 121 static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv); 123 122 123 + static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto) 124 + { 125 + switch (ip_proto) { 126 + case IPPROTO_UDP: 127 + return MLX4_NET_TRANS_RULE_ID_UDP; 128 + case IPPROTO_TCP: 129 + return MLX4_NET_TRANS_RULE_ID_TCP; 130 + default: 131 + return -EPROTONOSUPPORT; 132 + } 133 + }; 134 + 124 135 static void mlx4_en_filter_work(struct work_struct *work) 125 136 { 126 137 struct mlx4_en_filter *filter = container_of(work, 127 138 struct mlx4_en_filter, 128 139 work); 129 140 struct mlx4_en_priv *priv = filter->priv; 130 - struct mlx4_spec_list spec_tcp = { 131 - .id = MLX4_NET_TRANS_RULE_ID_TCP, 141 + struct mlx4_spec_list spec_tcp_udp = { 142 + .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto), 132 143 { 133 144 .tcp_udp = { 134 145 .dst_port = filter->dst_port, ··· 176 163 int rc; 177 164 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); 178 165 166 + if (spec_tcp_udp.id < 0) { 167 + en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n", 168 + filter->ip_proto); 169 + goto ignore; 170 + } 179 171 list_add_tail(&spec_eth.list, &rule.list); 180 172 list_add_tail(&spec_ip.list, &rule.list); 181 - list_add_tail(&spec_tcp.list, &rule.list); 173 + list_add_tail(&spec_tcp_udp.list, &rule.list); 182 174 183 175 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn; 184 176 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN); ··· 201 183 if (rc) 202 184 en_err(priv, "Error attaching flow. err = %d\n", rc); 203 185 186 + ignore: 204 187 mlx4_en_filter_rfs_expire(priv); 205 188 206 189 filter->activated = 1; ··· 225 206 226 207 static struct mlx4_en_filter * 227 208 mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip, 228 - __be32 dst_ip, __be16 src_port, __be16 dst_port, 229 - u32 flow_id) 209 + __be32 dst_ip, u8 ip_proto, __be16 src_port, 210 + __be16 dst_port, u32 flow_id) 230 211 { 231 212 struct mlx4_en_filter *filter = NULL; 232 213 ··· 240 221 241 222 filter->src_ip = src_ip; 242 223 filter->dst_ip = dst_ip; 224 + filter->ip_proto = ip_proto; 243 225 filter->src_port = src_port; 244 226 filter->dst_port = dst_port; 245 227 ··· 272 252 273 253 static inline struct mlx4_en_filter * 274 254 mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip, 275 - __be16 src_port, __be16 dst_port) 255 + u8 ip_proto, __be16 src_port, __be16 dst_port) 276 256 { 277 257 struct mlx4_en_filter *filter; 278 258 struct mlx4_en_filter *ret = NULL; ··· 283 263 filter_chain) { 284 264 if (filter->src_ip == src_ip && 285 265 filter->dst_ip == dst_ip && 266 + filter->ip_proto == ip_proto && 286 267 filter->src_port == src_port && 287 268 filter->dst_port == dst_port) { 288 269 ret = filter; ··· 302 281 struct mlx4_en_filter *filter; 303 282 const struct iphdr *ip; 304 283 const __be16 *ports; 284 + u8 ip_proto; 305 285 __be32 src_ip; 306 286 __be32 dst_ip; 307 287 __be16 src_port; ··· 317 295 if (ip_is_fragment(ip)) 318 296 return -EPROTONOSUPPORT; 319 297 298 + if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP)) 299 + return -EPROTONOSUPPORT; 320 300 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl); 321 301 302 + ip_proto = ip->protocol; 322 303 src_ip = ip->saddr; 323 304 dst_ip = ip->daddr; 324 305 src_port = ports[0]; 325 306 dst_port = ports[1]; 326 307 327 - if (ip->protocol != IPPROTO_TCP) 328 - return -EPROTONOSUPPORT; 329 - 330 308 spin_lock_bh(&priv->filters_lock); 331 - filter = mlx4_en_filter_find(priv, src_ip, dst_ip, src_port, dst_port); 309 + filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto, 310 + src_port, dst_port); 332 311 if (filter) { 333 312 if (filter->rxq_index == rxq_index) 334 313 goto out; ··· 337 314 filter->rxq_index = rxq_index; 338 315 } else { 339 316 filter = mlx4_en_filter_alloc(priv, rxq_index, 340 - src_ip, dst_ip, 317 + src_ip, dst_ip, ip_proto, 341 318 src_port, dst_port, flow_id); 342 319 if (!filter) { 343 320 ret = -ENOMEM; ··· 355 332 return ret; 356 333 } 357 334 358 - void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv, 359 - struct mlx4_en_rx_ring *rx_ring) 335 + void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv) 360 336 { 361 337 struct mlx4_en_filter *filter, *tmp; 362 338 LIST_HEAD(del_list); ··· 1241 1219 int i; 1242 1220 1243 1221 for (i = 0; i < priv->rx_ring_num; i++) { 1244 - cq = &priv->rx_cq[i]; 1222 + cq = priv->rx_cq[i]; 1245 1223 spin_lock_irqsave(&cq->lock, flags); 1246 1224 napi_synchronize(&cq->napi); 1247 1225 mlx4_en_process_rx_cq(dev, cq, 0); ··· 1263 1241 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i))) 1264 1242 continue; 1265 1243 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n", 1266 - i, priv->tx_ring[i].qpn, priv->tx_ring[i].cqn, 1267 - priv->tx_ring[i].cons, priv->tx_ring[i].prod); 1244 + i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn, 1245 + priv->tx_ring[i]->cons, priv->tx_ring[i]->prod); 1268 1246 } 1269 1247 1270 1248 priv->port_stats.tx_timeout++; ··· 1304 1282 1305 1283 /* Setup cq moderation params */ 1306 1284 for (i = 0; i < priv->rx_ring_num; i++) { 1307 - cq = &priv->rx_cq[i]; 1285 + cq = priv->rx_cq[i]; 1308 1286 cq->moder_cnt = priv->rx_frames; 1309 1287 cq->moder_time = priv->rx_usecs; 1310 1288 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; ··· 1313 1291 } 1314 1292 1315 1293 for (i = 0; i < priv->tx_ring_num; i++) { 1316 - cq = &priv->tx_cq[i]; 1294 + cq = priv->tx_cq[i]; 1317 1295 cq->moder_cnt = priv->tx_frames; 1318 1296 cq->moder_time = priv->tx_usecs; 1319 1297 } ··· 1347 1325 1348 1326 for (ring = 0; ring < priv->rx_ring_num; ring++) { 1349 1327 spin_lock_bh(&priv->stats_lock); 1350 - rx_packets = priv->rx_ring[ring].packets; 1351 - rx_bytes = priv->rx_ring[ring].bytes; 1328 + rx_packets = priv->rx_ring[ring]->packets; 1329 + rx_bytes = priv->rx_ring[ring]->bytes; 1352 1330 spin_unlock_bh(&priv->stats_lock); 1353 1331 1354 1332 rx_pkt_diff = ((unsigned long) (rx_packets - ··· 1377 1355 1378 1356 if (moder_time != priv->last_moder_time[ring]) { 1379 1357 priv->last_moder_time[ring] = moder_time; 1380 - cq = &priv->rx_cq[ring]; 1358 + cq = priv->rx_cq[ring]; 1381 1359 cq->moder_time = moder_time; 1382 1360 cq->moder_cnt = priv->rx_frames; 1383 1361 err = mlx4_en_set_cq_moder(priv, cq); ··· 1500 1478 return err; 1501 1479 } 1502 1480 for (i = 0; i < priv->rx_ring_num; i++) { 1503 - cq = &priv->rx_cq[i]; 1481 + cq = priv->rx_cq[i]; 1504 1482 1505 1483 mlx4_en_cq_init_lock(cq); 1506 1484 ··· 1518 1496 goto cq_err; 1519 1497 } 1520 1498 mlx4_en_arm_cq(priv, cq); 1521 - priv->rx_ring[i].cqn = cq->mcq.cqn; 1499 + priv->rx_ring[i]->cqn = cq->mcq.cqn; 1522 1500 ++rx_index; 1523 1501 } 1524 1502 ··· 1544 1522 /* Configure tx cq's and rings */ 1545 1523 for (i = 0; i < priv->tx_ring_num; i++) { 1546 1524 /* Configure cq */ 1547 - cq = &priv->tx_cq[i]; 1525 + cq = priv->tx_cq[i]; 1548 1526 err = mlx4_en_activate_cq(priv, cq, i); 1549 1527 if (err) { 1550 1528 en_err(priv, "Failed allocating Tx CQ\n"); ··· 1560 1538 cq->buf->wqe_index = cpu_to_be16(0xffff); 1561 1539 1562 1540 /* Configure ring */ 1563 - tx_ring = &priv->tx_ring[i]; 1541 + tx_ring = priv->tx_ring[i]; 1564 1542 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn, 1565 1543 i / priv->num_tx_rings_p_up); 1566 1544 if (err) { ··· 1630 1608 1631 1609 tx_err: 1632 1610 while (tx_index--) { 1633 - mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[tx_index]); 1634 - mlx4_en_deactivate_cq(priv, &priv->tx_cq[tx_index]); 1611 + mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]); 1612 + mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]); 1635 1613 } 1636 1614 mlx4_en_destroy_drop_qp(priv); 1637 1615 rss_err: ··· 1640 1618 mlx4_en_put_qp(priv); 1641 1619 cq_err: 1642 1620 while (rx_index--) 1643 - mlx4_en_deactivate_cq(priv, &priv->rx_cq[rx_index]); 1621 + mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]); 1644 1622 for (i = 0; i < priv->rx_ring_num; i++) 1645 - mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]); 1623 + mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]); 1646 1624 1647 1625 return err; /* need to close devices */ 1648 1626 } ··· 1738 1716 1739 1717 /* Free TX Rings */ 1740 1718 for (i = 0; i < priv->tx_ring_num; i++) { 1741 - mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[i]); 1742 - mlx4_en_deactivate_cq(priv, &priv->tx_cq[i]); 1719 + mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]); 1720 + mlx4_en_deactivate_cq(priv, priv->tx_cq[i]); 1743 1721 } 1744 1722 msleep(10); 1745 1723 1746 1724 for (i = 0; i < priv->tx_ring_num; i++) 1747 - mlx4_en_free_tx_buf(dev, &priv->tx_ring[i]); 1725 + mlx4_en_free_tx_buf(dev, priv->tx_ring[i]); 1748 1726 1749 1727 /* Free RSS qps */ 1750 1728 mlx4_en_release_rss_steer(priv); ··· 1756 1734 1757 1735 /* Free RX Rings */ 1758 1736 for (i = 0; i < priv->rx_ring_num; i++) { 1759 - struct mlx4_en_cq *cq = &priv->rx_cq[i]; 1737 + struct mlx4_en_cq *cq = priv->rx_cq[i]; 1760 1738 1761 1739 local_bh_disable(); 1762 1740 while (!mlx4_en_cq_lock_napi(cq)) { ··· 1767 1745 1768 1746 while (test_bit(NAPI_STATE_SCHED, &cq->napi.state)) 1769 1747 msleep(1); 1770 - mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]); 1748 + mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]); 1771 1749 mlx4_en_deactivate_cq(priv, cq); 1772 1750 } 1773 1751 } ··· 1805 1783 memset(&priv->port_stats, 0, sizeof(priv->port_stats)); 1806 1784 1807 1785 for (i = 0; i < priv->tx_ring_num; i++) { 1808 - priv->tx_ring[i].bytes = 0; 1809 - priv->tx_ring[i].packets = 0; 1810 - priv->tx_ring[i].tx_csum = 0; 1786 + priv->tx_ring[i]->bytes = 0; 1787 + priv->tx_ring[i]->packets = 0; 1788 + priv->tx_ring[i]->tx_csum = 0; 1811 1789 } 1812 1790 for (i = 0; i < priv->rx_ring_num; i++) { 1813 - priv->rx_ring[i].bytes = 0; 1814 - priv->rx_ring[i].packets = 0; 1815 - priv->rx_ring[i].csum_ok = 0; 1816 - priv->rx_ring[i].csum_none = 0; 1791 + priv->rx_ring[i]->bytes = 0; 1792 + priv->rx_ring[i]->packets = 0; 1793 + priv->rx_ring[i]->csum_ok = 0; 1794 + priv->rx_ring[i]->csum_none = 0; 1817 1795 } 1818 1796 } 1819 1797 ··· 1870 1848 #endif 1871 1849 1872 1850 for (i = 0; i < priv->tx_ring_num; i++) { 1873 - if (priv->tx_ring[i].tx_info) 1851 + if (priv->tx_ring && priv->tx_ring[i]) 1874 1852 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]); 1875 - if (priv->tx_cq[i].buf) 1853 + if (priv->tx_cq && priv->tx_cq[i]) 1876 1854 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]); 1877 1855 } 1878 1856 1879 1857 for (i = 0; i < priv->rx_ring_num; i++) { 1880 - if (priv->rx_ring[i].rx_info) 1858 + if (priv->rx_ring[i]) 1881 1859 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i], 1882 1860 priv->prof->rx_ring_size, priv->stride); 1883 - if (priv->rx_cq[i].buf) 1861 + if (priv->rx_cq[i]) 1884 1862 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]); 1885 1863 } 1886 1864 ··· 1895 1873 struct mlx4_en_port_profile *prof = priv->prof; 1896 1874 int i; 1897 1875 int err; 1876 + int node; 1898 1877 1899 1878 err = mlx4_qp_reserve_range(priv->mdev->dev, priv->tx_ring_num, 256, &priv->base_tx_qpn); 1900 1879 if (err) { ··· 1905 1882 1906 1883 /* Create tx Rings */ 1907 1884 for (i = 0; i < priv->tx_ring_num; i++) { 1885 + node = cpu_to_node(i % num_online_cpus()); 1908 1886 if (mlx4_en_create_cq(priv, &priv->tx_cq[i], 1909 - prof->tx_ring_size, i, TX)) 1887 + prof->tx_ring_size, i, TX, node)) 1910 1888 goto err; 1911 1889 1912 1890 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i], priv->base_tx_qpn + i, 1913 - prof->tx_ring_size, TXBB_SIZE)) 1891 + prof->tx_ring_size, TXBB_SIZE, node)) 1914 1892 goto err; 1915 1893 } 1916 1894 1917 1895 /* Create rx Rings */ 1918 1896 for (i = 0; i < priv->rx_ring_num; i++) { 1897 + node = cpu_to_node(i % num_online_cpus()); 1919 1898 if (mlx4_en_create_cq(priv, &priv->rx_cq[i], 1920 - prof->rx_ring_size, i, RX)) 1899 + prof->rx_ring_size, i, RX, node)) 1921 1900 goto err; 1922 1901 1923 1902 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i], 1924 - prof->rx_ring_size, priv->stride)) 1903 + prof->rx_ring_size, priv->stride, 1904 + node)) 1925 1905 goto err; 1926 1906 } 1927 1907 ··· 1940 1914 1941 1915 err: 1942 1916 en_err(priv, "Failed to allocate NIC resources\n"); 1917 + for (i = 0; i < priv->rx_ring_num; i++) { 1918 + if (priv->rx_ring[i]) 1919 + mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i], 1920 + prof->rx_ring_size, 1921 + priv->stride); 1922 + if (priv->rx_cq[i]) 1923 + mlx4_en_destroy_cq(priv, &priv->rx_cq[i]); 1924 + } 1925 + for (i = 0; i < priv->tx_ring_num; i++) { 1926 + if (priv->tx_ring[i]) 1927 + mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]); 1928 + if (priv->tx_cq[i]) 1929 + mlx4_en_destroy_cq(priv, &priv->tx_cq[i]); 1930 + } 1943 1931 return -ENOMEM; 1944 1932 } 1945 1933 ··· 2247 2207 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up; 2248 2208 priv->tx_ring_num = prof->tx_ring_num; 2249 2209 2250 - priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring) * MAX_TX_RINGS, 2210 + priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS, 2251 2211 GFP_KERNEL); 2252 2212 if (!priv->tx_ring) { 2253 2213 err = -ENOMEM; 2254 2214 goto out; 2255 2215 } 2256 - priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq) * MAX_TX_RINGS, 2216 + priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS, 2257 2217 GFP_KERNEL); 2258 2218 if (!priv->tx_cq) { 2259 2219 err = -ENOMEM;
+7 -10
drivers/net/ethernet/mellanox/mlx4/en_port.c
··· 56 56 return PTR_ERR(mailbox); 57 57 58 58 filter = mailbox->buf; 59 - memset(filter, 0, sizeof(*filter)); 60 59 for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) { 61 60 entry = 0; 62 61 for (j = 0; j < 32; j++) ··· 80 81 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 81 82 if (IS_ERR(mailbox)) 82 83 return PTR_ERR(mailbox); 83 - memset(mailbox->buf, 0, sizeof(*qport_context)); 84 84 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 85 85 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 86 86 MLX4_CMD_WRAPPED); ··· 125 127 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 126 128 if (IS_ERR(mailbox)) 127 129 return PTR_ERR(mailbox); 128 - memset(mailbox->buf, 0, sizeof(*mlx4_en_stats)); 129 130 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0, 130 131 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B, 131 132 MLX4_CMD_WRAPPED); ··· 140 143 priv->port_stats.rx_chksum_good = 0; 141 144 priv->port_stats.rx_chksum_none = 0; 142 145 for (i = 0; i < priv->rx_ring_num; i++) { 143 - stats->rx_packets += priv->rx_ring[i].packets; 144 - stats->rx_bytes += priv->rx_ring[i].bytes; 145 - priv->port_stats.rx_chksum_good += priv->rx_ring[i].csum_ok; 146 - priv->port_stats.rx_chksum_none += priv->rx_ring[i].csum_none; 146 + stats->rx_packets += priv->rx_ring[i]->packets; 147 + stats->rx_bytes += priv->rx_ring[i]->bytes; 148 + priv->port_stats.rx_chksum_good += priv->rx_ring[i]->csum_ok; 149 + priv->port_stats.rx_chksum_none += priv->rx_ring[i]->csum_none; 147 150 } 148 151 stats->tx_packets = 0; 149 152 stats->tx_bytes = 0; 150 153 priv->port_stats.tx_chksum_offload = 0; 151 154 for (i = 0; i < priv->tx_ring_num; i++) { 152 - stats->tx_packets += priv->tx_ring[i].packets; 153 - stats->tx_bytes += priv->tx_ring[i].bytes; 154 - priv->port_stats.tx_chksum_offload += priv->tx_ring[i].tx_csum; 155 + stats->tx_packets += priv->tx_ring[i]->packets; 156 + stats->tx_bytes += priv->tx_ring[i]->bytes; 157 + priv->port_stats.tx_chksum_offload += priv->tx_ring[i]->tx_csum; 155 158 } 156 159 157 160 stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
+48 -20
drivers/net/ethernet/mellanox/mlx4/en_rx.c
··· 264 264 265 265 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { 266 266 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 267 - ring = &priv->rx_ring[ring_ind]; 267 + ring = priv->rx_ring[ring_ind]; 268 268 269 269 if (mlx4_en_prepare_rx_desc(priv, ring, 270 270 ring->actual_size, ··· 289 289 290 290 reduce_rings: 291 291 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 292 - ring = &priv->rx_ring[ring_ind]; 292 + ring = priv->rx_ring[ring_ind]; 293 293 while (ring->actual_size > new_size) { 294 294 ring->actual_size--; 295 295 ring->prod--; ··· 319 319 } 320 320 321 321 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 322 - struct mlx4_en_rx_ring *ring, u32 size, u16 stride) 322 + struct mlx4_en_rx_ring **pring, 323 + u32 size, u16 stride, int node) 323 324 { 324 325 struct mlx4_en_dev *mdev = priv->mdev; 326 + struct mlx4_en_rx_ring *ring; 325 327 int err = -ENOMEM; 326 328 int tmp; 329 + 330 + ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 331 + if (!ring) { 332 + ring = kzalloc(sizeof(*ring), GFP_KERNEL); 333 + if (!ring) { 334 + en_err(priv, "Failed to allocate RX ring structure\n"); 335 + return -ENOMEM; 336 + } 337 + } 327 338 328 339 ring->prod = 0; 329 340 ring->cons = 0; ··· 346 335 347 336 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * 348 337 sizeof(struct mlx4_en_rx_alloc)); 349 - ring->rx_info = vmalloc(tmp); 350 - if (!ring->rx_info) 351 - return -ENOMEM; 338 + ring->rx_info = vmalloc_node(tmp, node); 339 + if (!ring->rx_info) { 340 + ring->rx_info = vmalloc(tmp); 341 + if (!ring->rx_info) { 342 + err = -ENOMEM; 343 + goto err_ring; 344 + } 345 + } 352 346 353 347 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", 354 348 ring->rx_info, tmp); 355 349 350 + /* Allocate HW buffers on provided NUMA node */ 351 + set_dev_node(&mdev->dev->pdev->dev, node); 356 352 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, 357 353 ring->buf_size, 2 * PAGE_SIZE); 354 + set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); 358 355 if (err) 359 - goto err_ring; 356 + goto err_info; 360 357 361 358 err = mlx4_en_map_buffer(&ring->wqres.buf); 362 359 if (err) { ··· 375 356 376 357 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; 377 358 359 + *pring = ring; 378 360 return 0; 379 361 380 362 err_hwq: 381 363 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); 382 - err_ring: 364 + err_info: 383 365 vfree(ring->rx_info); 384 366 ring->rx_info = NULL; 367 + err_ring: 368 + kfree(ring); 369 + *pring = NULL; 370 + 385 371 return err; 386 372 } 387 373 ··· 400 376 DS_SIZE * priv->num_frags); 401 377 402 378 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 403 - ring = &priv->rx_ring[ring_ind]; 379 + ring = priv->rx_ring[ring_ind]; 404 380 405 381 ring->prod = 0; 406 382 ring->cons = 0; 407 383 ring->actual_size = 0; 408 - ring->cqn = priv->rx_cq[ring_ind].mcq.cqn; 384 + ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; 409 385 410 386 ring->stride = stride; 411 387 if (ring->stride <= TXBB_SIZE) ··· 436 412 goto err_buffers; 437 413 438 414 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { 439 - ring = &priv->rx_ring[ring_ind]; 415 + ring = priv->rx_ring[ring_ind]; 440 416 441 417 ring->size_mask = ring->actual_size - 1; 442 418 mlx4_en_update_rx_prod_db(ring); ··· 446 422 447 423 err_buffers: 448 424 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) 449 - mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]); 425 + mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); 450 426 451 427 ring_ind = priv->rx_ring_num - 1; 452 428 err_allocator: 453 429 while (ring_ind >= 0) { 454 - if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE) 455 - priv->rx_ring[ring_ind].buf -= TXBB_SIZE; 456 - mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]); 430 + if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) 431 + priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; 432 + mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); 457 433 ring_ind--; 458 434 } 459 435 return err; 460 436 } 461 437 462 438 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 463 - struct mlx4_en_rx_ring *ring, u32 size, u16 stride) 439 + struct mlx4_en_rx_ring **pring, 440 + u32 size, u16 stride) 464 441 { 465 442 struct mlx4_en_dev *mdev = priv->mdev; 443 + struct mlx4_en_rx_ring *ring = *pring; 466 444 467 445 mlx4_en_unmap_buffer(&ring->wqres.buf); 468 446 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); 469 447 vfree(ring->rx_info); 470 448 ring->rx_info = NULL; 449 + kfree(ring); 450 + *pring = NULL; 471 451 #ifdef CONFIG_RFS_ACCEL 472 - mlx4_en_cleanup_filters(priv, ring); 452 + mlx4_en_cleanup_filters(priv); 473 453 #endif 474 454 } 475 455 ··· 620 592 struct mlx4_en_priv *priv = netdev_priv(dev); 621 593 struct mlx4_en_dev *mdev = priv->mdev; 622 594 struct mlx4_cqe *cqe; 623 - struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; 595 + struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; 624 596 struct mlx4_en_rx_alloc *frags; 625 597 struct mlx4_en_rx_desc *rx_desc; 626 598 struct sk_buff *skb; ··· 1019 991 1020 992 for (i = 0; i < priv->rx_ring_num; i++) { 1021 993 qpn = rss_map->base_qpn + i; 1022 - err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i], 994 + err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], 1023 995 &rss_map->state[i], 1024 996 &rss_map->qps[i]); 1025 997 if (err) ··· 1036 1008 } 1037 1009 rss_map->indir_qp.event = mlx4_en_sqp_event; 1038 1010 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, 1039 - priv->rx_ring[0].cqn, -1, &context); 1011 + priv->rx_ring[0]->cqn, -1, &context); 1040 1012 1041 1013 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) 1042 1014 rss_rings = priv->rx_ring_num;
+1 -1
drivers/net/ethernet/mellanox/mlx4/en_selftest.c
··· 156 156 * since we turned the carrier off */ 157 157 msleep(200); 158 158 for (i = 0; i < priv->tx_ring_num && carrier_ok; i++) { 159 - tx_ring = &priv->tx_ring[i]; 159 + tx_ring = priv->tx_ring[i]; 160 160 if (tx_ring->prod != (tx_ring->cons + tx_ring->last_nr_txbb)) 161 161 goto retry_tx; 162 162 }
+41 -13
drivers/net/ethernet/mellanox/mlx4/en_tx.c
··· 54 54 MODULE_PARM_DESC(inline_thold, "threshold for using inline data"); 55 55 56 56 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 57 - struct mlx4_en_tx_ring *ring, int qpn, u32 size, 58 - u16 stride) 57 + struct mlx4_en_tx_ring **pring, int qpn, u32 size, 58 + u16 stride, int node) 59 59 { 60 60 struct mlx4_en_dev *mdev = priv->mdev; 61 + struct mlx4_en_tx_ring *ring; 61 62 int tmp; 62 63 int err; 64 + 65 + ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); 66 + if (!ring) { 67 + ring = kzalloc(sizeof(*ring), GFP_KERNEL); 68 + if (!ring) { 69 + en_err(priv, "Failed allocating TX ring\n"); 70 + return -ENOMEM; 71 + } 72 + } 63 73 64 74 ring->size = size; 65 75 ring->size_mask = size - 1; ··· 78 68 inline_thold = min(inline_thold, MAX_INLINE); 79 69 80 70 tmp = size * sizeof(struct mlx4_en_tx_info); 81 - ring->tx_info = vmalloc(tmp); 82 - if (!ring->tx_info) 83 - return -ENOMEM; 71 + ring->tx_info = vmalloc_node(tmp, node); 72 + if (!ring->tx_info) { 73 + ring->tx_info = vmalloc(tmp); 74 + if (!ring->tx_info) { 75 + err = -ENOMEM; 76 + goto err_ring; 77 + } 78 + } 84 79 85 80 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", 86 81 ring->tx_info, tmp); 87 82 88 - ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 83 + ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); 89 84 if (!ring->bounce_buf) { 90 - err = -ENOMEM; 91 - goto err_tx; 85 + ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); 86 + if (!ring->bounce_buf) { 87 + err = -ENOMEM; 88 + goto err_info; 89 + } 92 90 } 93 91 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); 94 92 93 + /* Allocate HW buffers on provided NUMA node */ 94 + set_dev_node(&mdev->dev->pdev->dev, node); 95 95 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, 96 96 2 * PAGE_SIZE); 97 + set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); 97 98 if (err) { 98 99 en_err(priv, "Failed allocating hwq resources\n"); 99 100 goto err_bounce; ··· 130 109 } 131 110 ring->qp.event = mlx4_en_sqp_event; 132 111 133 - err = mlx4_bf_alloc(mdev->dev, &ring->bf); 112 + err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); 134 113 if (err) { 135 114 en_dbg(DRV, priv, "working without blueflame (%d)", err); 136 115 ring->bf.uar = &mdev->priv_uar; ··· 141 120 142 121 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; 143 122 123 + *pring = ring; 144 124 return 0; 145 125 146 126 err_map: ··· 151 129 err_bounce: 152 130 kfree(ring->bounce_buf); 153 131 ring->bounce_buf = NULL; 154 - err_tx: 132 + err_info: 155 133 vfree(ring->tx_info); 156 134 ring->tx_info = NULL; 135 + err_ring: 136 + kfree(ring); 137 + *pring = NULL; 157 138 return err; 158 139 } 159 140 160 141 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 161 - struct mlx4_en_tx_ring *ring) 142 + struct mlx4_en_tx_ring **pring) 162 143 { 163 144 struct mlx4_en_dev *mdev = priv->mdev; 145 + struct mlx4_en_tx_ring *ring = *pring; 164 146 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); 165 147 166 148 if (ring->bf_enabled) ··· 177 151 ring->bounce_buf = NULL; 178 152 vfree(ring->tx_info); 179 153 ring->tx_info = NULL; 154 + kfree(ring); 155 + *pring = NULL; 180 156 } 181 157 182 158 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, ··· 358 330 { 359 331 struct mlx4_en_priv *priv = netdev_priv(dev); 360 332 struct mlx4_cq *mcq = &cq->mcq; 361 - struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; 333 + struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; 362 334 struct mlx4_cqe *cqe; 363 335 u16 index; 364 336 u16 new_index, ring_index, stamp_index; ··· 650 622 } 651 623 652 624 tx_ind = skb->queue_mapping; 653 - ring = &priv->tx_ring[tx_ind]; 625 + ring = priv->tx_ring[tx_ind]; 654 626 if (vlan_tx_tag_present(skb)) 655 627 vlan_tag = vlan_tx_tag_get(skb); 656 628
-1
drivers/net/ethernet/mellanox/mlx4/eq.c
··· 936 936 if (err) 937 937 goto err_out_free_mtt; 938 938 939 - memset(eq_context, 0, sizeof *eq_context); 940 939 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | 941 940 MLX4_EQ_STATE_ARMED); 942 941 eq_context->log_eq_size = ilog2(eq->nent);
-7
drivers/net/ethernet/mellanox/mlx4/fw.c
··· 159 159 return PTR_ERR(mailbox); 160 160 inbox = mailbox->buf; 161 161 162 - memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); 163 - 164 162 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 165 163 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 166 164 ··· 965 967 mailbox = mlx4_alloc_cmd_mailbox(dev); 966 968 if (IS_ERR(mailbox)) 967 969 return PTR_ERR(mailbox); 968 - memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); 969 970 pages = mailbox->buf; 970 971 971 972 for (mlx4_icm_first(icm, &iter); ··· 1313 1316 return PTR_ERR(mailbox); 1314 1317 inbox = mailbox->buf; 1315 1318 1316 - memset(inbox, 0, INIT_HCA_IN_SIZE); 1317 - 1318 1319 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1319 1320 1320 1321 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = ··· 1610 1615 if (IS_ERR(mailbox)) 1611 1616 return PTR_ERR(mailbox); 1612 1617 inbox = mailbox->buf; 1613 - 1614 - memset(inbox, 0, INIT_PORT_IN_SIZE); 1615 1618 1616 1619 flags = 0; 1617 1620 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
+30 -12
drivers/net/ethernet/mellanox/mlx4/icm.c
··· 93 93 kfree(icm); 94 94 } 95 95 96 - static int mlx4_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask) 96 + static int mlx4_alloc_icm_pages(struct scatterlist *mem, int order, 97 + gfp_t gfp_mask, int node) 97 98 { 98 99 struct page *page; 99 100 100 - page = alloc_pages(gfp_mask, order); 101 - if (!page) 102 - return -ENOMEM; 101 + page = alloc_pages_node(node, gfp_mask, order); 102 + if (!page) { 103 + page = alloc_pages(gfp_mask, order); 104 + if (!page) 105 + return -ENOMEM; 106 + } 103 107 104 108 sg_set_page(mem, page, PAGE_SIZE << order, 0); 105 109 return 0; ··· 134 130 /* We use sg_set_buf for coherent allocs, which assumes low memory */ 135 131 BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM)); 136 132 137 - icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN)); 138 - if (!icm) 139 - return NULL; 133 + icm = kmalloc_node(sizeof(*icm), 134 + gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN), 135 + dev->numa_node); 136 + if (!icm) { 137 + icm = kmalloc(sizeof(*icm), 138 + gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN)); 139 + if (!icm) 140 + return NULL; 141 + } 140 142 141 143 icm->refcount = 0; 142 144 INIT_LIST_HEAD(&icm->chunk_list); ··· 151 141 152 142 while (npages > 0) { 153 143 if (!chunk) { 154 - chunk = kmalloc(sizeof *chunk, 155 - gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN)); 156 - if (!chunk) 157 - goto fail; 144 + chunk = kmalloc_node(sizeof(*chunk), 145 + gfp_mask & ~(__GFP_HIGHMEM | 146 + __GFP_NOWARN), 147 + dev->numa_node); 148 + if (!chunk) { 149 + chunk = kmalloc(sizeof(*chunk), 150 + gfp_mask & ~(__GFP_HIGHMEM | 151 + __GFP_NOWARN)); 152 + if (!chunk) 153 + goto fail; 154 + } 158 155 159 156 sg_init_table(chunk->mem, MLX4_ICM_CHUNK_LEN); 160 157 chunk->npages = 0; ··· 178 161 cur_order, gfp_mask); 179 162 else 180 163 ret = mlx4_alloc_icm_pages(&chunk->mem[chunk->npages], 181 - cur_order, gfp_mask); 164 + cur_order, gfp_mask, 165 + dev->numa_node); 182 166 183 167 if (ret) { 184 168 if (--cur_order < 0)
+1
drivers/net/ethernet/mellanox/mlx4/main.c
··· 2191 2191 mutex_init(&priv->bf_mutex); 2192 2192 2193 2193 dev->rev_id = pdev->revision; 2194 + dev->numa_node = dev_to_node(&pdev->dev); 2194 2195 /* Detect if this device is a virtual function */ 2195 2196 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 2196 2197 /* When acting as pf, we normally skip vfs unless explicitly
-2
drivers/net/ethernet/mellanox/mlx4/mcg.c
··· 506 506 goto out_list; 507 507 } 508 508 mgm = mailbox->buf; 509 - memset(mgm, 0, sizeof *mgm); 510 509 members_count = 0; 511 510 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list) 512 511 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK); ··· 856 857 if (IS_ERR(mailbox)) 857 858 return PTR_ERR(mailbox); 858 859 859 - memset(mailbox->buf, 0, sizeof(struct mlx4_net_trans_rule_hw_ctrl)); 860 860 trans_rule_ctrl_to_hw(rule, mailbox->buf); 861 861 862 862 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
+17 -16
drivers/net/ethernet/mellanox/mlx4/mlx4_en.h
··· 530 530 u16 num_frags; 531 531 u16 log_rx_info; 532 532 533 - struct mlx4_en_tx_ring *tx_ring; 534 - struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS]; 535 - struct mlx4_en_cq *tx_cq; 536 - struct mlx4_en_cq rx_cq[MAX_RX_RINGS]; 533 + struct mlx4_en_tx_ring **tx_ring; 534 + struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 535 + struct mlx4_en_cq **tx_cq; 536 + struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 537 537 struct mlx4_qp drop_qp; 538 538 struct work_struct rx_mode_task; 539 539 struct work_struct watchdog_task; ··· 626 626 if ((cq->state & MLX4_CQ_LOCKED)) { 627 627 struct net_device *dev = cq->dev; 628 628 struct mlx4_en_priv *priv = netdev_priv(dev); 629 - struct mlx4_en_rx_ring *rx_ring = &priv->rx_ring[cq->ring]; 629 + struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 630 630 631 631 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD; 632 632 rc = false; ··· 704 704 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 705 705 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 706 706 707 - int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 708 - int entries, int ring, enum cq_type mode); 709 - void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 707 + int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 708 + int entries, int ring, enum cq_type mode, int node); 709 + void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 710 710 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 711 711 int cq_idx); 712 712 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); ··· 717 717 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb); 718 718 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 719 719 720 - int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring, 721 - int qpn, u32 size, u16 stride); 722 - void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring); 720 + int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 721 + struct mlx4_en_tx_ring **pring, 722 + int qpn, u32 size, u16 stride, int node); 723 + void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 724 + struct mlx4_en_tx_ring **pring); 723 725 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 724 726 struct mlx4_en_tx_ring *ring, 725 727 int cq, int user_prio); ··· 729 727 struct mlx4_en_tx_ring *ring); 730 728 731 729 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 732 - struct mlx4_en_rx_ring *ring, 733 - u32 size, u16 stride); 730 + struct mlx4_en_rx_ring **pring, 731 + u32 size, u16 stride, int node); 734 732 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 735 - struct mlx4_en_rx_ring *ring, 733 + struct mlx4_en_rx_ring **pring, 736 734 u32 size, u16 stride); 737 735 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 738 736 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, ··· 770 768 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 771 769 772 770 #ifdef CONFIG_RFS_ACCEL 773 - void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv, 774 - struct mlx4_en_rx_ring *rx_ring); 771 + void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 775 772 #endif 776 773 777 774 #define MLX4_EN_NUM_SELF_TEST 5
-5
drivers/net/ethernet/mellanox/mlx4/mr.c
··· 480 480 goto err_table; 481 481 } 482 482 mpt_entry = mailbox->buf; 483 - 484 - memset(mpt_entry, 0, sizeof *mpt_entry); 485 - 486 483 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO | 487 484 MLX4_MPT_FLAG_REGION | 488 485 mr->access); ··· 691 694 goto err_table; 692 695 } 693 696 mpt_entry = mailbox->buf; 694 - 695 - memset(mpt_entry, 0, sizeof(*mpt_entry)); 696 697 697 698 /* Note that the MLX4_MPT_FLAG_REGION bit in mpt_entry->flags is turned 698 699 * off, thus creating a memory window and not a memory region.
+7 -4
drivers/net/ethernet/mellanox/mlx4/pd.c
··· 168 168 } 169 169 EXPORT_SYMBOL_GPL(mlx4_uar_free); 170 170 171 - int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf) 171 + int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node) 172 172 { 173 173 struct mlx4_priv *priv = mlx4_priv(dev); 174 174 struct mlx4_uar *uar; ··· 186 186 err = -ENOMEM; 187 187 goto out; 188 188 } 189 - uar = kmalloc(sizeof *uar, GFP_KERNEL); 189 + uar = kmalloc_node(sizeof(*uar), GFP_KERNEL, node); 190 190 if (!uar) { 191 - err = -ENOMEM; 192 - goto out; 191 + uar = kmalloc(sizeof(*uar), GFP_KERNEL); 192 + if (!uar) { 193 + err = -ENOMEM; 194 + goto out; 195 + } 193 196 } 194 197 err = mlx4_uar_alloc(dev, uar); 195 198 if (err)
-11
drivers/net/ethernet/mellanox/mlx4/port.c
··· 469 469 470 470 inbuf = inmailbox->buf; 471 471 outbuf = outmailbox->buf; 472 - memset(inbuf, 0, 256); 473 - memset(outbuf, 0, 256); 474 472 inbuf[0] = 1; 475 473 inbuf[1] = 1; 476 474 inbuf[2] = 1; ··· 651 653 if (IS_ERR(mailbox)) 652 654 return PTR_ERR(mailbox); 653 655 654 - memset(mailbox->buf, 0, 256); 655 - 656 656 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port]; 657 657 658 658 if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) { ··· 688 692 if (IS_ERR(mailbox)) 689 693 return PTR_ERR(mailbox); 690 694 context = mailbox->buf; 691 - memset(context, 0, sizeof *context); 692 - 693 695 context->flags = SET_PORT_GEN_ALL_VALID; 694 696 context->mtu = cpu_to_be16(mtu); 695 697 context->pptx = (pptx * (!pfctx)) << 7; ··· 721 727 if (IS_ERR(mailbox)) 722 728 return PTR_ERR(mailbox); 723 729 context = mailbox->buf; 724 - memset(context, 0, sizeof *context); 725 - 726 730 context->base_qpn = cpu_to_be32(base_qpn); 727 731 context->n_mac = dev->caps.log_num_macs; 728 732 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT | ··· 753 761 if (IS_ERR(mailbox)) 754 762 return PTR_ERR(mailbox); 755 763 context = mailbox->buf; 756 - memset(context, 0, sizeof *context); 757 - 758 764 for (i = 0; i < MLX4_NUM_UP; i += 2) 759 765 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1]; 760 766 ··· 778 788 if (IS_ERR(mailbox)) 779 789 return PTR_ERR(mailbox); 780 790 context = mailbox->buf; 781 - memset(context, 0, sizeof *context); 782 791 783 792 for (i = 0; i < MLX4_NUM_TC; i++) { 784 793 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
+67 -12
drivers/net/ethernet/mellanox/mlx4/resource_tracker.c
··· 110 110 int local_qpn; 111 111 atomic_t ref_count; 112 112 u32 qpc_flags; 113 + /* saved qp params before VST enforcement in order to restore on VGT */ 113 114 u8 sched_queue; 115 + __be32 param3; 116 + u8 vlan_control; 117 + u8 fvl_rx; 118 + u8 pri_path_fl; 119 + u8 vlan_index; 120 + u8 feup; 114 121 }; 115 122 116 123 enum res_mtt_states { ··· 2575 2568 return err; 2576 2569 qp->local_qpn = local_qpn; 2577 2570 qp->sched_queue = 0; 2571 + qp->param3 = 0; 2572 + qp->vlan_control = 0; 2573 + qp->fvl_rx = 0; 2574 + qp->pri_path_fl = 0; 2575 + qp->vlan_index = 0; 2576 + qp->feup = 0; 2578 2577 qp->qpc_flags = be32_to_cpu(qpc->flags); 2579 2578 2580 2579 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt); ··· 3307 3294 int qpn = vhcr->in_modifier & 0x7fffff; 3308 3295 struct res_qp *qp; 3309 3296 u8 orig_sched_queue; 3297 + __be32 orig_param3 = qpc->param3; 3298 + u8 orig_vlan_control = qpc->pri_path.vlan_control; 3299 + u8 orig_fvl_rx = qpc->pri_path.fvl_rx; 3300 + u8 orig_pri_path_fl = qpc->pri_path.fl; 3301 + u8 orig_vlan_index = qpc->pri_path.vlan_index; 3302 + u8 orig_feup = qpc->pri_path.feup; 3310 3303 3311 3304 err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave); 3312 3305 if (err) ··· 3340 3321 * essentially the QOS value provided by the VF. This will be useful 3341 3322 * if we allow dynamic changes from VST back to VGT 3342 3323 */ 3343 - if (!err) 3324 + if (!err) { 3344 3325 qp->sched_queue = orig_sched_queue; 3345 - 3326 + qp->param3 = orig_param3; 3327 + qp->vlan_control = orig_vlan_control; 3328 + qp->fvl_rx = orig_fvl_rx; 3329 + qp->pri_path_fl = orig_pri_path_fl; 3330 + qp->vlan_index = orig_vlan_index; 3331 + qp->feup = orig_feup; 3332 + } 3346 3333 put_res(dev, slave, qpn, RES_QP); 3347 3334 return err; 3348 3335 } ··· 4462 4437 &tracker->slave_list[work->slave].res_list[RES_QP]; 4463 4438 struct res_qp *qp; 4464 4439 struct res_qp *tmp; 4465 - u64 qp_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) | 4440 + u64 qp_path_mask_vlan_ctrl = 4441 + ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) | 4466 4442 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) | 4467 4443 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) | 4468 4444 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) | 4469 4445 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) | 4470 - (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED) | 4471 - (1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) | 4446 + (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED)); 4447 + 4448 + u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) | 4449 + (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) | 4450 + (1ULL << MLX4_UPD_QP_PATH_MASK_CV) | 4451 + (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) | 4452 + (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) | 4453 + (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) | 4472 4454 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE)); 4473 4455 4474 4456 int err; ··· 4507 4475 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED; 4508 4476 4509 4477 upd_context = mailbox->buf; 4510 - upd_context->primary_addr_path_mask = cpu_to_be64(qp_mask); 4511 - upd_context->qp_context.pri_path.vlan_control = vlan_control; 4512 - upd_context->qp_context.pri_path.vlan_index = work->vlan_ix; 4478 + upd_context->qp_mask = cpu_to_be64(MLX4_UPD_QP_MASK_VSD); 4513 4479 4514 4480 spin_lock_irq(mlx4_tlock(dev)); 4515 4481 list_for_each_entry_safe(qp, tmp, qp_list, com.list) { ··· 4525 4495 spin_lock_irq(mlx4_tlock(dev)); 4526 4496 continue; 4527 4497 } 4528 - upd_context->qp_context.pri_path.sched_queue = 4529 - qp->sched_queue & 0xC7; 4530 - upd_context->qp_context.pri_path.sched_queue |= 4531 - ((work->qos & 0x7) << 3); 4498 + if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff)) 4499 + upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask); 4500 + else 4501 + upd_context->primary_addr_path_mask = 4502 + cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl); 4503 + if (work->vlan_id == MLX4_VGT) { 4504 + upd_context->qp_context.param3 = qp->param3; 4505 + upd_context->qp_context.pri_path.vlan_control = qp->vlan_control; 4506 + upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx; 4507 + upd_context->qp_context.pri_path.vlan_index = qp->vlan_index; 4508 + upd_context->qp_context.pri_path.fl = qp->pri_path_fl; 4509 + upd_context->qp_context.pri_path.feup = qp->feup; 4510 + upd_context->qp_context.pri_path.sched_queue = 4511 + qp->sched_queue; 4512 + } else { 4513 + upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN); 4514 + upd_context->qp_context.pri_path.vlan_control = vlan_control; 4515 + upd_context->qp_context.pri_path.vlan_index = work->vlan_ix; 4516 + upd_context->qp_context.pri_path.fvl_rx = 4517 + qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN; 4518 + upd_context->qp_context.pri_path.fl = 4519 + qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN; 4520 + upd_context->qp_context.pri_path.feup = 4521 + qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN; 4522 + upd_context->qp_context.pri_path.sched_queue = 4523 + qp->sched_queue & 0xC7; 4524 + upd_context->qp_context.pri_path.sched_queue |= 4525 + ((work->qos & 0x7) << 3); 4526 + } 4532 4527 4533 4528 err = mlx4_cmd(dev, mailbox->dma, 4534 4529 qp->local_qpn & 0xffffff,
-2
drivers/net/ethernet/mellanox/mlx4/srq.c
··· 189 189 } 190 190 191 191 srq_context = mailbox->buf; 192 - memset(srq_context, 0, sizeof *srq_context); 193 - 194 192 srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) | 195 193 srq->srqn); 196 194 srq_context->logstride = srq->wqe_shift - 4;
+2 -1
include/linux/mlx4/device.h
··· 662 662 u8 rev_id; 663 663 char board_id[MLX4_BOARD_ID_LEN]; 664 664 int num_vfs; 665 + int numa_node; 665 666 int oper_log_mgm_entry_size; 666 667 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 667 668 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; ··· 835 834 836 835 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 837 836 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 838 - int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); 837 + int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 839 838 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 840 839 841 840 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,