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linux
iio: accel: adxl367: Fix alignment for DMA safety
____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_DMA_MINALIGN definition.
Update comment to reflect that DMA safety may require separate
cachelines.
Fixes: cbab791c5e2a5 ("iio: accel: add ADXL367 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cosmin Tanislav <demonsingur@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-5-jic23@kernel.org
+6
-4
+1
-1
drivers/iio/accel/adxl367.c
+1
-1
drivers/iio/accel/adxl367.c
···
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unsigned int fifo_set_size;
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unsigned int fifo_watermark;
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-
__be16 fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned;
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+
__be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
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__be16 sample_buf;
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u8 act_threshold_buf[2];
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u8 inact_time_buf[2];
+5
-3
drivers/iio/accel/adxl367_spi.c
+5
-3
drivers/iio/accel/adxl367_spi.c
···
9
9
#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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+
#include <linux/iio/iio.h>
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+
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#include "adxl367.h"
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#define ADXL367_SPI_WRITE_COMMAND 0x0A
···
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struct spi_transfer fifo_xfer[2];
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/*
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-
* DMA (thus cache coherency maintenance) requires the
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-
* transfer buffers to live in their own cache lines.
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+
* DMA (thus cache coherency maintenance) may require the
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+
* transfer buffers live in their own cache lines.
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*/
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-
u8 reg_write_tx_buf[1] ____cacheline_aligned;
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+
u8 reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN);
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u8 reg_read_tx_buf[2];
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u8 fifo_tx_buf[1];
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};