Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ptp: idt82p33: Add .getmaxphase ptp_clock_info callback

Advertise the maximum offset the .adjphase callback is capable of
supporting in nanoseconds for IDT devices.

Refactor the negation of the offset stored in the register to be after the
boundary check of the offset value rather than before. Boundary check based
on the intended value rather than its device-specific representation.
Depend on ptp_clock_adjtime for handling out-of-range offsets.
ptp_clock_adjtime returns -ERANGE instead of clamping out-of-range offsets.

Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Min Li <min.li.xe@renesas.com>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Rahul Rameshbabu and committed by
David S. Miller
e156e4d2 c066e74f

+11 -11
+9 -9
drivers/ptp/ptp_idt82p33.c
··· 978 978 return err; 979 979 } 980 980 981 + static s32 idt82p33_getmaxphase(__always_unused struct ptp_clock_info *ptp) 982 + { 983 + return WRITE_PHASE_OFFSET_LIMIT; 984 + } 985 + 981 986 static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns) 982 987 { 983 988 struct idt82p33_channel *channel = 984 989 container_of(ptp, struct idt82p33_channel, caps); 985 990 struct idt82p33 *idt82p33 = channel->idt82p33; 986 - s64 offset_regval, offset_fs; 991 + s64 offset_regval; 987 992 u8 val[4] = {0}; 988 993 int err; 989 994 990 - offset_fs = (s64)(-offset_ns) * 1000000; 991 - 992 - if (offset_fs > WRITE_PHASE_OFFSET_LIMIT) 993 - offset_fs = WRITE_PHASE_OFFSET_LIMIT; 994 - else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT) 995 - offset_fs = -WRITE_PHASE_OFFSET_LIMIT; 996 - 997 995 /* Convert from phaseoffset_fs to register value */ 998 - offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL); 996 + offset_regval = div_s64((s64)(-offset_ns) * 1000000000ll, 997 + IDT_T0DPLL_PHASE_RESOL); 999 998 1000 999 val[0] = offset_regval & 0xFF; 1001 1000 val[1] = (offset_regval >> 8) & 0xFF; ··· 1174 1175 caps->n_ext_ts = MAX_PHC_PLL, 1175 1176 caps->n_pins = max_pins, 1176 1177 caps->adjphase = idt82p33_adjwritephase, 1178 + caps->getmaxphase = idt82p33_getmaxphase, 1177 1179 caps->adjfine = idt82p33_adjfine; 1178 1180 caps->adjtime = idt82p33_adjtime; 1179 1181 caps->gettime64 = idt82p33_gettime;
+2 -2
drivers/ptp/ptp_idt82p33.h
··· 43 43 #define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0 44 44 45 45 /** 46 - * @brief Maximum absolute value for write phase offset in femtoseconds 46 + * @brief Maximum absolute value for write phase offset in nanoseconds 47 47 */ 48 - #define WRITE_PHASE_OFFSET_LIMIT (20000052084ll) 48 + #define WRITE_PHASE_OFFSET_LIMIT (20000l) 49 49 50 50 /** @brief Phase offset resolution 51 51 *