Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dt-bindings: interrupt-controller: Convert marvell,ap806-gicp to DT schema

Convert the Marvell GICP MSI controller binding to schema format. It's a
straight-forward conversion of the typical MSI controller.

Link: https://lore.kernel.org/r/20250505144721.1290068-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

+50 -27
+50
Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-gicp.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-gicp.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Marvell GICP Controller 8 + 9 + maintainers: 10 + - Thomas Petazzoni <thomas.petazzoni@bootlin.com> 11 + 12 + description: 13 + GICP is a Marvell extension of the GIC that allows to trigger GIC SPI 14 + interrupts by doing a memory transaction. It is used by the ICU 15 + located in the Marvell CP110 to turn wired interrupts inside the CP 16 + into GIC SPI interrupts. 17 + 18 + properties: 19 + compatible: 20 + const: marvell,ap806-gicp 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + marvell,spi-ranges: 26 + description: Tuples of GIC SPI interrupt ranges available for this GICP 27 + $ref: /schemas/types.yaml#/definitions/uint32-matrix 28 + items: 29 + items: 30 + - description: SPI interrupt base 31 + - description: Number of interrupts in the range 32 + 33 + msi-controller: true 34 + 35 + required: 36 + - compatible 37 + - reg 38 + - msi-controller 39 + - marvell,spi-ranges 40 + 41 + additionalProperties: false 42 + 43 + examples: 44 + - | 45 + msi-controller@3f0040 { 46 + compatible = "marvell,ap806-gicp"; 47 + reg = <0x3f0040 0x10>; 48 + marvell,spi-ranges = <64 64>, <288 64>; 49 + msi-controller; 50 + };
-27
Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
··· 1 - Marvell GICP Controller 2 - ----------------------- 3 - 4 - GICP is a Marvell extension of the GIC that allows to trigger GIC SPI 5 - interrupts by doing a memory transaction. It is used by the ICU 6 - located in the Marvell CP110 to turn wired interrupts inside the CP 7 - into GIC SPI interrupts. 8 - 9 - Required properties: 10 - 11 - - compatible: Must be "marvell,ap806-gicp" 12 - 13 - - reg: Must be the address and size of the GICP SPI registers 14 - 15 - - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available 16 - for this GICP 17 - 18 - - msi-controller: indicates that this is an MSI controller 19 - 20 - Example: 21 - 22 - gicp_spi: gicp-spi@3f0040 { 23 - compatible = "marvell,ap806-gicp"; 24 - reg = <0x3f0040 0x10>; 25 - marvell,spi-ranges = <64 64>, <288 64>; 26 - msi-controller; 27 - };