Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: qcom: mmcc-msm8994: Add MSM8992 support

MSM8992 features less clocks & GDSCS and has different
freq tables for some of them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210618111435.595689-3-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Konrad Dybcio and committed by
Stephen Boyd
e0be9986 4d5b4572

+126
+126
drivers/clk/qcom/mmcc-msm8994.c
··· 329 329 { } 330 330 }; 331 331 332 + static const struct freq_tbl ftbl_axi_clk_src_8992[] = { 333 + F(75000000, P_GPLL0, 8, 0, 0), 334 + F(150000000, P_GPLL0, 4, 0, 0), 335 + F(300000000, P_GPLL0, 2, 0, 0), 336 + F(404000000, P_MMPLL1, 2, 0, 0), 337 + { } 338 + }; 339 + 332 340 static struct clk_rcg2 axi_clk_src = { 333 341 .cmd_rcgr = 0x5040, 334 342 .hid_width = 5, ··· 353 345 static const struct freq_tbl ftbl_csi0_1_2_3_clk_src[] = { 354 346 F(100000000, P_GPLL0, 6, 0, 0), 355 347 F(240000000, P_GPLL0, 2.5, 0, 0), 348 + F(266670000, P_MMPLL0, 3, 0, 0), 349 + { } 350 + }; 351 + 352 + static const struct freq_tbl ftbl_csi0_1_2_3_clk_src_8992[] = { 353 + F(100000000, P_GPLL0, 6, 0, 0), 356 354 F(266670000, P_MMPLL0, 3, 0, 0), 357 355 { } 358 356 }; ··· 384 370 F(200000000, P_MMPLL0, 4, 0, 0), 385 371 F(240000000, P_GPLL0, 2.5, 0, 0), 386 372 F(266670000, P_MMPLL0, 3, 0, 0), 373 + F(320000000, P_MMPLL0, 2.5, 0, 0), 374 + F(510000000, P_MMPLL3, 2, 0, 0), 375 + { } 376 + }; 377 + 378 + static const struct freq_tbl ftbl_vcodec0_clk_src_8992[] = { 379 + F(66670000, P_GPLL0, 9, 0, 0), 380 + F(100000000, P_GPLL0, 6, 0, 0), 381 + F(133330000, P_GPLL0, 4.5, 0, 0), 382 + F(200000000, P_MMPLL0, 4, 0, 0), 387 383 F(320000000, P_MMPLL0, 2.5, 0, 0), 388 384 F(510000000, P_MMPLL3, 2, 0, 0), 389 385 { } ··· 464 440 { } 465 441 }; 466 442 443 + static const struct freq_tbl ftbl_vfe0_1_clk_src_8992[] = { 444 + F(80000000, P_GPLL0, 7.5, 0, 0), 445 + F(100000000, P_GPLL0, 6, 0, 0), 446 + F(200000000, P_GPLL0, 3, 0, 0), 447 + F(320000000, P_MMPLL0, 2.5, 0, 0), 448 + F(480000000, P_MMPLL4, 2, 0, 0), 449 + F(600000000, P_GPLL0, 1, 0, 0), 450 + { } 451 + }; 452 + 467 453 static struct clk_rcg2 vfe0_clk_src = { 468 454 .cmd_rcgr = 0x3600, 469 455 .hid_width = 5, ··· 516 482 F(320000000, P_MMPLL0, 2.5, 0, 0), 517 483 F(480000000, P_MMPLL4, 2, 0, 0), 518 484 F(600000000, P_GPLL0, 1, 0, 0), 485 + F(640000000, P_MMPLL4, 1.5, 0, 0), 486 + { } 487 + }; 488 + 489 + static const struct freq_tbl ftbl_cpp_clk_src_8992[] = { 490 + F(100000000, P_GPLL0, 6, 0, 0), 491 + F(200000000, P_GPLL0, 3, 0, 0), 492 + F(320000000, P_MMPLL0, 2.5, 0, 0), 493 + F(480000000, P_MMPLL4, 2, 0, 0), 519 494 F(640000000, P_MMPLL4, 1.5, 0, 0), 520 495 { } 521 496 }; ··· 644 601 { } 645 602 }; 646 603 604 + static const struct freq_tbl ftbl_mdp_clk_src_8992[] = { 605 + F(85710000, P_GPLL0, 7, 0, 0), 606 + F(171430000, P_GPLL0, 3.5, 0, 0), 607 + F(200000000, P_GPLL0, 3, 0, 0), 608 + F(240000000, P_GPLL0, 2.5, 0, 0), 609 + F(266670000, P_MMPLL0, 3, 0, 0), 610 + F(320000000, P_MMPLL0, 2.5, 0, 0), 611 + F(400000000, P_MMPLL0, 2, 0, 0), 612 + { } 613 + }; 614 + 647 615 static struct clk_rcg2 mdp_clk_src = { 648 616 .cmd_rcgr = 0x2040, 649 617 .hid_width = 5, ··· 703 649 F(150000000, P_GPLL0, 4, 0, 0), 704 650 F(228570000, P_MMPLL0, 3.5, 0, 0), 705 651 F(266670000, P_MMPLL0, 3, 0, 0), 652 + F(320000000, P_MMPLL0, 2.5, 0, 0), 653 + F(400000000, P_MMPLL0, 2, 0, 0), 654 + { } 655 + }; 656 + 657 + static const struct freq_tbl ftbl_ocmemnoc_clk_src_8992[] = { 658 + F(19200000, P_XO, 1, 0, 0), 659 + F(75000000, P_GPLL0, 8, 0, 0), 660 + F(100000000, P_GPLL0, 6, 0, 0), 661 + F(150000000, P_GPLL0, 4, 0, 0), 706 662 F(320000000, P_MMPLL0, 2.5, 0, 0), 707 663 F(400000000, P_MMPLL0, 2, 0, 0), 708 664 { } ··· 828 764 F(32000000, P_MMPLL0, 5, 1, 5), 829 765 F(48000000, P_GPLL0, 12.5, 0, 0), 830 766 F(64000000, P_MMPLL0, 12.5, 0, 0), 767 + { } 768 + }; 769 + 770 + static const struct freq_tbl ftbl_mclk0_clk_src_8992[] = { 771 + F(4800000, P_XO, 4, 0, 0), 772 + F(6000000, P_MMPLL4, 10, 1, 16), 773 + F(8000000, P_MMPLL4, 10, 1, 12), 774 + F(9600000, P_XO, 2, 0, 0), 775 + F(12000000, P_MMPLL4, 10, 1, 8), 776 + F(16000000, P_MMPLL4, 10, 1, 6), 777 + F(19200000, P_XO, 1, 0, 0), 778 + F(24000000, P_MMPLL4, 10, 1, 4), 779 + F(32000000, P_MMPLL4, 10, 1, 3), 780 + F(48000000, P_MMPLL4, 10, 1, 2), 781 + F(64000000, P_MMPLL4, 15, 0, 0), 782 + { } 783 + }; 784 + 785 + static const struct freq_tbl ftbl_mclk1_2_3_clk_src_8992[] = { 786 + F(4800000, P_XO, 4, 0, 0), 787 + F(6000000, P_MMPLL4, 10, 1, 16), 788 + F(8000000, P_MMPLL4, 10, 1, 12), 789 + F(9600000, P_XO, 2, 0, 0), 790 + F(16000000, P_MMPLL4, 10, 1, 6), 791 + F(19200000, P_XO, 1, 0, 0), 792 + F(24000000, P_MMPLL4, 10, 1, 4), 793 + F(32000000, P_MMPLL4, 10, 1, 3), 794 + F(48000000, P_MMPLL4, 10, 1, 2), 795 + F(64000000, P_MMPLL4, 15, 0, 0), 831 796 { } 832 797 }; 833 798 ··· 2560 2467 static int mmcc_msm8994_probe(struct platform_device *pdev) 2561 2468 { 2562 2469 struct regmap *regmap; 2470 + 2471 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,mmcc-msm8992")) { 2472 + /* MSM8992 features less clocks and some have different freq tables */ 2473 + mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG1_CLK] = NULL; 2474 + mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG2_CLK] = NULL; 2475 + mmcc_msm8994_desc.clks[FD_CORE_CLK_SRC] = NULL; 2476 + mmcc_msm8994_desc.clks[FD_CORE_CLK] = NULL; 2477 + mmcc_msm8994_desc.clks[FD_CORE_UAR_CLK] = NULL; 2478 + mmcc_msm8994_desc.clks[FD_AXI_CLK] = NULL; 2479 + mmcc_msm8994_desc.clks[FD_AHB_CLK] = NULL; 2480 + mmcc_msm8994_desc.clks[JPEG1_CLK_SRC] = NULL; 2481 + mmcc_msm8994_desc.clks[JPEG2_CLK_SRC] = NULL; 2482 + mmcc_msm8994_desc.clks[VENUS0_CORE2_VCODEC_CLK] = NULL; 2483 + 2484 + mmcc_msm8994_desc.gdscs[FD_GDSC] = NULL; 2485 + mmcc_msm8994_desc.gdscs[VENUS_CORE2_GDSC] = NULL; 2486 + 2487 + axi_clk_src.freq_tbl = ftbl_axi_clk_src_8992; 2488 + cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_8992; 2489 + csi0_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992; 2490 + csi1_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992; 2491 + csi2_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992; 2492 + csi3_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992; 2493 + mclk0_clk_src.freq_tbl = ftbl_mclk0_clk_src_8992; 2494 + mclk1_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992; 2495 + mclk2_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992; 2496 + mclk3_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992; 2497 + mdp_clk_src.freq_tbl = ftbl_mdp_clk_src_8992; 2498 + ocmemnoc_clk_src.freq_tbl = ftbl_ocmemnoc_clk_src_8992; 2499 + vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_8992; 2500 + vfe0_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992; 2501 + vfe1_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992; 2502 + } 2563 2503 2564 2504 regmap = qcom_cc_map(pdev, &mmcc_msm8994_desc); 2565 2505 if (IS_ERR(regmap))