Merge tag 'sunxi-core-for-3.13' of https://github.com/mripard/linux into next/soc

+25 -1

Documentation/arm/sunxi/README

··· 10 10 Linux kernel mach directory: arch/arm/mach-sunxi 11 11 12 12 Flavors: 13 + * ARM926 based SoCs 14 + - Allwinner F20 (sun3i) 15 + + Not Supported 16 + 13 17 * ARM Cortex-A8 based SoCs 14 18 - Allwinner A10 (sun4i) 15 19 + Datasheet ··· 29 25 + Datasheet 30 26 http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf 31 27 + User Manual 32 - http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-08-08%29.pdf 28 + http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-01-08%29.pdf 29 + 30 + * Dual ARM Cortex-A7 based SoCs 31 + - Allwinner A20 (sun7i) 32 + + User Manual 33 + http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf 34 + 35 + - Allwinner A23 36 + + Not Supported 37 + 38 + * Quad ARM Cortex-A7 based SoCs 39 + - Allwinner A31 (sun6i) 40 + + Datasheet 41 + http://dl.linux-sunxi.org/A31/A31%20Datasheet%20-%20v1.00%20(2012-12-24).pdf 42 + 43 + - Allwinner A31s (sun6i) 44 + + Not Supported 45 + 46 + * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs 47 + - Allwinner A80 48 + + Not Supported

+2 -2

Documentation/devicetree/bindings/clock/sunxi.txt

··· 45 45 46 46 Clock consumers should specify the desired clocks they use with a 47 47 "clocks" phandle cell. Consumers that are using a gated clock should 48 - provide an additional ID in their clock property. The values of this 49 - ID are documented in sunxi/<soc>-gates.txt. 48 + provide an additional ID in their clock property. This ID is the 49 + offset of the bit controlling this particular gate in the register. 50 50 51 51 For example: 52 52

-93

Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt

··· 1 - Gate clock outputs 2 - ------------------ 3 - 4 - * AXI gates ("allwinner,sun4i-axi-gates-clk") 5 - 6 - DRAM 0 7 - 8 - * AHB gates ("allwinner,sun4i-ahb-gates-clk") 9 - 10 - USB0 0 11 - EHCI0 1 12 - OHCI0 2* 13 - EHCI1 3 14 - OHCI1 4* 15 - SS 5 16 - DMA 6 17 - BIST 7 18 - MMC0 8 19 - MMC1 9 20 - MMC2 10 21 - MMC3 11 22 - MS 12** 23 - NAND 13 24 - SDRAM 14 25 - 26 - ACE 16 27 - EMAC 17 28 - TS 18 29 - 30 - SPI0 20 31 - SPI1 21 32 - SPI2 22 33 - SPI3 23 34 - PATA 24 35 - SATA 25** 36 - GPS 26* 37 - 38 - VE 32 39 - TVD 33 40 - TVE0 34 41 - TVE1 35 42 - LCD0 36 43 - LCD1 37 44 - 45 - CSI0 40 46 - CSI1 41 47 - 48 - HDMI 43 49 - DE_BE0 44 50 - DE_BE1 45 51 - DE_FE1 46 52 - DE_FE1 47 53 - 54 - MP 50 55 - 56 - MALI400 52 57 - 58 - * APB0 gates ("allwinner,sun4i-apb0-gates-clk") 59 - 60 - CODEC 0 61 - SPDIF 1* 62 - AC97 2 63 - IIS 3 64 - 65 - PIO 5 66 - IR0 6 67 - IR1 7 68 - 69 - KEYPAD 10 70 - 71 - * APB1 gates ("allwinner,sun4i-apb1-gates-clk") 72 - 73 - I2C0 0 74 - I2C1 1 75 - I2C2 2 76 - 77 - CAN 4 78 - SCR 5 79 - PS20 6 80 - PS21 7 81 - 82 - UART0 16 83 - UART1 17 84 - UART2 18 85 - UART3 19 86 - UART4 20 87 - UART5 21 88 - UART6 22 89 - UART7 23 90 - 91 - Notation: 92 - [*]: The datasheet didn't mention these, but they are present on AW code 93 - [**]: The datasheet had this marked as "NC" but they are used on AW code

-75

Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt

··· 1 - Gate clock outputs 2 - ------------------ 3 - 4 - * AXI gates ("allwinner,sun4i-axi-gates-clk") 5 - 6 - DRAM 0 7 - 8 - * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk") 9 - 10 - USB0 0 11 - EHCI0 1 12 - OHCI0 2 13 - 14 - SS 5 15 - DMA 6 16 - BIST 7 17 - MMC0 8 18 - MMC1 9 19 - MMC2 10 20 - 21 - NAND 13 22 - SDRAM 14 23 - 24 - EMAC 17 25 - TS 18 26 - 27 - SPI0 20 28 - SPI1 21 29 - SPI2 22 30 - 31 - GPS 26 32 - 33 - HSTIMER 28 34 - 35 - VE 32 36 - 37 - TVE 34 38 - 39 - LCD 36 40 - 41 - CSI 40 42 - 43 - HDMI 43 44 - DE_BE 44 45 - 46 - DE_FE 46 47 - 48 - IEP 51 49 - MALI400 52 50 - 51 - * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk") 52 - 53 - CODEC 0 54 - 55 - IIS 3 56 - 57 - PIO 5 58 - IR 6 59 - 60 - KEYPAD 10 61 - 62 - * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk") 63 - 64 - I2C0 0 65 - I2C1 1 66 - I2C2 2 67 - 68 - UART0 16 69 - UART1 17 70 - UART2 18 71 - UART3 19 72 - 73 - Notation: 74 - [*]: The datasheet didn't mention these, but they are present on AW code 75 - [**]: The datasheet had this marked as "NC" but they are used on AW code

-58

Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt

··· 1 - Gate clock outputs 2 - ------------------ 3 - 4 - * AXI gates ("allwinner,sun4i-axi-gates-clk") 5 - 6 - DRAM 0 7 - 8 - * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk") 9 - 10 - USBOTG 0 11 - EHCI 1 12 - OHCI 2 13 - 14 - SS 5 15 - DMA 6 16 - BIST 7 17 - MMC0 8 18 - MMC1 9 19 - MMC2 10 20 - 21 - NAND 13 22 - SDRAM 14 23 - 24 - SPI0 20 25 - SPI1 21 26 - SPI2 22 27 - 28 - STIMER 28 29 - 30 - VE 32 31 - 32 - LCD 36 33 - 34 - CSI 40 35 - 36 - DE_BE 44 37 - 38 - DE_FE 46 39 - 40 - IEP 51 41 - MALI400 52 42 - 43 - * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk") 44 - 45 - CODEC 0 46 - 47 - PIO 5 48 - IR 6 49 - 50 - * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk") 51 - 52 - I2C0 0 53 - I2C1 1 54 - I2C2 2 55 - 56 - UART1 17 57 - 58 - UART3 19

-83

Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt

··· 1 - Gate clock outputs 2 - ------------------ 3 - 4 - * AHB1 gates ("allwinner,sun6i-a31-ahb1-gates-clk") 5 - 6 - MIPI DSI 1 7 - 8 - SS 5 9 - DMA 6 10 - 11 - MMC0 8 12 - MMC1 9 13 - MMC2 10 14 - MMC3 11 15 - 16 - NAND1 12 17 - NAND0 13 18 - SDRAM 14 19 - 20 - GMAC 17 21 - TS 18 22 - HSTIMER 19 23 - SPI0 20 24 - SPI1 21 25 - SPI2 22 26 - SPI3 23 27 - USB_OTG 24 28 - 29 - EHCI0 26 30 - EHCI1 27 31 - 32 - OHCI0 29 33 - OHCI1 30 34 - OHCI2 31 35 - VE 32 36 - 37 - LCD0 36 38 - LCD1 37 39 - 40 - CSI 40 41 - 42 - HDMI 43 43 - DE_BE0 44 44 - DE_BE1 45 45 - DE_FE1 46 46 - DE_FE1 47 47 - 48 - MP 50 49 - 50 - GPU 52 51 - 52 - DEU0 55 53 - DEU1 56 54 - DRC0 57 55 - DRC1 58 56 - 57 - * APB1 gates ("allwinner,sun6i-a31-apb1-gates-clk") 58 - 59 - CODEC 0 60 - 61 - DIGITAL MIC 4 62 - PIO 5 63 - 64 - DAUDIO0 12 65 - DAUDIO1 13 66 - 67 - * APB2 gates ("allwinner,sun6i-a31-apb2-gates-clk") 68 - 69 - I2C0 0 70 - I2C1 1 71 - I2C2 2 72 - I2C3 3 73 - 74 - UART0 16 75 - UART1 17 76 - UART2 18 77 - UART3 19 78 - UART4 20 79 - UART5 21 80 - 81 - Notation: 82 - [*]: The datasheet didn't mention these, but they are present on AW code 83 - [**]: The datasheet had this marked as "NC" but they are used on AW code

-98

Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt

··· 1 - Gate clock outputs 2 - ------------------ 3 - 4 - * AXI gates ("allwinner,sun4i-axi-gates-clk") 5 - 6 - DRAM 0 7 - 8 - * AHB gates ("allwinner,sun7i-a20-ahb-gates-clk") 9 - 10 - USB0 0 11 - EHCI0 1 12 - OHCI0 2 13 - EHCI1 3 14 - OHCI1 4 15 - SS 5 16 - DMA 6 17 - BIST 7 18 - MMC0 8 19 - MMC1 9 20 - MMC2 10 21 - MMC3 11 22 - MS 12 23 - NAND 13 24 - SDRAM 14 25 - 26 - ACE 16 27 - EMAC 17 28 - TS 18 29 - 30 - SPI0 20 31 - SPI1 21 32 - SPI2 22 33 - SPI3 23 34 - 35 - SATA 25 36 - 37 - HSTIMER 28 38 - 39 - VE 32 40 - TVD 33 41 - TVE0 34 42 - TVE1 35 43 - LCD0 36 44 - LCD1 37 45 - 46 - CSI0 40 47 - CSI1 41 48 - 49 - HDMI1 42 50 - HDMI0 43 51 - DE_BE0 44 52 - DE_BE1 45 53 - DE_FE1 46 54 - DE_FE1 47 55 - 56 - GMAC 49 57 - MP 50 58 - 59 - MALI400 52 60 - 61 - * APB0 gates ("allwinner,sun7i-a20-apb0-gates-clk") 62 - 63 - CODEC 0 64 - SPDIF 1 65 - AC97 2 66 - IIS0 3 67 - IIS1 4 68 - PIO 5 69 - IR0 6 70 - IR1 7 71 - IIS2 8 72 - 73 - KEYPAD 10 74 - 75 - * APB1 gates ("allwinner,sun7i-a20-apb1-gates-clk") 76 - 77 - I2C0 0 78 - I2C1 1 79 - I2C2 2 80 - I2C3 3 81 - CAN 4 82 - SCR 5 83 - PS20 6 84 - PS21 7 85 - 86 - I2C4 15 87 - UART0 16 88 - UART1 17 89 - UART2 18 90 - UART3 19 91 - UART4 20 92 - UART5 21 93 - UART6 22 94 - UART7 23 95 - 96 - Notation: 97 - [*]: The datasheet didn't mention these, but they are present on AW code 98 - [**]: The datasheet had this marked as "NC" but they are used on AW code

-3

Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt

··· 8 8 - #interrupt-cells : Specifies the number of cells needed to encode an 9 9 interrupt source. The value shall be 1. 10 10 11 - For the valid interrupt sources for your SoC, see the documentation in 12 - sunxi/<soc>.txt 13 - 14 11 Example: 15 12 16 13 intc: interrupt-controller {

-89

Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt

··· 1 - Allwinner A10 (sun4i) interrupt sources 2 - --------------------------------------- 3 - 4 - The interrupt sources available for the Allwinner A10 SoC are the 5 - following one: 6 - 7 - 0: ENMI 8 - 1: UART0 9 - 2: UART1 10 - 3: UART2 11 - 4: UART3 12 - 5: IR0 13 - 6: IR1 14 - 7: I2C0 15 - 8: I2C1 16 - 9: I2C2 17 - 10: SPI0 18 - 11: SPI1 19 - 12: SPI2 20 - 13: SPDIF 21 - 14: AC97 22 - 15: TS 23 - 16: I2S 24 - 17: UART4 25 - 18: UART5 26 - 19: UART6 27 - 20: UART7 28 - 21: KEYPAD 29 - 22: TIMER0 30 - 23: TIMER1 31 - 24: TIMER2 32 - 25: TIMER3 33 - 26: CAN 34 - 27: DMA 35 - 28: PIO 36 - 29: TOUCH_PANEL 37 - 30: AUDIO_CODEC 38 - 31: LRADC 39 - 32: MMC0 40 - 33: MMC1 41 - 34: MMC2 42 - 35: MMC3 43 - 36: MEMSTICK 44 - 37: NAND 45 - 38: USB0 46 - 39: USB1 47 - 40: USB2 48 - 41: SCR 49 - 42: CSI0 50 - 43: CSI1 51 - 44: LCDCTRL0 52 - 45: LCDCTRL1 53 - 46: MP 54 - 47: DEFEBE0 55 - 48: DEFEBE1 56 - 49: PMU 57 - 50: SPI3 58 - 51: TZASC 59 - 52: PATA 60 - 53: VE 61 - 54: SS 62 - 55: EMAC 63 - 56: SATA 64 - 57: GPS 65 - 58: HDMI 66 - 59: TVE 67 - 60: ACE 68 - 61: TVD 69 - 62: PS2_0 70 - 63: PS2_1 71 - 64: USB3 72 - 65: USB4 73 - 66: PLE_PFM 74 - 67: TIMER4 75 - 68: TIMER5 76 - 69: GPU_GP 77 - 70: GPU_GPMMU 78 - 71: GPU_PP0 79 - 72: GPU_PPMMU0 80 - 73: GPU_PMU 81 - 74: GPU_RSV0 82 - 75: GPU_RSV1 83 - 76: GPU_RSV2 84 - 77: GPU_RSV3 85 - 78: GPU_RSV4 86 - 79: GPU_RSV5 87 - 80: GPU_RSV6 88 - 82: SYNC_TIMER0 89 - 83: SYNC_TIMER1

-55

Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt

··· 1 - Allwinner A13 (sun5i) interrupt sources 2 - --------------------------------------- 3 - 4 - The interrupt sources available for the Allwinner A13 SoC are the 5 - following one: 6 - 7 - 0: ENMI 8 - 2: UART1 9 - 4: UART3 10 - 5: IR 11 - 7: I2C0 12 - 8: I2C1 13 - 9: I2C2 14 - 10: SPI0 15 - 11: SPI1 16 - 12: SPI2 17 - 22: TIMER0 18 - 23: TIMER1 19 - 24: TIMER2 20 - 25: TIMER3 21 - 27: DMA 22 - 28: PIO 23 - 29: TOUCH_PANEL 24 - 30: AUDIO_CODEC 25 - 31: LRADC 26 - 32: MMC0 27 - 33: MMC1 28 - 34: MMC2 29 - 37: NAND 30 - 38: USB OTG 31 - 39: USB EHCI 32 - 40: USB OHCI 33 - 42: CSI 34 - 44: LCDCTRL 35 - 47: DEFEBE 36 - 49: PMU 37 - 53: VE 38 - 54: SS 39 - 66: PLE_PFM 40 - 67: TIMER4 41 - 68: TIMER5 42 - 69: GPU_GP 43 - 70: GPU_GPMMU 44 - 71: GPU_PP0 45 - 72: GPU_PPMMU0 46 - 73: GPU_PMU 47 - 74: GPU_RSV0 48 - 75: GPU_RSV1 49 - 76: GPU_RSV2 50 - 77: GPU_RSV3 51 - 78: GPU_RSV4 52 - 79: GPU_RSV5 53 - 80: GPU_RSV6 54 - 82: SYNC_TIMER0 55 - 83: SYNC_TIMER1

+3 -3

arch/arm/mach-sunxi/Kconfig

··· 1 1 config ARCH_SUNXI 2 2 bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 3 3 select ARCH_REQUIRE_GPIOLIB 4 + select ARM_GIC 4 5 select CLKSRC_MMIO 5 6 select CLKSRC_OF 6 7 select COMMON_CLK 7 8 select GENERIC_CLOCKEVENTS 8 9 select GENERIC_IRQ_CHIP 10 + select HAVE_SMP 9 11 select PINCTRL 12 + select PINCTRL_SUNXI 10 13 select SPARSE_IRQ 11 14 select SUN4I_TIMER 12 - select PINCTRL_SUNXI 13 - select ARM_GIC 14 - select HAVE_SMP

+27 -10

arch/arm/mach-sunxi/sunxi.c

··· 90 90 } 91 91 92 92 static struct of_device_id sunxi_restart_ids[] = { 93 - { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, 94 - { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart }, 93 + { .compatible = "allwinner,sun4i-wdt" }, 94 + { .compatible = "allwinner,sun6i-wdt" }, 95 95 { /*sentinel*/ } 96 96 }; 97 97 98 98 static void sunxi_setup_restart(void) 99 99 { 100 - const struct of_device_id *of_id; 101 100 struct device_node *np; 102 101 103 102 np = of_find_matching_node(NULL, sunxi_restart_ids); ··· 105 106 106 107 wdt_base = of_iomap(np, 0); 107 108 WARN(!wdt_base, "failed to map watchdog base address"); 108 - 109 - of_id = of_match_node(sunxi_restart_ids, np); 110 - WARN(!of_id, "restart function not available"); 111 - 112 - arm_pm_restart = of_id->data; 113 109 } 114 110 115 111 static void __init sunxi_dt_init(void) ··· 118 124 "allwinner,sun4i-a10", 119 125 "allwinner,sun5i-a10s", 120 126 "allwinner,sun5i-a13", 121 - "allwinner,sun6i-a31", 122 - "allwinner,sun7i-a20", 123 127 NULL, 124 128 }; 125 129 126 130 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") 127 131 .init_machine = sunxi_dt_init, 128 132 .dt_compat = sunxi_board_dt_compat, 133 + .restart = sun4i_restart, 134 + MACHINE_END 135 + 136 + static const char * const sun6i_board_dt_compat[] = { 137 + "allwinner,sun6i-a31", 138 + NULL, 139 + }; 140 + 141 + DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") 142 + .init_machine = sunxi_dt_init, 143 + .init_time = sunxi_timer_init, 144 + .dt_compat = sun6i_board_dt_compat, 145 + .restart = sun6i_restart, 146 + MACHINE_END 147 + 148 + static const char * const sun7i_board_dt_compat[] = { 149 + "allwinner,sun7i-a20", 150 + NULL, 151 + }; 152 + 153 + DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") 154 + .init_machine = sunxi_dt_init, 155 + .init_time = sunxi_timer_init, 156 + .dt_compat = sun7i_board_dt_compat, 157 + .restart = sun4i_restart, 129 158 MACHINE_END