commit e07cd2f3e7e525fa8df334d11beceb4c1bdcc74e · tjh.dev/kernel

+3 -1

MAINTAINERS

··· 9240 9240 K: \bSGX_ 9241 9241 9242 9242 INTERCONNECT API 9243 - M: Georgi Djakov <georgi.djakov@linaro.org> 9243 + M: Georgi Djakov <djakov@kernel.org> 9244 9244 L: linux-pm@vger.kernel.org 9245 9245 S: Maintained 9246 9246 F: Documentation/devicetree/bindings/interconnect/ ··· 16709 16709 L: speakup@linux-speakup.org 16710 16710 S: Odd Fixes 16711 16711 W: http://www.linux-speakup.org/ 16712 + W: https://github.com/linux-speakup/speakup 16713 + B: https://github.com/linux-speakup/speakup/issues 16712 16714 F: drivers/accessibility/speakup/ 16713 16715 16714 16716 SPEAR CLOCK FRAMEWORK SUPPORT

+1 -1

crypto/asymmetric_keys/asym_tpm.c

··· 354 354 memcpy(cur, e, sizeof(e)); 355 355 cur += sizeof(e); 356 356 /* Zero parameters to satisfy set_pub_key ABI. */ 357 - memset(cur, 0, SETKEY_PARAMS_SIZE); 357 + memzero_explicit(cur, SETKEY_PARAMS_SIZE); 358 358 359 359 return cur - buf; 360 360 }

+2 -1

drivers/interconnect/imx/imx.c

··· 96 96 return -ENODEV; 97 97 } 98 98 /* Allow scaling to be disabled on a per-node basis */ 99 - if (!dn || !of_device_is_available(dn)) { 99 + if (!of_device_is_available(dn)) { 100 100 dev_warn(dev, "Missing property %s, skip scaling %s\n", 101 101 adj->phandle_name, node->name); 102 + of_node_put(dn); 102 103 return 0; 103 104 } 104 105

+2

drivers/interconnect/imx/imx8mq.c

··· 7 7 8 8 #include <linux/module.h> 9 9 #include <linux/platform_device.h> 10 + #include <linux/interconnect-provider.h> 10 11 #include <dt-bindings/interconnect/imx8mq.h> 11 12 12 13 #include "imx.h" ··· 95 94 .remove = imx8mq_icc_remove, 96 95 .driver = { 97 96 .name = "imx8mq-interconnect", 97 + .sync_state = icc_sync_state, 98 98 }, 99 99 }; 100 100

+15 -8

drivers/interconnect/qcom/Kconfig

··· 42 42 This is a driver for the Qualcomm Network-on-Chip on qcs404-based 43 43 platforms. 44 44 45 + config INTERCONNECT_QCOM_RPMH_POSSIBLE 46 + tristate 47 + default INTERCONNECT_QCOM 48 + depends on QCOM_RPMH || (COMPILE_TEST && !QCOM_RPMH) 49 + depends on QCOM_COMMAND_DB || (COMPILE_TEST && !QCOM_COMMAND_DB) 50 + depends on OF || COMPILE_TEST 51 + help 52 + Compile-testing RPMH drivers is possible on other platforms, 53 + but in order to avoid link failures, drivers must not be built-in 54 + when QCOM_RPMH or QCOM_COMMAND_DB are loadable modules 55 + 45 56 config INTERCONNECT_QCOM_RPMH 46 57 tristate 47 58 48 59 config INTERCONNECT_QCOM_SC7180 49 60 tristate "Qualcomm SC7180 interconnect driver" 50 - depends on INTERCONNECT_QCOM 51 - depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST 61 + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE 52 62 select INTERCONNECT_QCOM_RPMH 53 63 select INTERCONNECT_QCOM_BCM_VOTER 54 64 help ··· 67 57 68 58 config INTERCONNECT_QCOM_SDM845 69 59 tristate "Qualcomm SDM845 interconnect driver" 70 - depends on INTERCONNECT_QCOM 71 - depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST 60 + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE 72 61 select INTERCONNECT_QCOM_RPMH 73 62 select INTERCONNECT_QCOM_BCM_VOTER 74 63 help ··· 76 67 77 68 config INTERCONNECT_QCOM_SM8150 78 69 tristate "Qualcomm SM8150 interconnect driver" 79 - depends on INTERCONNECT_QCOM 80 - depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST 70 + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE 81 71 select INTERCONNECT_QCOM_RPMH 82 72 select INTERCONNECT_QCOM_BCM_VOTER 83 73 help ··· 85 77 86 78 config INTERCONNECT_QCOM_SM8250 87 79 tristate "Qualcomm SM8250 interconnect driver" 88 - depends on INTERCONNECT_QCOM 89 - depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST 80 + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE 90 81 select INTERCONNECT_QCOM_RPMH 91 82 select INTERCONNECT_QCOM_BCM_VOTER 92 83 help

+58 -19

drivers/misc/habanalabs/common/command_submission.c

··· 472 472 cntr = &hdev->aggregated_cs_counters; 473 473 474 474 cs = kzalloc(sizeof(*cs), GFP_ATOMIC); 475 - if (!cs) 475 + if (!cs) { 476 + atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt); 477 + atomic64_inc(&cntr->out_of_mem_drop_cnt); 476 478 return -ENOMEM; 479 + } 477 480 478 481 cs->ctx = ctx; 479 482 cs->submitted = false; ··· 489 486 490 487 cs_cmpl = kmalloc(sizeof(*cs_cmpl), GFP_ATOMIC); 491 488 if (!cs_cmpl) { 489 + atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt); 490 + atomic64_inc(&cntr->out_of_mem_drop_cnt); 492 491 rc = -ENOMEM; 493 492 goto free_cs; 494 493 } ··· 518 513 cs->jobs_in_queue_cnt = kcalloc(hdev->asic_prop.max_queues, 519 514 sizeof(*cs->jobs_in_queue_cnt), GFP_ATOMIC); 520 515 if (!cs->jobs_in_queue_cnt) { 516 + atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt); 517 + atomic64_inc(&cntr->out_of_mem_drop_cnt); 521 518 rc = -ENOMEM; 522 519 goto free_fence; 523 520 } ··· 569 562 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) 570 563 flush_workqueue(hdev->cq_wq[i]); 571 564 572 - /* Make sure we don't have leftovers in the H/W queues mirror list */ 565 + /* Make sure we don't have leftovers in the CS mirror list */ 573 566 list_for_each_entry_safe(cs, tmp, &hdev->cs_mirror_list, mirror_node) { 574 567 cs_get(cs); 575 568 cs->aborted = true; ··· 771 764 772 765 static int hl_cs_copy_chunk_array(struct hl_device *hdev, 773 766 struct hl_cs_chunk **cs_chunk_array, 774 - void __user *chunks, u32 num_chunks) 767 + void __user *chunks, u32 num_chunks, 768 + struct hl_ctx *ctx) 775 769 { 776 770 u32 size_to_copy; 777 771 778 772 if (num_chunks > HL_MAX_JOBS_PER_CS) { 773 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 774 + atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt); 779 775 dev_err(hdev->dev, 780 776 "Number of chunks can NOT be larger than %d\n", 781 777 HL_MAX_JOBS_PER_CS); ··· 787 777 788 778 *cs_chunk_array = kmalloc_array(num_chunks, sizeof(**cs_chunk_array), 789 779 GFP_ATOMIC); 790 - if (!*cs_chunk_array) 780 + if (!*cs_chunk_array) { 781 + atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt); 782 + atomic64_inc(&hdev->aggregated_cs_counters.out_of_mem_drop_cnt); 791 783 return -ENOMEM; 784 + } 792 785 793 786 size_to_copy = num_chunks * sizeof(struct hl_cs_chunk); 794 787 if (copy_from_user(*cs_chunk_array, chunks, size_to_copy)) { 788 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 789 + atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt); 795 790 dev_err(hdev->dev, "Failed to copy cs chunk array from user\n"); 796 791 kfree(*cs_chunk_array); 797 792 return -EFAULT; ··· 812 797 struct hl_device *hdev = hpriv->hdev; 813 798 struct hl_cs_chunk *cs_chunk_array; 814 799 struct hl_cs_counters_atomic *cntr; 800 + struct hl_ctx *ctx = hpriv->ctx; 815 801 struct hl_cs_job *job; 816 802 struct hl_cs *cs; 817 803 struct hl_cb *cb; ··· 821 805 cntr = &hdev->aggregated_cs_counters; 822 806 *cs_seq = ULLONG_MAX; 823 807 824 - rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks); 808 + rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks, 809 + hpriv->ctx); 825 810 if (rc) 826 811 goto out; 827 812 ··· 849 832 rc = validate_queue_index(hdev, chunk, &queue_type, 850 833 &is_kernel_allocated_cb); 851 834 if (rc) { 852 - atomic64_inc(&hpriv->ctx->cs_counters.parsing_drop_cnt); 853 - atomic64_inc(&cntr->parsing_drop_cnt); 835 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 836 + atomic64_inc(&cntr->validation_drop_cnt); 854 837 goto free_cs_object; 855 838 } 856 839 ··· 858 841 cb = get_cb_from_cs_chunk(hdev, &hpriv->cb_mgr, chunk); 859 842 if (!cb) { 860 843 atomic64_inc( 861 - &hpriv->ctx->cs_counters.parsing_drop_cnt); 862 - atomic64_inc(&cntr->parsing_drop_cnt); 844 + &ctx->cs_counters.validation_drop_cnt); 845 + atomic64_inc(&cntr->validation_drop_cnt); 863 846 rc = -EINVAL; 864 847 goto free_cs_object; 865 848 } ··· 873 856 job = hl_cs_allocate_job(hdev, queue_type, 874 857 is_kernel_allocated_cb); 875 858 if (!job) { 876 - atomic64_inc( 877 - &hpriv->ctx->cs_counters.out_of_mem_drop_cnt); 859 + atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt); 878 860 atomic64_inc(&cntr->out_of_mem_drop_cnt); 879 861 dev_err(hdev->dev, "Failed to allocate a new job\n"); 880 862 rc = -ENOMEM; ··· 907 891 908 892 rc = cs_parser(hpriv, job); 909 893 if (rc) { 910 - atomic64_inc(&hpriv->ctx->cs_counters.parsing_drop_cnt); 894 + atomic64_inc(&ctx->cs_counters.parsing_drop_cnt); 911 895 atomic64_inc(&cntr->parsing_drop_cnt); 912 896 dev_err(hdev->dev, 913 897 "Failed to parse JOB %d.%llu.%d, err %d, rejecting the CS\n", ··· 917 901 } 918 902 919 903 if (int_queues_only) { 920 - atomic64_inc(&hpriv->ctx->cs_counters.parsing_drop_cnt); 921 - atomic64_inc(&cntr->parsing_drop_cnt); 904 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 905 + atomic64_inc(&cntr->validation_drop_cnt); 922 906 dev_err(hdev->dev, 923 907 "Reject CS %d.%llu because only internal queues jobs are present\n", 924 908 cs->ctx->asid, cs->sequence); ··· 1058 1042 } 1059 1043 1060 1044 static int cs_ioctl_extract_signal_seq(struct hl_device *hdev, 1061 - struct hl_cs_chunk *chunk, u64 *signal_seq) 1045 + struct hl_cs_chunk *chunk, u64 *signal_seq, struct hl_ctx *ctx) 1062 1046 { 1063 1047 u64 *signal_seq_arr = NULL; 1064 1048 u32 size_to_copy, signal_seq_arr_len; ··· 1068 1052 1069 1053 /* currently only one signal seq is supported */ 1070 1054 if (signal_seq_arr_len != 1) { 1055 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 1056 + atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt); 1071 1057 dev_err(hdev->dev, 1072 1058 "Wait for signal CS supports only one signal CS seq\n"); 1073 1059 return -EINVAL; ··· 1078 1060 signal_seq_arr = kmalloc_array(signal_seq_arr_len, 1079 1061 sizeof(*signal_seq_arr), 1080 1062 GFP_ATOMIC); 1081 - if (!signal_seq_arr) 1063 + if (!signal_seq_arr) { 1064 + atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt); 1065 + atomic64_inc(&hdev->aggregated_cs_counters.out_of_mem_drop_cnt); 1082 1066 return -ENOMEM; 1067 + } 1083 1068 1084 1069 size_to_copy = chunk->num_signal_seq_arr * sizeof(*signal_seq_arr); 1085 1070 if (copy_from_user(signal_seq_arr, 1086 1071 u64_to_user_ptr(chunk->signal_seq_arr), 1087 1072 size_to_copy)) { 1073 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 1074 + atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt); 1088 1075 dev_err(hdev->dev, 1089 1076 "Failed to copy signal seq array from user\n"); 1090 1077 rc = -EFAULT; ··· 1176 1153 struct hl_device *hdev = hpriv->hdev; 1177 1154 struct hl_cs_compl *sig_waitcs_cmpl; 1178 1155 u32 q_idx, collective_engine_id = 0; 1156 + struct hl_cs_counters_atomic *cntr; 1179 1157 struct hl_fence *sig_fence = NULL; 1180 1158 struct hl_ctx *ctx = hpriv->ctx; 1181 1159 enum hl_queue_type q_type; ··· 1184 1160 u64 signal_seq; 1185 1161 int rc; 1186 1162 1163 + cntr = &hdev->aggregated_cs_counters; 1187 1164 *cs_seq = ULLONG_MAX; 1188 1165 1189 - rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks); 1166 + rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks, 1167 + ctx); 1190 1168 if (rc) 1191 1169 goto out; 1192 1170 ··· 1196 1170 chunk = &cs_chunk_array[0]; 1197 1171 1198 1172 if (chunk->queue_index >= hdev->asic_prop.max_queues) { 1173 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 1174 + atomic64_inc(&cntr->validation_drop_cnt); 1199 1175 dev_err(hdev->dev, "Queue index %d is invalid\n", 1200 1176 chunk->queue_index); 1201 1177 rc = -EINVAL; ··· 1209 1181 q_type = hw_queue_prop->type; 1210 1182 1211 1183 if (!hw_queue_prop->supports_sync_stream) { 1184 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 1185 + atomic64_inc(&cntr->validation_drop_cnt); 1212 1186 dev_err(hdev->dev, 1213 1187 "Queue index %d does not support sync stream operations\n", 1214 1188 q_idx); ··· 1220 1190 1221 1191 if (cs_type == CS_TYPE_COLLECTIVE_WAIT) { 1222 1192 if (!(hw_queue_prop->collective_mode == HL_COLLECTIVE_MASTER)) { 1193 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 1194 + atomic64_inc(&cntr->validation_drop_cnt); 1223 1195 dev_err(hdev->dev, 1224 1196 "Queue index %d is invalid\n", q_idx); 1225 1197 rc = -EINVAL; ··· 1232 1200 } 1233 1201 1234 1202 if (cs_type == CS_TYPE_WAIT || cs_type == CS_TYPE_COLLECTIVE_WAIT) { 1235 - rc = cs_ioctl_extract_signal_seq(hdev, chunk, &signal_seq); 1203 + rc = cs_ioctl_extract_signal_seq(hdev, chunk, &signal_seq, ctx); 1236 1204 if (rc) 1237 1205 goto free_cs_chunk_array; 1238 1206 1239 1207 sig_fence = hl_ctx_get_fence(ctx, signal_seq); 1240 1208 if (IS_ERR(sig_fence)) { 1209 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 1210 + atomic64_inc(&cntr->validation_drop_cnt); 1241 1211 dev_err(hdev->dev, 1242 1212 "Failed to get signal CS with seq 0x%llx\n", 1243 1213 signal_seq); ··· 1257 1223 container_of(sig_fence, struct hl_cs_compl, base_fence); 1258 1224 1259 1225 if (sig_waitcs_cmpl->type != CS_TYPE_SIGNAL) { 1226 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 1227 + atomic64_inc(&cntr->validation_drop_cnt); 1260 1228 dev_err(hdev->dev, 1261 1229 "CS seq 0x%llx is not of a signal CS\n", 1262 1230 signal_seq); ··· 1306 1270 else if (cs_type == CS_TYPE_COLLECTIVE_WAIT) 1307 1271 rc = hdev->asic_funcs->collective_wait_create_jobs(hdev, ctx, 1308 1272 cs, q_idx, collective_engine_id); 1309 - else 1273 + else { 1274 + atomic64_inc(&ctx->cs_counters.validation_drop_cnt); 1275 + atomic64_inc(&cntr->validation_drop_cnt); 1310 1276 rc = -EINVAL; 1277 + } 1311 1278 1312 1279 if (rc) 1313 1280 goto free_cs_object;

+5 -3

drivers/misc/habanalabs/common/device.c

··· 17 17 { 18 18 enum hl_device_status status; 19 19 20 - if (hdev->disabled) 21 - status = HL_DEVICE_STATUS_MALFUNCTION; 22 - else if (atomic_read(&hdev->in_reset)) 20 + if (atomic_read(&hdev->in_reset)) 23 21 status = HL_DEVICE_STATUS_IN_RESET; 24 22 else if (hdev->needs_reset) 25 23 status = HL_DEVICE_STATUS_NEEDS_RESET; 24 + else if (hdev->disabled) 25 + status = HL_DEVICE_STATUS_MALFUNCTION; 26 26 else 27 27 status = HL_DEVICE_STATUS_OPERATIONAL; 28 28 ··· 1092 1092 GFP_KERNEL); 1093 1093 if (!hdev->kernel_ctx) { 1094 1094 rc = -ENOMEM; 1095 + hl_mmu_fini(hdev); 1095 1096 goto out_err; 1096 1097 } 1097 1098 ··· 1104 1103 "failed to init kernel ctx in hard reset\n"); 1105 1104 kfree(hdev->kernel_ctx); 1106 1105 hdev->kernel_ctx = NULL; 1106 + hl_mmu_fini(hdev); 1107 1107 goto out_err; 1108 1108 } 1109 1109 }

+44 -16

drivers/misc/habanalabs/common/firmware_if.c

··· 627 627 security_status = RREG32(cpu_security_boot_status_reg); 628 628 629 629 /* We read security status multiple times during boot: 630 - * 1. preboot - we check if fw security feature is supported 631 - * 2. boot cpu - we get boot cpu security status 632 - * 3. FW application - we get FW application security status 630 + * 1. preboot - a. Check whether the security status bits are valid 631 + * b. Check whether fw security is enabled 632 + * c. Check whether hard reset is done by preboot 633 + * 2. boot cpu - a. Fetch boot cpu security status 634 + * b. Check whether hard reset is done by boot cpu 635 + * 3. FW application - a. Fetch fw application security status 636 + * b. Check whether hard reset is done by fw app 633 637 * 634 638 * Preboot: 635 639 * Check security status bit (CPU_BOOT_DEV_STS0_ENABLED), if it is set 636 640 * check security enabled bit (CPU_BOOT_DEV_STS0_SECURITY_EN) 637 641 */ 638 642 if (security_status & CPU_BOOT_DEV_STS0_ENABLED) { 639 - hdev->asic_prop.fw_security_status_valid = 1; 640 - prop->fw_security_disabled = 641 - !(security_status & CPU_BOOT_DEV_STS0_SECURITY_EN); 643 + prop->fw_security_status_valid = 1; 644 + 645 + if (security_status & CPU_BOOT_DEV_STS0_SECURITY_EN) 646 + prop->fw_security_disabled = false; 647 + else 648 + prop->fw_security_disabled = true; 649 + 650 + if (security_status & CPU_BOOT_DEV_STS0_FW_HARD_RST_EN) 651 + prop->hard_reset_done_by_fw = true; 642 652 } else { 643 - hdev->asic_prop.fw_security_status_valid = 0; 653 + prop->fw_security_status_valid = 0; 644 654 prop->fw_security_disabled = true; 645 655 } 646 656 657 + dev_dbg(hdev->dev, "Firmware preboot hard-reset is %s\n", 658 + prop->hard_reset_done_by_fw ? "enabled" : "disabled"); 659 + 647 660 dev_info(hdev->dev, "firmware-level security is %s\n", 648 - prop->fw_security_disabled ? "disabled" : "enabled"); 661 + prop->fw_security_disabled ? "disabled" : "enabled"); 649 662 650 663 return 0; 651 664 } ··· 668 655 u32 cpu_security_boot_status_reg, u32 boot_err0_reg, 669 656 bool skip_bmc, u32 cpu_timeout, u32 boot_fit_timeout) 670 657 { 658 + struct asic_fixed_properties *prop = &hdev->asic_prop; 671 659 u32 status; 672 660 int rc; 673 661 ··· 737 723 /* Read U-Boot version now in case we will later fail */ 738 724 hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_UBOOT); 739 725 726 + /* Clear reset status since we need to read it again from boot CPU */ 727 + prop->hard_reset_done_by_fw = false; 728 + 740 729 /* Read boot_cpu security bits */ 741 - if (hdev->asic_prop.fw_security_status_valid) 742 - hdev->asic_prop.fw_boot_cpu_security_map = 730 + if (prop->fw_security_status_valid) { 731 + prop->fw_boot_cpu_security_map = 743 732 RREG32(cpu_security_boot_status_reg); 733 + 734 + if (prop->fw_boot_cpu_security_map & 735 + CPU_BOOT_DEV_STS0_FW_HARD_RST_EN) 736 + prop->hard_reset_done_by_fw = true; 737 + } 738 + 739 + dev_dbg(hdev->dev, "Firmware boot CPU hard-reset is %s\n", 740 + prop->hard_reset_done_by_fw ? "enabled" : "disabled"); 744 741 745 742 if (rc) { 746 743 detect_cpu_boot_status(hdev, status); ··· 821 796 goto out; 822 797 } 823 798 799 + /* Clear reset status since we need to read again from app */ 800 + prop->hard_reset_done_by_fw = false; 801 + 824 802 /* Read FW application security bits */ 825 - if (hdev->asic_prop.fw_security_status_valid) { 826 - hdev->asic_prop.fw_app_security_map = 803 + if (prop->fw_security_status_valid) { 804 + prop->fw_app_security_map = 827 805 RREG32(cpu_security_boot_status_reg); 828 806 829 - if (hdev->asic_prop.fw_app_security_map & 807 + if (prop->fw_app_security_map & 830 808 CPU_BOOT_DEV_STS0_FW_HARD_RST_EN) 831 - hdev->asic_prop.hard_reset_done_by_fw = true; 809 + prop->hard_reset_done_by_fw = true; 832 810 } 833 811 834 - dev_dbg(hdev->dev, "Firmware hard-reset is %s\n", 835 - hdev->asic_prop.hard_reset_done_by_fw ? "enabled" : "disabled"); 812 + dev_dbg(hdev->dev, "Firmware application CPU hard-reset is %s\n", 813 + prop->hard_reset_done_by_fw ? "enabled" : "disabled"); 836 814 837 815 dev_info(hdev->dev, "Successfully loaded firmware to device\n"); 838 816

+3 -1

drivers/misc/habanalabs/common/habanalabs.h

··· 944 944 u32 (*get_signal_cb_size)(struct hl_device *hdev); 945 945 u32 (*get_wait_cb_size)(struct hl_device *hdev); 946 946 u32 (*gen_signal_cb)(struct hl_device *hdev, void *data, u16 sob_id, 947 - u32 size); 947 + u32 size, bool eb); 948 948 u32 (*gen_wait_cb)(struct hl_device *hdev, 949 949 struct hl_gen_wait_properties *prop); 950 950 void (*reset_sob)(struct hl_device *hdev, void *data); ··· 1000 1000 * @queue_full_drop_cnt: dropped due to queue full 1001 1001 * @device_in_reset_drop_cnt: dropped due to device in reset 1002 1002 * @max_cs_in_flight_drop_cnt: dropped due to maximum CS in-flight 1003 + * @validation_drop_cnt: dropped due to error in validation 1003 1004 */ 1004 1005 struct hl_cs_counters_atomic { 1005 1006 atomic64_t out_of_mem_drop_cnt; ··· 1008 1007 atomic64_t queue_full_drop_cnt; 1009 1008 atomic64_t device_in_reset_drop_cnt; 1010 1009 atomic64_t max_cs_in_flight_drop_cnt; 1010 + atomic64_t validation_drop_cnt; 1011 1011 }; 1012 1012 1013 1013 /**

+1

drivers/misc/habanalabs/common/habanalabs_drv.c

··· 544 544 .id_table = ids, 545 545 .probe = hl_pci_probe, 546 546 .remove = hl_pci_remove, 547 + .shutdown = hl_pci_remove, 547 548 .driver.pm = &hl_pm_ops, 548 549 .err_handler = &hl_pci_err_handler, 549 550 };

+6 -1

drivers/misc/habanalabs/common/habanalabs_ioctl.c

··· 335 335 atomic64_read(&cntr->device_in_reset_drop_cnt); 336 336 cs_counters.total_max_cs_in_flight_drop_cnt = 337 337 atomic64_read(&cntr->max_cs_in_flight_drop_cnt); 338 + cs_counters.total_validation_drop_cnt = 339 + atomic64_read(&cntr->validation_drop_cnt); 338 340 339 341 if (hpriv->ctx) { 340 342 cs_counters.ctx_out_of_mem_drop_cnt = ··· 354 352 cs_counters.ctx_max_cs_in_flight_drop_cnt = 355 353 atomic64_read( 356 354 &hpriv->ctx->cs_counters.max_cs_in_flight_drop_cnt); 355 + cs_counters.ctx_validation_drop_cnt = 356 + atomic64_read( 357 + &hpriv->ctx->cs_counters.validation_drop_cnt); 357 358 } 358 359 359 360 return copy_to_user(out, &cs_counters, ··· 411 406 static int pll_frequency_info(struct hl_fpriv *hpriv, struct hl_info_args *args) 412 407 { 413 408 struct hl_device *hdev = hpriv->hdev; 414 - struct hl_pll_frequency_info freq_info = {0}; 409 + struct hl_pll_frequency_info freq_info = { {0} }; 415 410 u32 max_size = args->return_size; 416 411 void __user *out = (void __user *) (uintptr_t) args->return_pointer; 417 412 int rc;

+4 -1

drivers/misc/habanalabs/common/hw_queue.c

··· 418 418 "generate signal CB, sob_id: %d, sob val: 0x%x, q_idx: %d\n", 419 419 cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val, q_idx); 420 420 421 + /* we set an EB since we must make sure all oeprations are done 422 + * when sending the signal 423 + */ 421 424 hdev->asic_funcs->gen_signal_cb(hdev, job->patched_cb, 422 - cs_cmpl->hw_sob->sob_id, 0); 425 + cs_cmpl->hw_sob->sob_id, 0, true); 423 426 424 427 kref_get(&hw_sob->kref); 425 428

+17 -11

drivers/misc/habanalabs/common/pci.c

··· 130 130 if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE) 131 131 return 0; 132 132 133 - if (val & PCI_CONFIG_ELBI_STS_ERR) { 134 - dev_err(hdev->dev, "Error writing to ELBI\n"); 133 + if (val & PCI_CONFIG_ELBI_STS_ERR) 135 134 return -EIO; 136 - } 137 135 138 136 if (!(val & PCI_CONFIG_ELBI_STS_MASK)) { 139 137 dev_err(hdev->dev, "ELBI write didn't finish in time\n"); ··· 158 160 159 161 dbi_offset = addr & 0xFFF; 160 162 161 - rc = hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000); 162 - rc |= hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset, 163 + /* Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail 164 + * in case the firmware security is enabled 165 + */ 166 + hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000); 167 + 168 + rc = hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset, 163 169 data); 164 170 165 171 if (rc) ··· 246 244 247 245 rc |= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val); 248 246 249 - /* Return the DBI window to the default location */ 250 - rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0); 251 - rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0); 247 + /* Return the DBI window to the default location 248 + * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail 249 + * in case the firmware security is enabled 250 + */ 251 + hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0); 252 252 253 253 if (rc) 254 254 dev_err(hdev->dev, "failed to map bar %u to 0x%08llx\n", ··· 298 294 /* Enable */ 299 295 rc |= hl_pci_iatu_write(hdev, 0x004, 0x80000000); 300 296 301 - /* Return the DBI window to the default location */ 302 - rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0); 303 - rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0); 297 + /* Return the DBI window to the default location 298 + * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail 299 + * in case the firmware security is enabled 300 + */ 301 + hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0); 304 302 305 303 return rc; 306 304 }

+86 -111

drivers/misc/habanalabs/gaudi/gaudi.c

··· 151 151 [PACKET_LOAD_AND_EXE] = sizeof(struct packet_load_and_exe) 152 152 }; 153 153 154 - static const u32 gaudi_pll_base_addresses[GAUDI_PLL_MAX] = { 155 - [CPU_PLL] = mmPSOC_CPU_PLL_NR, 156 - [PCI_PLL] = mmPSOC_PCI_PLL_NR, 157 - [SRAM_PLL] = mmSRAM_W_PLL_NR, 158 - [HBM_PLL] = mmPSOC_HBM_PLL_NR, 159 - [NIC_PLL] = mmNIC0_PLL_NR, 160 - [DMA_PLL] = mmDMA_W_PLL_NR, 161 - [MESH_PLL] = mmMESH_W_PLL_NR, 162 - [MME_PLL] = mmPSOC_MME_PLL_NR, 163 - [TPC_PLL] = mmPSOC_TPC_PLL_NR, 164 - [IF_PLL] = mmIF_W_PLL_NR 165 - }; 166 - 167 154 static inline bool validate_packet_id(enum packet_id id) 168 155 { 169 156 switch (id) { ··· 361 374 static void gaudi_disable_clock_gating(struct hl_device *hdev); 362 375 static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid); 363 376 static u32 gaudi_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id, 364 - u32 size); 377 + u32 size, bool eb); 365 378 static u32 gaudi_gen_wait_cb(struct hl_device *hdev, 366 379 struct hl_gen_wait_properties *prop); 367 380 ··· 654 667 if (rc) 655 668 goto free_queue_props; 656 669 657 - if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { 658 - dev_info(hdev->dev, 659 - "H/W state is dirty, must reset before initializing\n"); 660 - hdev->asic_funcs->hw_fini(hdev, true); 661 - } 662 - 663 670 /* Before continuing in the initialization, we need to read the preboot 664 671 * version to determine whether we run with a security-enabled firmware 665 672 */ ··· 664 683 if (hdev->reset_on_preboot_fail) 665 684 hdev->asic_funcs->hw_fini(hdev, true); 666 685 goto pci_fini; 686 + } 687 + 688 + if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { 689 + dev_info(hdev->dev, 690 + "H/W state is dirty, must reset before initializing\n"); 691 + hdev->asic_funcs->hw_fini(hdev, true); 667 692 } 668 693 669 694 return 0; ··· 690 703 } 691 704 692 705 /** 693 - * gaudi_fetch_pll_frequency - Fetch PLL frequency values 694 - * 695 - * @hdev: pointer to hl_device structure 696 - * @pll_index: index of the pll to fetch frequency from 697 - * @pll_freq: pointer to store the pll frequency in MHz in each of the available 698 - * outputs. if a certain output is not available a 0 will be set 699 - * 700 - */ 701 - static int gaudi_fetch_pll_frequency(struct hl_device *hdev, 702 - enum gaudi_pll_index pll_index, 703 - u16 *pll_freq_arr) 704 - { 705 - u32 nr = 0, nf = 0, od = 0, pll_clk = 0, div_fctr, div_sel, 706 - pll_base_addr = gaudi_pll_base_addresses[pll_index]; 707 - u16 freq = 0; 708 - int i, rc; 709 - 710 - if (hdev->asic_prop.fw_security_status_valid && 711 - (hdev->asic_prop.fw_app_security_map & 712 - CPU_BOOT_DEV_STS0_PLL_INFO_EN)) { 713 - rc = hl_fw_cpucp_pll_info_get(hdev, pll_index, pll_freq_arr); 714 - 715 - if (rc) 716 - return rc; 717 - } else if (hdev->asic_prop.fw_security_disabled) { 718 - /* Backward compatibility */ 719 - nr = RREG32(pll_base_addr + PLL_NR_OFFSET); 720 - nf = RREG32(pll_base_addr + PLL_NF_OFFSET); 721 - od = RREG32(pll_base_addr + PLL_OD_OFFSET); 722 - 723 - for (i = 0; i < HL_PLL_NUM_OUTPUTS; i++) { 724 - div_fctr = RREG32(pll_base_addr + 725 - PLL_DIV_FACTOR_0_OFFSET + i * 4); 726 - div_sel = RREG32(pll_base_addr + 727 - PLL_DIV_SEL_0_OFFSET + i * 4); 728 - 729 - if (div_sel == DIV_SEL_REF_CLK || 730 - div_sel == DIV_SEL_DIVIDED_REF) { 731 - if (div_sel == DIV_SEL_REF_CLK) 732 - freq = PLL_REF_CLK; 733 - else 734 - freq = PLL_REF_CLK / (div_fctr + 1); 735 - } else if (div_sel == DIV_SEL_PLL_CLK || 736 - div_sel == DIV_SEL_DIVIDED_PLL) { 737 - pll_clk = PLL_REF_CLK * (nf + 1) / 738 - ((nr + 1) * (od + 1)); 739 - if (div_sel == DIV_SEL_PLL_CLK) 740 - freq = pll_clk; 741 - else 742 - freq = pll_clk / (div_fctr + 1); 743 - } else { 744 - dev_warn(hdev->dev, 745 - "Received invalid div select value: %d", 746 - div_sel); 747 - } 748 - 749 - pll_freq_arr[i] = freq; 750 - } 751 - } else { 752 - dev_err(hdev->dev, "Failed to fetch PLL frequency values\n"); 753 - return -EIO; 754 - } 755 - 756 - return 0; 757 - } 758 - 759 - /** 760 706 * gaudi_fetch_psoc_frequency - Fetch PSOC frequency values 761 707 * 762 708 * @hdev: pointer to hl_device structure ··· 698 778 static int gaudi_fetch_psoc_frequency(struct hl_device *hdev) 699 779 { 700 780 struct asic_fixed_properties *prop = &hdev->asic_prop; 701 - u16 pll_freq[HL_PLL_NUM_OUTPUTS]; 781 + u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel; 782 + u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq; 702 783 int rc; 703 784 704 - rc = gaudi_fetch_pll_frequency(hdev, CPU_PLL, pll_freq); 705 - if (rc) 706 - return rc; 785 + if (hdev->asic_prop.fw_security_disabled) { 786 + /* Backward compatibility */ 787 + div_fctr = RREG32(mmPSOC_CPU_PLL_DIV_FACTOR_2); 788 + div_sel = RREG32(mmPSOC_CPU_PLL_DIV_SEL_2); 789 + nr = RREG32(mmPSOC_CPU_PLL_NR); 790 + nf = RREG32(mmPSOC_CPU_PLL_NF); 791 + od = RREG32(mmPSOC_CPU_PLL_OD); 707 792 708 - prop->psoc_timestamp_frequency = pll_freq[2]; 709 - prop->psoc_pci_pll_nr = 0; 710 - prop->psoc_pci_pll_nf = 0; 711 - prop->psoc_pci_pll_od = 0; 712 - prop->psoc_pci_pll_div_factor = 0; 793 + if (div_sel == DIV_SEL_REF_CLK || 794 + div_sel == DIV_SEL_DIVIDED_REF) { 795 + if (div_sel == DIV_SEL_REF_CLK) 796 + freq = PLL_REF_CLK; 797 + else 798 + freq = PLL_REF_CLK / (div_fctr + 1); 799 + } else if (div_sel == DIV_SEL_PLL_CLK || 800 + div_sel == DIV_SEL_DIVIDED_PLL) { 801 + pll_clk = PLL_REF_CLK * (nf + 1) / 802 + ((nr + 1) * (od + 1)); 803 + if (div_sel == DIV_SEL_PLL_CLK) 804 + freq = pll_clk; 805 + else 806 + freq = pll_clk / (div_fctr + 1); 807 + } else { 808 + dev_warn(hdev->dev, 809 + "Received invalid div select value: %d", 810 + div_sel); 811 + freq = 0; 812 + } 813 + } else { 814 + rc = hl_fw_cpucp_pll_info_get(hdev, CPU_PLL, pll_freq_arr); 815 + 816 + if (rc) 817 + return rc; 818 + 819 + freq = pll_freq_arr[2]; 820 + } 821 + 822 + prop->psoc_timestamp_frequency = freq; 823 + prop->psoc_pci_pll_nr = nr; 824 + prop->psoc_pci_pll_nf = nf; 825 + prop->psoc_pci_pll_od = od; 826 + prop->psoc_pci_pll_div_factor = div_fctr; 713 827 714 828 return 0; 715 829 } ··· 838 884 size_t fw_size; 839 885 void *cpu_addr; 840 886 dma_addr_t dma_handle; 841 - int rc; 887 + int rc, count = 5; 842 888 889 + again: 843 890 rc = request_firmware(&fw, GAUDI_TPC_FW_FILE, hdev->dev); 891 + if (rc == -EINTR && count-- > 0) { 892 + msleep(50); 893 + goto again; 894 + } 895 + 844 896 if (rc) { 845 - dev_err(hdev->dev, "Firmware file %s is not found!\n", 897 + dev_err(hdev->dev, "Failed to load firmware file %s\n", 846 898 GAUDI_TPC_FW_FILE); 847 899 goto out; 848 900 } ··· 1070 1110 prop->collective_sob_id, queue_id); 1071 1111 1072 1112 cb_size += gaudi_gen_signal_cb(hdev, job->user_cb, 1073 - prop->collective_sob_id, cb_size); 1113 + prop->collective_sob_id, cb_size, false); 1074 1114 } 1075 1115 1076 1116 static void gaudi_collective_wait_init_cs(struct hl_cs *cs) ··· 2409 2449 gaudi_init_e2e(hdev); 2410 2450 gaudi_init_hbm_cred(hdev); 2411 2451 2412 - hdev->asic_funcs->disable_clock_gating(hdev); 2413 - 2414 2452 for (tpc_id = 0, tpc_offset = 0; 2415 2453 tpc_id < TPC_NUMBER_OF_ENGINES; 2416 2454 tpc_id++, tpc_offset += TPC_CFG_OFFSET) { ··· 3420 3462 if (hdev->in_debug) 3421 3463 return; 3422 3464 3465 + if (!hdev->asic_prop.fw_security_disabled) 3466 + return; 3467 + 3423 3468 for (i = GAUDI_PCI_DMA_1, qman_offset = 0 ; i < GAUDI_HBM_DMA_1 ; i++) { 3424 3469 enable = !!(hdev->clock_gating_mask & 3425 3470 (BIT_ULL(gaudi_dma_assignment[i]))); ··· 3474 3513 u32 qman_offset; 3475 3514 int i; 3476 3515 3477 - if (!(gaudi->hw_cap_initialized & HW_CAP_CLK_GATE)) 3516 + if (!hdev->asic_prop.fw_security_disabled) 3478 3517 return; 3479 3518 3480 3519 for (i = 0, qman_offset = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) { ··· 3767 3806 static void gaudi_pre_hw_init(struct hl_device *hdev) 3768 3807 { 3769 3808 /* Perform read from the device to make sure device is up */ 3770 - RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); 3809 + RREG32(mmHW_STATE); 3771 3810 3772 3811 if (hdev->asic_prop.fw_security_disabled) { 3773 3812 /* Set the access through PCI bars (Linux driver only) as ··· 3808 3847 return rc; 3809 3848 } 3810 3849 3850 + /* In case the clock gating was enabled in preboot we need to disable 3851 + * it here before touching the MME/TPC registers. 3852 + * There is no need to take clk gating mutex because when this function 3853 + * runs, no other relevant code can run 3854 + */ 3855 + hdev->asic_funcs->disable_clock_gating(hdev); 3856 + 3811 3857 /* SRAM scrambler must be initialized after CPU is running from HBM */ 3812 3858 gaudi_init_scrambler_sram(hdev); 3813 3859 ··· 3853 3885 } 3854 3886 3855 3887 /* Perform read from the device to flush all configuration */ 3856 - RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); 3888 + RREG32(mmHW_STATE); 3857 3889 3858 3890 return 0; 3859 3891 ··· 3895 3927 /* I don't know what is the state of the CPU so make sure it is 3896 3928 * stopped in any means necessary 3897 3929 */ 3898 - WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_GOTO_WFE); 3930 + if (hdev->asic_prop.hard_reset_done_by_fw) 3931 + WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_RST_DEV); 3932 + else 3933 + WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_GOTO_WFE); 3899 3934 3900 3935 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_HALT_MACHINE); 3901 3936 ··· 3942 3971 3943 3972 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST, 3944 3973 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT); 3945 - } 3946 3974 3947 - dev_info(hdev->dev, 3948 - "Issued HARD reset command, going to wait %dms\n", 3949 - reset_timeout_ms); 3975 + dev_info(hdev->dev, 3976 + "Issued HARD reset command, going to wait %dms\n", 3977 + reset_timeout_ms); 3978 + } else { 3979 + dev_info(hdev->dev, 3980 + "Firmware performs HARD reset, going to wait %dms\n", 3981 + reset_timeout_ms); 3982 + } 3950 3983 3951 3984 /* 3952 3985 * After hard reset, we can't poll the BTM_FSM register because the PSOC ··· 7911 7936 } 7912 7937 7913 7938 static u32 gaudi_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id, 7914 - u32 size) 7939 + u32 size, bool eb) 7915 7940 { 7916 7941 struct hl_cb *cb = (struct hl_cb *) data; 7917 7942 struct packet_msg_short *pkt; ··· 7928 7953 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OP_MASK, 0); /* write the value */ 7929 7954 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 3); /* W_S SOB base */ 7930 7955 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OPCODE_MASK, PACKET_MSG_SHORT); 7931 - ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_EB_MASK, 1); 7956 + ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_EB_MASK, eb); 7932 7957 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_RB_MASK, 1); 7933 7958 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_MB_MASK, 1); 7934 7959

-7

drivers/misc/habanalabs/gaudi/gaudiP.h

··· 105 105 #define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE) 106 106 #define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE) 107 107 108 - #define PLL_NR_OFFSET 0 109 - #define PLL_NF_OFFSET (mmPSOC_CPU_PLL_NF - mmPSOC_CPU_PLL_NR) 110 - #define PLL_OD_OFFSET (mmPSOC_CPU_PLL_OD - mmPSOC_CPU_PLL_NR) 111 - #define PLL_DIV_FACTOR_0_OFFSET (mmPSOC_CPU_PLL_DIV_FACTOR_0 - \ 112 - mmPSOC_CPU_PLL_NR) 113 - #define PLL_DIV_SEL_0_OFFSET (mmPSOC_CPU_PLL_DIV_SEL_0 - mmPSOC_CPU_PLL_NR) 114 - 115 108 #define NUM_OF_SOB_IN_BLOCK \ 116 109 (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \ 117 110 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)

+2 -1

drivers/misc/habanalabs/gaudi/gaudi_coresight.c

··· 9 9 #include "../include/gaudi/gaudi_coresight.h" 10 10 #include "../include/gaudi/asic_reg/gaudi_regs.h" 11 11 #include "../include/gaudi/gaudi_masks.h" 12 + #include "../include/gaudi/gaudi_reg_map.h" 12 13 13 14 #include <uapi/misc/habanalabs.h> 14 15 #define SPMU_SECTION_SIZE MME0_ACC_SPMU_MAX_OFFSET ··· 875 874 } 876 875 877 876 /* Perform read from the device to flush all configuration */ 878 - RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); 877 + RREG32(mmHW_STATE); 879 878 880 879 return rc; 881 880 }

+44 -29

drivers/misc/habanalabs/goya/goya.c

··· 613 613 if (rc) 614 614 goto free_queue_props; 615 615 616 - if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { 617 - dev_info(hdev->dev, 618 - "H/W state is dirty, must reset before initializing\n"); 619 - hdev->asic_funcs->hw_fini(hdev, true); 620 - } 621 - 622 616 /* Before continuing in the initialization, we need to read the preboot 623 617 * version to determine whether we run with a security-enabled firmware 624 618 */ ··· 623 629 if (hdev->reset_on_preboot_fail) 624 630 hdev->asic_funcs->hw_fini(hdev, true); 625 631 goto pci_fini; 632 + } 633 + 634 + if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { 635 + dev_info(hdev->dev, 636 + "H/W state is dirty, must reset before initializing\n"); 637 + hdev->asic_funcs->hw_fini(hdev, true); 626 638 } 627 639 628 640 if (!hdev->pldm) { ··· 694 694 static void goya_fetch_psoc_frequency(struct hl_device *hdev) 695 695 { 696 696 struct asic_fixed_properties *prop = &hdev->asic_prop; 697 - u32 trace_freq = 0; 698 - u32 pll_clk = 0; 699 - u32 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1); 700 - u32 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1); 701 - u32 nr = RREG32(mmPSOC_PCI_PLL_NR); 702 - u32 nf = RREG32(mmPSOC_PCI_PLL_NF); 703 - u32 od = RREG32(mmPSOC_PCI_PLL_OD); 697 + u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel; 698 + u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq; 699 + int rc; 704 700 705 - if (div_sel == DIV_SEL_REF_CLK || div_sel == DIV_SEL_DIVIDED_REF) { 706 - if (div_sel == DIV_SEL_REF_CLK) 707 - trace_freq = PLL_REF_CLK; 708 - else 709 - trace_freq = PLL_REF_CLK / (div_fctr + 1); 710 - } else if (div_sel == DIV_SEL_PLL_CLK || 711 - div_sel == DIV_SEL_DIVIDED_PLL) { 712 - pll_clk = PLL_REF_CLK * (nf + 1) / ((nr + 1) * (od + 1)); 713 - if (div_sel == DIV_SEL_PLL_CLK) 714 - trace_freq = pll_clk; 715 - else 716 - trace_freq = pll_clk / (div_fctr + 1); 701 + if (hdev->asic_prop.fw_security_disabled) { 702 + div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1); 703 + div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1); 704 + nr = RREG32(mmPSOC_PCI_PLL_NR); 705 + nf = RREG32(mmPSOC_PCI_PLL_NF); 706 + od = RREG32(mmPSOC_PCI_PLL_OD); 707 + 708 + if (div_sel == DIV_SEL_REF_CLK || 709 + div_sel == DIV_SEL_DIVIDED_REF) { 710 + if (div_sel == DIV_SEL_REF_CLK) 711 + freq = PLL_REF_CLK; 712 + else 713 + freq = PLL_REF_CLK / (div_fctr + 1); 714 + } else if (div_sel == DIV_SEL_PLL_CLK || 715 + div_sel == DIV_SEL_DIVIDED_PLL) { 716 + pll_clk = PLL_REF_CLK * (nf + 1) / 717 + ((nr + 1) * (od + 1)); 718 + if (div_sel == DIV_SEL_PLL_CLK) 719 + freq = pll_clk; 720 + else 721 + freq = pll_clk / (div_fctr + 1); 722 + } else { 723 + dev_warn(hdev->dev, 724 + "Received invalid div select value: %d", 725 + div_sel); 726 + freq = 0; 727 + } 717 728 } else { 718 - dev_warn(hdev->dev, 719 - "Received invalid div select value: %d", div_sel); 729 + rc = hl_fw_cpucp_pll_info_get(hdev, PCI_PLL, pll_freq_arr); 730 + 731 + if (rc) 732 + return; 733 + 734 + freq = pll_freq_arr[1]; 720 735 } 721 736 722 - prop->psoc_timestamp_frequency = trace_freq; 737 + prop->psoc_timestamp_frequency = freq; 723 738 prop->psoc_pci_pll_nr = nr; 724 739 prop->psoc_pci_pll_nf = nf; 725 740 prop->psoc_pci_pll_od = od; ··· 5339 5324 } 5340 5325 5341 5326 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id, 5342 - u32 size) 5327 + u32 size, bool eb) 5343 5328 { 5344 5329 return 0; 5345 5330 }

+8 -1

drivers/misc/habanalabs/include/common/hl_boot_if.h

··· 145 145 * implemented. This means that FW will 146 146 * perform hard reset procedure on 147 147 * receiving the halt-machine event. 148 - * Initialized in: linux 148 + * Initialized in: preboot, u-boot, linux 149 149 * 150 150 * CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled. 151 151 * Initialized in: linux 152 + * 153 + * CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled. 154 + * FW initialized Clock Gating. 155 + * Initialized in: preboot 152 156 * 153 157 * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. 154 158 * This is a main indication that the ··· 175 171 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << 9) 176 172 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << 10) 177 173 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << 11) 174 + #define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << 13) 178 175 #define CPU_BOOT_DEV_STS0_ENABLED (1 << 31) 179 176 180 177 enum cpu_boot_status { ··· 209 204 KMD_MSG_GOTO_WFE, 210 205 KMD_MSG_FIT_RDY, 211 206 KMD_MSG_SKIP_BMC, 207 + RESERVED, 208 + KMD_MSG_RST_DEV, 212 209 }; 213 210 214 211 enum cpu_msg_status {

+15 -4

drivers/misc/pvpanic.c

··· 55 55 struct resource *res; 56 56 57 57 res = platform_get_mem_or_io(pdev, 0); 58 - if (res && resource_type(res) == IORESOURCE_IO) 58 + if (!res) 59 + return -EINVAL; 60 + 61 + switch (resource_type(res)) { 62 + case IORESOURCE_IO: 59 63 base = devm_ioport_map(dev, res->start, resource_size(res)); 60 - else 64 + if (!base) 65 + return -ENOMEM; 66 + break; 67 + case IORESOURCE_MEM: 61 68 base = devm_ioremap_resource(dev, res); 62 - if (IS_ERR(base)) 63 - return PTR_ERR(base); 69 + if (IS_ERR(base)) 70 + return PTR_ERR(base); 71 + break; 72 + default: 73 + return -EINVAL; 74 + } 64 75 65 76 atomic_notifier_chain_register(&panic_notifier_list, 66 77 &pvpanic_panic_nb);

+5

include/uapi/misc/habanalabs.h

··· 279 279 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason 280 280 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore 281 281 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption 282 + * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency 282 283 */ 283 284 #define HL_INFO_HW_IP_INFO 0 284 285 #define HL_INFO_HW_EVENTS 1 ··· 426 425 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset 427 426 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight 428 427 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight 428 + * @total_validation_drop_cnt: total dropped due to validation error 429 + * @ctx_validation_drop_cnt: context dropped due to validation error 429 430 */ 430 431 struct hl_info_cs_counters { 431 432 __u64 total_out_of_mem_drop_cnt; ··· 440 437 __u64 ctx_device_in_reset_drop_cnt; 441 438 __u64 total_max_cs_in_flight_drop_cnt; 442 439 __u64 ctx_max_cs_in_flight_drop_cnt; 440 + __u64 total_validation_drop_cnt; 441 + __u64 ctx_validation_drop_cnt; 443 442 }; 444 443 445 444 enum gaudi_dcores {

+3 -3

lib/fonts/font_ter16x32.c

··· 774 774 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 775 775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfc, 776 776 0x7f, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 95 */ 777 - 0x00, 0x00, 0x1c, 0x00, 0x0e, 0x00, 0x07, 0x00, 778 - 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 777 + 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x0e, 0x00, 778 + 0x07, 0x00, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 779 779 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 780 780 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 781 781 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ··· 1169 1169 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1170 1170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1171 1171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1172 - 0x7f, 0xf8, 0x7f, 0xfc, 0x03, 0x9e, 0x03, 0x8e, 1172 + 0x7e, 0xf8, 0x7f, 0xfc, 0x03, 0x9e, 0x03, 0x8e, 1173 1173 0x03, 0x8e, 0x3f, 0x8e, 0x7f, 0xfe, 0xf3, 0xfe, 1174 1174 0xe3, 0x80, 0xe3, 0x80, 0xe3, 0x80, 0xf3, 0xce, 1175 1175 0x7f, 0xfe, 0x3e, 0xfc, 0x00, 0x00, 0x00, 0x00,