Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dt-bindings: hwmon: Support Aspeed g6 PWM TACH Control

Document the compatible for aspeed,ast2600-pwm-tach device, which can
support up to 16 PWM outputs and 16 fan tach input.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240221104025.1306227-3-billy_tsai@aspeedtech.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>

authored by

Billy Tsai and committed by
Guenter Roeck
df9d235c 3b0ac1f9

+71
+71
Documentation/devicetree/bindings/hwmon/aspeed,g6-pwm-tach.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright (C) 2023 Aspeed, Inc. 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/hwmon/aspeed,g6-pwm-tach.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: ASPEED G6 PWM and Fan Tach controller 9 + 10 + maintainers: 11 + - Billy Tsai <billy_tsai@aspeedtech.com> 12 + 13 + description: | 14 + The ASPEED PWM controller can support up to 16 PWM outputs. 15 + The ASPEED Fan Tacho controller can support up to 16 fan tach input. 16 + They are independent hardware blocks, which are different from the 17 + previous version of the ASPEED chip. 18 + 19 + properties: 20 + compatible: 21 + enum: 22 + - aspeed,ast2600-pwm-tach 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + clocks: 28 + maxItems: 1 29 + 30 + resets: 31 + maxItems: 1 32 + 33 + "#pwm-cells": 34 + const: 3 35 + 36 + patternProperties: 37 + "^fan-[0-9]+$": 38 + $ref: fan-common.yaml# 39 + unevaluatedProperties: false 40 + required: 41 + - tach-ch 42 + 43 + required: 44 + - reg 45 + - clocks 46 + - resets 47 + - "#pwm-cells" 48 + - compatible 49 + 50 + additionalProperties: false 51 + 52 + examples: 53 + - | 54 + #include <dt-bindings/clock/aspeed-clock.h> 55 + pwm_tach: pwm-tach-controller@1e610000 { 56 + compatible = "aspeed,ast2600-pwm-tach"; 57 + reg = <0x1e610000 0x100>; 58 + clocks = <&syscon ASPEED_CLK_AHB>; 59 + resets = <&syscon ASPEED_RESET_PWM>; 60 + #pwm-cells = <3>; 61 + 62 + fan-0 { 63 + tach-ch = /bits/ 8 <0x0>; 64 + pwms = <&pwm_tach 0 40000 0>; 65 + }; 66 + 67 + fan-1 { 68 + tach-ch = /bits/ 8 <0x1 0x2>; 69 + pwms = <&pwm_tach 1 40000 0>; 70 + }; 71 + };