tjh.dev / kernel
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ath9k: Fix register definitions for QCA956x

Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com>
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

authored by

Miaoqing Pan and committed by
Kalle Valo df476df1 635d7c50

+11 -8
+11 -8
drivers/net/wireless/ath/ath9k/ar9003_phy.h
··· 454 454 #define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4) 455 455 #define AR_PHY_MODE (AR_SM_BASE + 0x8) 456 456 #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc) 457 - #define AR_PHY_SPUR_MASK_A (AR_SM_BASE + 0x20) 457 + #define AR_PHY_SPUR_MASK_A (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x18 : 0x20)) 458 458 #define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24) 459 459 #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28) 460 460 #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c) ··· 506 506 #define AR_PHY_TEST_CHAIN_SEL 0xC0000000 507 507 #define AR_PHY_TEST_CHAIN_SEL_S 30 508 508 509 - #define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + 0x164) 509 + #define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x160 : 0x164)) 510 510 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1 511 511 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 512 512 #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C ··· 525 525 526 526 #define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c) 527 527 528 - #define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170) 528 + #define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x16c : 0x170)) 529 529 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008 530 530 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3 531 531 ··· 536 536 #define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190) 537 537 #define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194) 538 538 539 - #define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + 0x1a4) 539 + #define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x198 : 0x1a4)) 540 540 #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8) 541 541 #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac) 542 542 #define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0) ··· 726 726 727 727 #define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : \ 728 728 (AR_SREV_9462(ah) ? 0x16290 : 0x16284)) 729 - #define AR_CH0_TOP2_XPABIASLVL 0xf000 729 + #define AR_CH0_TOP2_XPABIASLVL (AR_SREV_9561(ah) ? 0x1e00 : 0xf000) 730 730 #define AR_CH0_TOP2_XPABIASLVL_S 12 731 731 732 732 #define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \ 733 - ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : 0x16290)) 733 + ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : \ 734 + (AR_SREV_9561(ah) ? 0x162c0 : 0x16290))) 734 735 #define AR_CH0_XTAL_CAPINDAC 0x7f000000 735 736 #define AR_CH0_XTAL_CAPINDAC_S 24 736 737 #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 737 738 #define AR_CH0_XTAL_CAPOUTDAC_S 17 738 739 739 - #define AR_PHY_PMU1 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16340 : 0x16c40) 740 + #define AR_PHY_PMU1 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16340 : \ 741 + (AR_SREV_9561(ah) ? 0x16cc0 : 0x16c40)) 740 742 #define AR_PHY_PMU1_PWD 0x1 741 743 #define AR_PHY_PMU1_PWD_S 0 742 744 743 - #define AR_PHY_PMU2 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16344 : 0x16c44) 745 + #define AR_PHY_PMU2 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16344 : \ 746 + (AR_SREV_9561(ah) ? 0x16cc4 : 0x16c44)) 744 747 #define AR_PHY_PMU2_PGM 0x00200000 745 748 #define AR_PHY_PMU2_PGM_S 21 746 749