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linux
KVM: LoongArch: selftests: Add timer interrupt test case
Add timer test case based on common arch_timer code, timer interrupt
with one-shot and period mode is tested.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
authored by
Bibo Mao
and committed by
Huacai Chen
df417423
d84fe2f3
+228
-2
+1
tools/testing/selftests/kvm/Makefile.kvm
+1
tools/testing/selftests/kvm/Makefile.kvm
···
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TEST_GEN_PROGS_riscv += rseq_test
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TEST_GEN_PROGS_riscv += steal_time
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TEST_GEN_PROGS_loongarch = arch_timer
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TEST_GEN_PROGS_loongarch += coalesced_io_test
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TEST_GEN_PROGS_loongarch += demand_paging_test
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TEST_GEN_PROGS_loongarch += dirty_log_perf_test
+85
tools/testing/selftests/kvm/include/loongarch/arch_timer.h
+85
tools/testing/selftests/kvm/include/loongarch/arch_timer.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* LoongArch Constant Timer specific interface
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*/
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#ifndef SELFTEST_KVM_ARCH_TIMER_H
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#define SELFTEST_KVM_ARCH_TIMER_H
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#include "processor.h"
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/* LoongArch timer frequency is constant 100MHZ */
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#define TIMER_FREQ (100UL << 20)
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#define msec_to_cycles(msec) (TIMER_FREQ * (unsigned long)(msec) / 1000)
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#define usec_to_cycles(usec) (TIMER_FREQ * (unsigned long)(usec) / 1000000)
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#define cycles_to_usec(cycles) ((unsigned long)(cycles) * 1000000 / TIMER_FREQ)
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static inline unsigned long timer_get_cycles(void)
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{
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unsigned long val = 0;
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__asm__ __volatile__(
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"rdtime.d %0, $zero\n\t"
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: "=r"(val)
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:
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);
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return val;
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}
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static inline unsigned long timer_get_cfg(void)
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{
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return csr_read(LOONGARCH_CSR_TCFG);
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}
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static inline unsigned long timer_get_val(void)
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{
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return csr_read(LOONGARCH_CSR_TVAL);
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}
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static inline void disable_timer(void)
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{
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csr_write(0, LOONGARCH_CSR_TCFG);
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}
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static inline void timer_irq_enable(void)
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{
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unsigned long val;
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val = csr_read(LOONGARCH_CSR_ECFG);
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val |= ECFGF_TIMER;
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csr_write(val, LOONGARCH_CSR_ECFG);
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}
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static inline void timer_irq_disable(void)
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{
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unsigned long val;
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val = csr_read(LOONGARCH_CSR_ECFG);
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val &= ~ECFGF_TIMER;
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csr_write(val, LOONGARCH_CSR_ECFG);
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}
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static inline void timer_set_next_cmp_ms(unsigned int msec, bool period)
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{
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unsigned long val;
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val = msec_to_cycles(msec) & CSR_TCFG_VAL;
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val |= CSR_TCFG_EN;
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if (period)
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val |= CSR_TCFG_PERIOD;
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csr_write(val, LOONGARCH_CSR_TCFG);
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}
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static inline void __delay(uint64_t cycles)
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{
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uint64_t start = timer_get_cycles();
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while ((timer_get_cycles() - start) < cycles)
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cpu_relax();
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}
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static inline void udelay(unsigned long usec)
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{
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__delay(usec_to_cycles(usec));
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}
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#endif /* SELFTEST_KVM_ARCH_TIMER_H */
+10
tools/testing/selftests/kvm/include/loongarch/processor.h
+10
tools/testing/selftests/kvm/include/loongarch/processor.h
···
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#define LOONGARCH_CSR_PRMD 0x1
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#define LOONGARCH_CSR_EUEN 0x2
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#define LOONGARCH_CSR_ECFG 0x4
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#define ECFGB_TIMER 11
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#define ECFGF_TIMER (BIT_ULL(ECFGB_TIMER))
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#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
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#define CSR_ESTAT_EXC_SHIFT 16
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#define CSR_ESTAT_EXC_WIDTH 6
···
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#define LOONGARCH_CSR_KS1 0x31
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#define LOONGARCH_CSR_TMID 0x40
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#define LOONGARCH_CSR_TCFG 0x41
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#define CSR_TCFG_VAL (BIT_ULL(48) - BIT_ULL(2))
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#define CSR_TCFG_PERIOD_SHIFT 1
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#define CSR_TCFG_PERIOD (0x1UL << CSR_TCFG_PERIOD_SHIFT)
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#define CSR_TCFG_EN (0x1UL)
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#define LOONGARCH_CSR_TVAL 0x42
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#define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */
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#define CSR_TINTCLR_TI_SHIFT 0
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#define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT)
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/* TLB refill exception entry */
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#define LOONGARCH_CSR_TLBRENTRY 0x88
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#define LOONGARCH_CSR_TLBRSAVE 0x8b
+2
-2
tools/testing/selftests/kvm/lib/loongarch/processor.c
+2
-2
tools/testing/selftests/kvm/lib/loongarch/processor.c
···
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TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
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}
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/* user mode and page enable mode */
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val = PLV_USER | CSR_CRMD_PG;
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/* kernel mode and page enable mode */
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val = PLV_KERN | CSR_CRMD_PG;
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loongarch_set_csr(vcpu, LOONGARCH_CSR_CRMD, val);
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loongarch_set_csr(vcpu, LOONGARCH_CSR_PRMD, val);
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loongarch_set_csr(vcpu, LOONGARCH_CSR_EUEN, 1);
+130
tools/testing/selftests/kvm/loongarch/arch_timer.c
+130
tools/testing/selftests/kvm/loongarch/arch_timer.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* The test validates periodic/one-shot constant timer IRQ using
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* CSR.TCFG and CSR.TVAL registers.
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*/
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#include "arch_timer.h"
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#include "kvm_util.h"
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#include "processor.h"
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#include "timer_test.h"
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#include "ucall_common.h"
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static void guest_irq_handler(struct ex_regs *regs)
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{
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unsigned int intid;
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uint32_t cpu = guest_get_vcpuid();
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uint64_t xcnt, val, cfg, xcnt_diff_us;
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struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
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intid = !!(regs->estat & BIT(INT_TI));
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/* Make sure we are dealing with the correct timer IRQ */
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GUEST_ASSERT_EQ(intid, 1);
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cfg = timer_get_cfg();
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if (cfg & CSR_TCFG_PERIOD) {
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WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter - 1);
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if (shared_data->nr_iter == 0)
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disable_timer();
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csr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR);
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return;
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}
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/*
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* On real machine, value of LOONGARCH_CSR_TVAL is BIT_ULL(48) - 1
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* On virtual machine, its value counts down from BIT_ULL(48) - 1
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*/
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val = timer_get_val();
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xcnt = timer_get_cycles();
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xcnt_diff_us = cycles_to_usec(xcnt - shared_data->xcnt);
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/* Basic 'timer condition met' check */
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__GUEST_ASSERT(val > cfg,
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"val = 0x%lx, cfg = 0x%lx, xcnt_diff_us = 0x%lx",
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val, cfg, xcnt_diff_us);
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csr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR);
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WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1);
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}
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static void guest_test_period_timer(uint32_t cpu)
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{
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uint32_t irq_iter, config_iter;
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uint64_t us;
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struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
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shared_data->nr_iter = test_args.nr_iter;
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shared_data->xcnt = timer_get_cycles();
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us = msecs_to_usecs(test_args.timer_period_ms) + test_args.timer_err_margin_us;
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timer_set_next_cmp_ms(test_args.timer_period_ms, true);
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for (config_iter = 0; config_iter < test_args.nr_iter; config_iter++) {
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/* Setup a timeout for the interrupt to arrive */
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udelay(us);
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}
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irq_iter = READ_ONCE(shared_data->nr_iter);
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__GUEST_ASSERT(irq_iter == 0,
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"irq_iter = 0x%x.\n"
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" Guest period timer interrupt was not triggered within the specified\n"
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" interval, try to increase the error margin by [-e] option.\n",
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irq_iter);
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}
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static void guest_test_oneshot_timer(uint32_t cpu)
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{
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uint32_t irq_iter, config_iter;
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uint64_t us;
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struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
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shared_data->nr_iter = 0;
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shared_data->guest_stage = 0;
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us = msecs_to_usecs(test_args.timer_period_ms) + test_args.timer_err_margin_us;
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for (config_iter = 0; config_iter < test_args.nr_iter; config_iter++) {
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shared_data->xcnt = timer_get_cycles();
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/* Setup the next interrupt */
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timer_set_next_cmp_ms(test_args.timer_period_ms, false);
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/* Setup a timeout for the interrupt to arrive */
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udelay(us);
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irq_iter = READ_ONCE(shared_data->nr_iter);
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__GUEST_ASSERT(config_iter + 1 == irq_iter,
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"config_iter + 1 = 0x%x, irq_iter = 0x%x.\n"
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" Guest timer interrupt was not triggered within the specified\n"
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" interval, try to increase the error margin by [-e] option.\n",
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config_iter + 1, irq_iter);
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}
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}
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static void guest_code(void)
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{
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uint32_t cpu = guest_get_vcpuid();
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timer_irq_enable();
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local_irq_enable();
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guest_test_period_timer(cpu);
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guest_test_oneshot_timer(cpu);
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GUEST_DONE();
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}
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struct kvm_vm *test_vm_create(void)
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{
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struct kvm_vm *vm;
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int nr_vcpus = test_args.nr_vcpus;
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vm = vm_create_with_vcpus(nr_vcpus, guest_code, vcpus);
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vm_init_descriptor_tables(vm);
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vm_install_exception_handler(vm, EXCCODE_INT, guest_irq_handler);
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/* Make all the test's cmdline args visible to the guest */
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sync_global_to_guest(vm, test_args);
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return vm;
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}
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void test_vm_cleanup(struct kvm_vm *vm)
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{
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kvm_vm_free(vm);
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}