Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu: add sdma ip block for navy_flounder

Navy_Flounder has the same sdma IP version with
sienna_cichlid, and it has 2 sdma controllers.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Jiansong Chen and committed by
Alex Deucher
df2d15df 885eb3fa

+19 -2
+1
drivers/gpu/drm/amd/amdgpu/nv.c
··· 528 528 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 529 529 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 530 530 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 531 + amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 531 532 break; 532 533 default: 533 534 return -EINVAL;
+18 -2
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
··· 45 45 #include "sdma_v5_2.h" 46 46 47 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 + MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 48 49 49 50 #define SDMA1_REG_OFFSET 0x600 50 51 #define SDMA3_REG_OFFSET 0x400 ··· 86 85 { 87 86 switch (adev->asic_type) { 88 87 case CHIP_SIENNA_CICHLID: 88 + case CHIP_NAVY_FLOUNDER: 89 89 break; 90 90 default: 91 91 break; ··· 154 152 case CHIP_SIENNA_CICHLID: 155 153 chip_name = "sienna_cichlid"; 156 154 break; 155 + case CHIP_NAVY_FLOUNDER: 156 + chip_name = "navy_flounder"; 157 + break; 157 158 default: 158 159 BUG(); 159 160 } ··· 172 167 goto out; 173 168 174 169 for (i = 1; i < adev->sdma.num_instances; i++) { 175 - if (adev->asic_type == CHIP_SIENNA_CICHLID) { 170 + if (adev->asic_type == CHIP_SIENNA_CICHLID || 171 + adev->asic_type == CHIP_NAVY_FLOUNDER) { 176 172 memcpy((void*)&adev->sdma.instance[i], 177 173 (void*)&adev->sdma.instance[0], 178 174 sizeof(struct amdgpu_sdma_instance)); ··· 1161 1155 { 1162 1156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1163 1157 1164 - adev->sdma.num_instances = 4; 1158 + switch (adev->asic_type) { 1159 + case CHIP_SIENNA_CICHLID: 1160 + adev->sdma.num_instances = 4; 1161 + break; 1162 + case CHIP_NAVY_FLOUNDER: 1163 + adev->sdma.num_instances = 2; 1164 + break; 1165 + default: 1166 + break; 1167 + } 1165 1168 1166 1169 sdma_v5_2_set_ring_funcs(adev); 1167 1170 sdma_v5_2_set_buffer_funcs(adev); ··· 1563 1548 1564 1549 switch (adev->asic_type) { 1565 1550 case CHIP_SIENNA_CICHLID: 1551 + case CHIP_NAVY_FLOUNDER: 1566 1552 sdma_v5_2_update_medium_grain_clock_gating(adev, 1567 1553 state == AMD_CG_STATE_GATE ? true : false); 1568 1554 sdma_v5_2_update_medium_grain_light_sleep(adev,