drm/radeon: remove struct radeon_bo_list

+105 -105

drivers/gpu/drm/radeon/evergreen_cs.c

··· 1165 1165 "0x%04X\n", reg); 1166 1166 return -EINVAL; 1167 1167 } 1168 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1168 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1169 1169 break; 1170 1170 case DB_DEPTH_CONTROL: 1171 1171 track->db_depth_control = radeon_get_ib_value(p, idx); ··· 1196 1196 } 1197 1197 ib[idx] &= ~Z_ARRAY_MODE(0xf); 1198 1198 track->db_z_info &= ~Z_ARRAY_MODE(0xf); 1199 - ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1200 - track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1201 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1199 + ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1200 + track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1201 + if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1202 1202 unsigned bankw, bankh, mtaspect, tile_split; 1203 1203 1204 - evergreen_tiling_fields(reloc->lobj.tiling_flags, 1204 + evergreen_tiling_fields(reloc->tiling_flags, 1205 1205 &bankw, &bankh, &mtaspect, 1206 1206 &tile_split); 1207 1207 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); ··· 1237 1237 return -EINVAL; 1238 1238 } 1239 1239 track->db_z_read_offset = radeon_get_ib_value(p, idx); 1240 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1240 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1241 1241 track->db_z_read_bo = reloc->robj; 1242 1242 track->db_dirty = true; 1243 1243 break; ··· 1249 1249 return -EINVAL; 1250 1250 } 1251 1251 track->db_z_write_offset = radeon_get_ib_value(p, idx); 1252 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1252 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1253 1253 track->db_z_write_bo = reloc->robj; 1254 1254 track->db_dirty = true; 1255 1255 break; ··· 1261 1261 return -EINVAL; 1262 1262 } 1263 1263 track->db_s_read_offset = radeon_get_ib_value(p, idx); 1264 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1264 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1265 1265 track->db_s_read_bo = reloc->robj; 1266 1266 track->db_dirty = true; 1267 1267 break; ··· 1273 1273 return -EINVAL; 1274 1274 } 1275 1275 track->db_s_write_offset = radeon_get_ib_value(p, idx); 1276 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1276 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1277 1277 track->db_s_write_bo = reloc->robj; 1278 1278 track->db_dirty = true; 1279 1279 break; ··· 1297 1297 } 1298 1298 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; 1299 1299 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1300 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1300 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1301 1301 track->vgt_strmout_bo[tmp] = reloc->robj; 1302 1302 track->streamout_dirty = true; 1303 1303 break; ··· 1317 1317 "0x%04X\n", reg); 1318 1318 return -EINVAL; 1319 1319 } 1320 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1320 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1321 1321 case CB_TARGET_MASK: 1322 1322 track->cb_target_mask = radeon_get_ib_value(p, idx); 1323 1323 track->cb_dirty = true; ··· 1381 1381 "0x%04X\n", reg); 1382 1382 return -EINVAL; 1383 1383 } 1384 - ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1385 - track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1384 + ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1385 + track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1386 1386 } 1387 1387 track->cb_dirty = true; 1388 1388 break; ··· 1399 1399 "0x%04X\n", reg); 1400 1400 return -EINVAL; 1401 1401 } 1402 - ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1403 - track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1402 + ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1403 + track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1404 1404 } 1405 1405 track->cb_dirty = true; 1406 1406 break; ··· 1461 1461 return -EINVAL; 1462 1462 } 1463 1463 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1464 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1464 + if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1465 1465 unsigned bankw, bankh, mtaspect, tile_split; 1466 1466 1467 - evergreen_tiling_fields(reloc->lobj.tiling_flags, 1467 + evergreen_tiling_fields(reloc->tiling_flags, 1468 1468 &bankw, &bankh, &mtaspect, 1469 1469 &tile_split); 1470 1470 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); ··· 1489 1489 return -EINVAL; 1490 1490 } 1491 1491 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1492 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1492 + if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1493 1493 unsigned bankw, bankh, mtaspect, tile_split; 1494 1494 1495 - evergreen_tiling_fields(reloc->lobj.tiling_flags, 1495 + evergreen_tiling_fields(reloc->tiling_flags, 1496 1496 &bankw, &bankh, &mtaspect, 1497 1497 &tile_split); 1498 1498 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); ··· 1520 1520 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1521 1521 return -EINVAL; 1522 1522 } 1523 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1523 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1524 1524 track->cb_color_fmask_bo[tmp] = reloc->robj; 1525 1525 break; 1526 1526 case CB_COLOR0_CMASK: ··· 1537 1537 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1538 1538 return -EINVAL; 1539 1539 } 1540 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1540 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1541 1541 track->cb_color_cmask_bo[tmp] = reloc->robj; 1542 1542 break; 1543 1543 case CB_COLOR0_FMASK_SLICE: ··· 1578 1578 } 1579 1579 tmp = (reg - CB_COLOR0_BASE) / 0x3c; 1580 1580 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); 1581 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1581 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1582 1582 track->cb_color_bo[tmp] = reloc->robj; 1583 1583 track->cb_dirty = true; 1584 1584 break; ··· 1594 1594 } 1595 1595 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; 1596 1596 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); 1597 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1597 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1598 1598 track->cb_color_bo[tmp] = reloc->robj; 1599 1599 track->cb_dirty = true; 1600 1600 break; ··· 1606 1606 return -EINVAL; 1607 1607 } 1608 1608 track->htile_offset = radeon_get_ib_value(p, idx); 1609 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1609 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1610 1610 track->htile_bo = reloc->robj; 1611 1611 track->db_dirty = true; 1612 1612 break; ··· 1723 1723 "0x%04X\n", reg); 1724 1724 return -EINVAL; 1725 1725 } 1726 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1726 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1727 1727 break; 1728 1728 case SX_MEMORY_EXPORT_BASE: 1729 1729 if (p->rdev->family >= CHIP_CAYMAN) { ··· 1737 1737 "0x%04X\n", reg); 1738 1738 return -EINVAL; 1739 1739 } 1740 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1740 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1741 1741 break; 1742 1742 case CAYMAN_SX_SCATTER_EXPORT_BASE: 1743 1743 if (p->rdev->family < CHIP_CAYMAN) { ··· 1751 1751 "0x%04X\n", reg); 1752 1752 return -EINVAL; 1753 1753 } 1754 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1754 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1755 1755 break; 1756 1756 case SX_MISC: 1757 1757 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; ··· 1836 1836 return -EINVAL; 1837 1837 } 1838 1838 1839 - offset = reloc->lobj.gpu_offset + 1839 + offset = reloc->gpu_offset + 1840 1840 (idx_value & 0xfffffff0) + 1841 1841 ((u64)(tmp & 0xff) << 32); 1842 1842 ··· 1882 1882 return -EINVAL; 1883 1883 } 1884 1884 1885 - offset = reloc->lobj.gpu_offset + 1885 + offset = reloc->gpu_offset + 1886 1886 idx_value + 1887 1887 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1888 1888 ··· 1909 1909 return -EINVAL; 1910 1910 } 1911 1911 1912 - offset = reloc->lobj.gpu_offset + 1912 + offset = reloc->gpu_offset + 1913 1913 idx_value + 1914 1914 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1915 1915 ··· 1937 1937 return -EINVAL; 1938 1938 } 1939 1939 1940 - offset = reloc->lobj.gpu_offset + 1940 + offset = reloc->gpu_offset + 1941 1941 radeon_get_ib_value(p, idx+1) + 1942 1942 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1943 1943 ··· 2027 2027 DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2028 2028 return -EINVAL; 2029 2029 } 2030 - ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); 2030 + ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); 2031 2031 r = evergreen_cs_track_check(p); 2032 2032 if (r) { 2033 2033 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); ··· 2049 2049 return -EINVAL; 2050 2050 } 2051 2051 2052 - offset = reloc->lobj.gpu_offset + 2052 + offset = reloc->gpu_offset + 2053 2053 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2054 2054 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2055 2055 ··· 2106 2106 tmp = radeon_get_ib_value(p, idx) + 2107 2107 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 2108 2108 2109 - offset = reloc->lobj.gpu_offset + tmp; 2109 + offset = reloc->gpu_offset + tmp; 2110 2110 2111 2111 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 2112 2112 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", ··· 2144 2144 tmp = radeon_get_ib_value(p, idx+2) + 2145 2145 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); 2146 2146 2147 - offset = reloc->lobj.gpu_offset + tmp; 2147 + offset = reloc->gpu_offset + tmp; 2148 2148 2149 2149 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 2150 2150 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", ··· 2174 2174 DRM_ERROR("bad SURFACE_SYNC\n"); 2175 2175 return -EINVAL; 2176 2176 } 2177 - ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2177 + ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 2178 2178 } 2179 2179 break; 2180 2180 case PACKET3_EVENT_WRITE: ··· 2190 2190 DRM_ERROR("bad EVENT_WRITE\n"); 2191 2191 return -EINVAL; 2192 2192 } 2193 - offset = reloc->lobj.gpu_offset + 2193 + offset = reloc->gpu_offset + 2194 2194 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + 2195 2195 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2196 2196 ··· 2212 2212 return -EINVAL; 2213 2213 } 2214 2214 2215 - offset = reloc->lobj.gpu_offset + 2215 + offset = reloc->gpu_offset + 2216 2216 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2217 2217 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2218 2218 ··· 2234 2234 return -EINVAL; 2235 2235 } 2236 2236 2237 - offset = reloc->lobj.gpu_offset + 2237 + offset = reloc->gpu_offset + 2238 2238 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2239 2239 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2240 2240 ··· 2302 2302 } 2303 2303 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 2304 2304 ib[idx+1+(i*8)+1] |= 2305 - TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 2306 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 2305 + TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 2306 + if (reloc->tiling_flags & RADEON_TILING_MACRO) { 2307 2307 unsigned bankw, bankh, mtaspect, tile_split; 2308 2308 2309 - evergreen_tiling_fields(reloc->lobj.tiling_flags, 2309 + evergreen_tiling_fields(reloc->tiling_flags, 2310 2310 &bankw, &bankh, &mtaspect, 2311 2311 &tile_split); 2312 2312 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); ··· 2318 2318 } 2319 2319 } 2320 2320 texture = reloc->robj; 2321 - toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2321 + toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 2322 2322 2323 2323 /* tex mip base */ 2324 2324 tex_dim = ib[idx+1+(i*8)+0] & 0x7; ··· 2337 2337 DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2338 2338 return -EINVAL; 2339 2339 } 2340 - moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2340 + moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 2341 2341 mipmap = reloc->robj; 2342 2342 } 2343 2343 ··· 2364 2364 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; 2365 2365 } 2366 2366 2367 - offset64 = reloc->lobj.gpu_offset + offset; 2367 + offset64 = reloc->gpu_offset + offset; 2368 2368 ib[idx+1+(i*8)+0] = offset64; 2369 2369 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | 2370 2370 (upper_32_bits(offset64) & 0xff); ··· 2445 2445 offset + 4, radeon_bo_size(reloc->robj)); 2446 2446 return -EINVAL; 2447 2447 } 2448 - offset += reloc->lobj.gpu_offset; 2448 + offset += reloc->gpu_offset; 2449 2449 ib[idx+1] = offset; 2450 2450 ib[idx+2] = upper_32_bits(offset) & 0xff; 2451 2451 } ··· 2464 2464 offset + 4, radeon_bo_size(reloc->robj)); 2465 2465 return -EINVAL; 2466 2466 } 2467 - offset += reloc->lobj.gpu_offset; 2467 + offset += reloc->gpu_offset; 2468 2468 ib[idx+3] = offset; 2469 2469 ib[idx+4] = upper_32_bits(offset) & 0xff; 2470 2470 } ··· 2493 2493 offset + 8, radeon_bo_size(reloc->robj)); 2494 2494 return -EINVAL; 2495 2495 } 2496 - offset += reloc->lobj.gpu_offset; 2496 + offset += reloc->gpu_offset; 2497 2497 ib[idx+0] = offset; 2498 2498 ib[idx+1] = upper_32_bits(offset) & 0xff; 2499 2499 break; ··· 2518 2518 offset + 4, radeon_bo_size(reloc->robj)); 2519 2519 return -EINVAL; 2520 2520 } 2521 - offset += reloc->lobj.gpu_offset; 2521 + offset += reloc->gpu_offset; 2522 2522 ib[idx+1] = offset; 2523 2523 ib[idx+2] = upper_32_bits(offset) & 0xff; 2524 2524 } else { ··· 2542 2542 offset + 4, radeon_bo_size(reloc->robj)); 2543 2543 return -EINVAL; 2544 2544 } 2545 - offset += reloc->lobj.gpu_offset; 2545 + offset += reloc->gpu_offset; 2546 2546 ib[idx+3] = offset; 2547 2547 ib[idx+4] = upper_32_bits(offset) & 0xff; 2548 2548 } else { ··· 2717 2717 dst_offset = radeon_get_ib_value(p, idx+1); 2718 2718 dst_offset <<= 8; 2719 2719 2720 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2720 + ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2721 2721 p->idx += count + 7; 2722 2722 break; 2723 2723 /* linear */ ··· 2725 2725 dst_offset = radeon_get_ib_value(p, idx+1); 2726 2726 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2727 2727 2728 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2729 - ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2728 + ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2729 + ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2730 2730 p->idx += count + 3; 2731 2731 break; 2732 2732 default: ··· 2768 2768 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2769 2769 return -EINVAL; 2770 2770 } 2771 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2772 - ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2773 - ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2774 - ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2771 + ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2772 + ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2773 + ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2774 + ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2775 2775 p->idx += 5; 2776 2776 break; 2777 2777 /* Copy L2T/T2L */ ··· 2781 2781 /* tiled src, linear dst */ 2782 2782 src_offset = radeon_get_ib_value(p, idx+1); 2783 2783 src_offset <<= 8; 2784 - ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); 2784 + ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 2785 2785 2786 2786 dst_offset = radeon_get_ib_value(p, idx + 7); 2787 2787 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; 2788 - ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2789 - ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2788 + ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2789 + ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2790 2790 } else { 2791 2791 /* linear src, tiled dst */ 2792 2792 src_offset = radeon_get_ib_value(p, idx+7); 2793 2793 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; 2794 - ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2795 - ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2794 + ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2795 + ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2796 2796 2797 2797 dst_offset = radeon_get_ib_value(p, idx+1); 2798 2798 dst_offset <<= 8; 2799 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2799 + ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2800 2800 } 2801 2801 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2802 2802 dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n", ··· 2827 2827 dst_offset + count, radeon_bo_size(dst_reloc->robj)); 2828 2828 return -EINVAL; 2829 2829 } 2830 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff); 2831 - ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); 2832 - ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2833 - ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2830 + ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); 2831 + ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); 2832 + ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2833 + ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2834 2834 p->idx += 5; 2835 2835 break; 2836 2836 /* Copy L2L, partial */ ··· 2840 2840 DRM_ERROR("L2L Partial is cayman only !\n"); 2841 2841 return -EINVAL; 2842 2842 } 2843 - ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); 2844 - ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2845 - ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff); 2846 - ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2843 + ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); 2844 + ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2845 + ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); 2846 + ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2847 2847 2848 2848 p->idx += 9; 2849 2849 break; ··· 2876 2876 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 2877 2877 return -EINVAL; 2878 2878 } 2879 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2880 - ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc); 2881 - ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2882 - ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2883 - ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff; 2884 - ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2879 + ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2880 + ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); 2881 + ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2882 + ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2883 + ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; 2884 + ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2885 2885 p->idx += 7; 2886 2886 break; 2887 2887 /* Copy L2T Frame to Field */ ··· 2916 2916 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 2917 2917 return -EINVAL; 2918 2918 } 2919 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2920 - ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8); 2921 - ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2922 - ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2919 + ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2920 + ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); 2921 + ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2922 + ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2923 2923 p->idx += 10; 2924 2924 break; 2925 2925 /* Copy L2T/T2L, partial */ ··· 2932 2932 /* detile bit */ 2933 2933 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 2934 2934 /* tiled src, linear dst */ 2935 - ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); 2935 + ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 2936 2936 2937 - ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2938 - ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2937 + ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2938 + ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2939 2939 } else { 2940 2940 /* linear src, tiled dst */ 2941 - ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2942 - ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2941 + ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2942 + ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2943 2943 2944 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2944 + ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2945 2945 } 2946 2946 p->idx += 12; 2947 2947 break; ··· 2978 2978 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 2979 2979 return -EINVAL; 2980 2980 } 2981 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2982 - ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8); 2983 - ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2984 - ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2981 + ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2982 + ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); 2983 + ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2984 + ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2985 2985 p->idx += 10; 2986 2986 break; 2987 2987 /* Copy L2T/T2L (tile units) */ ··· 2992 2992 /* tiled src, linear dst */ 2993 2993 src_offset = radeon_get_ib_value(p, idx+1); 2994 2994 src_offset <<= 8; 2995 - ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); 2995 + ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 2996 2996 2997 2997 dst_offset = radeon_get_ib_value(p, idx+7); 2998 2998 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; 2999 - ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 3000 - ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2999 + ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 3000 + ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 3001 3001 } else { 3002 3002 /* linear src, tiled dst */ 3003 3003 src_offset = radeon_get_ib_value(p, idx+7); 3004 3004 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; 3005 - ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 3006 - ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 3005 + ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 3006 + ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 3007 3007 3008 3008 dst_offset = radeon_get_ib_value(p, idx+1); 3009 3009 dst_offset <<= 8; 3010 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 3010 + ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 3011 3011 } 3012 3012 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3013 3013 dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n", ··· 3028 3028 DRM_ERROR("L2T, T2L Partial is cayman only !\n"); 3029 3029 return -EINVAL; 3030 3030 } 3031 - ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); 3032 - ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 3031 + ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 3032 + ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); 3033 3033 p->idx += 13; 3034 3034 break; 3035 3035 /* Copy L2T broadcast (tile units) */ ··· 3065 3065 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3066 3066 return -EINVAL; 3067 3067 } 3068 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 3069 - ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8); 3070 - ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 3071 - ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 3068 + ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 3069 + ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); 3070 + ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 3071 + ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 3072 3072 p->idx += 10; 3073 3073 break; 3074 3074 default: ··· 3089 3089 dst_offset, radeon_bo_size(dst_reloc->robj)); 3090 3090 return -EINVAL; 3091 3091 } 3092 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 3093 - ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000; 3092 + ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 3093 + ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; 3094 3094 p->idx += 4; 3095 3095 break; 3096 3096 case DMA_PACKET_NOP:

+20 -20

drivers/gpu/drm/radeon/r100.c

··· 1274 1274 1275 1275 value = radeon_get_ib_value(p, idx); 1276 1276 tmp = value & 0x003fffff; 1277 - tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 1277 + tmp += (((u32)reloc->gpu_offset) >> 10); 1278 1278 1279 1279 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1280 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1280 + if (reloc->tiling_flags & RADEON_TILING_MACRO) 1281 1281 tile_flags |= RADEON_DST_TILE_MACRO; 1282 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1282 + if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1283 1283 if (reg == RADEON_SRC_PITCH_OFFSET) { 1284 1284 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1285 1285 radeon_cs_dump_packet(p, pkt); ··· 1325 1325 return r; 1326 1326 } 1327 1327 idx_value = radeon_get_ib_value(p, idx); 1328 - ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1328 + ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1329 1329 1330 1330 track->arrays[i + 0].esize = idx_value >> 8; 1331 1331 track->arrays[i + 0].robj = reloc->robj; ··· 1337 1337 radeon_cs_dump_packet(p, pkt); 1338 1338 return r; 1339 1339 } 1340 - ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 1340 + ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); 1341 1341 track->arrays[i + 1].robj = reloc->robj; 1342 1342 track->arrays[i + 1].esize = idx_value >> 24; 1343 1343 track->arrays[i + 1].esize &= 0x7F; ··· 1351 1351 return r; 1352 1352 } 1353 1353 idx_value = radeon_get_ib_value(p, idx); 1354 - ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1354 + ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1355 1355 track->arrays[i + 0].robj = reloc->robj; 1356 1356 track->arrays[i + 0].esize = idx_value >> 8; 1357 1357 track->arrays[i + 0].esize &= 0x7F; ··· 1594 1594 track->zb.robj = reloc->robj; 1595 1595 track->zb.offset = idx_value; 1596 1596 track->zb_dirty = true; 1597 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1597 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1598 1598 break; 1599 1599 case RADEON_RB3D_COLOROFFSET: 1600 1600 r = radeon_cs_packet_next_reloc(p, &reloc, 0); ··· 1607 1607 track->cb[0].robj = reloc->robj; 1608 1608 track->cb[0].offset = idx_value; 1609 1609 track->cb_dirty = true; 1610 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1610 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1611 1611 break; 1612 1612 case RADEON_PP_TXOFFSET_0: 1613 1613 case RADEON_PP_TXOFFSET_1: ··· 1621 1621 return r; 1622 1622 } 1623 1623 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1624 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1624 + if (reloc->tiling_flags & RADEON_TILING_MACRO) 1625 1625 tile_flags |= RADEON_TXO_MACRO_TILE; 1626 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1626 + if (reloc->tiling_flags & RADEON_TILING_MICRO) 1627 1627 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1628 1628 1629 1629 tmp = idx_value & ~(0x7 << 2); 1630 1630 tmp |= tile_flags; 1631 - ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); 1631 + ib[idx] = tmp + ((u32)reloc->gpu_offset); 1632 1632 } else 1633 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1633 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1634 1634 track->textures[i].robj = reloc->robj; 1635 1635 track->tex_dirty = true; 1636 1636 break; ··· 1648 1648 return r; 1649 1649 } 1650 1650 track->textures[0].cube_info[i].offset = idx_value; 1651 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1651 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1652 1652 track->textures[0].cube_info[i].robj = reloc->robj; 1653 1653 track->tex_dirty = true; 1654 1654 break; ··· 1666 1666 return r; 1667 1667 } 1668 1668 track->textures[1].cube_info[i].offset = idx_value; 1669 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1669 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1670 1670 track->textures[1].cube_info[i].robj = reloc->robj; 1671 1671 track->tex_dirty = true; 1672 1672 break; ··· 1684 1684 return r; 1685 1685 } 1686 1686 track->textures[2].cube_info[i].offset = idx_value; 1687 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1687 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1688 1688 track->textures[2].cube_info[i].robj = reloc->robj; 1689 1689 track->tex_dirty = true; 1690 1690 break; ··· 1702 1702 return r; 1703 1703 } 1704 1704 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1705 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1705 + if (reloc->tiling_flags & RADEON_TILING_MACRO) 1706 1706 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1707 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1707 + if (reloc->tiling_flags & RADEON_TILING_MICRO) 1708 1708 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1709 1709 1710 1710 tmp = idx_value & ~(0x7 << 16); ··· 1772 1772 radeon_cs_dump_packet(p, pkt); 1773 1773 return r; 1774 1774 } 1775 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1775 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1776 1776 break; 1777 1777 case RADEON_PP_CNTL: 1778 1778 { ··· 1932 1932 radeon_cs_dump_packet(p, pkt); 1933 1933 return r; 1934 1934 } 1935 - ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1935 + ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); 1936 1936 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1937 1937 if (r) { 1938 1938 return r; ··· 1946 1946 radeon_cs_dump_packet(p, pkt); 1947 1947 return r; 1948 1948 } 1949 - ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1949 + ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); 1950 1950 track->num_arrays = 1; 1951 1951 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1952 1952

+10 -10

drivers/gpu/drm/radeon/r200.c

··· 185 185 track->zb.robj = reloc->robj; 186 186 track->zb.offset = idx_value; 187 187 track->zb_dirty = true; 188 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 188 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 189 189 break; 190 190 case RADEON_RB3D_COLOROFFSET: 191 191 r = radeon_cs_packet_next_reloc(p, &reloc, 0); ··· 198 198 track->cb[0].robj = reloc->robj; 199 199 track->cb[0].offset = idx_value; 200 200 track->cb_dirty = true; 201 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 201 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 202 202 break; 203 203 case R200_PP_TXOFFSET_0: 204 204 case R200_PP_TXOFFSET_1: ··· 215 215 return r; 216 216 } 217 217 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 218 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 218 + if (reloc->tiling_flags & RADEON_TILING_MACRO) 219 219 tile_flags |= R200_TXO_MACRO_TILE; 220 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 220 + if (reloc->tiling_flags & RADEON_TILING_MICRO) 221 221 tile_flags |= R200_TXO_MICRO_TILE; 222 222 223 223 tmp = idx_value & ~(0x7 << 2); 224 224 tmp |= tile_flags; 225 - ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); 225 + ib[idx] = tmp + ((u32)reloc->gpu_offset); 226 226 } else 227 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 227 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 228 228 track->textures[i].robj = reloc->robj; 229 229 track->tex_dirty = true; 230 230 break; ··· 268 268 return r; 269 269 } 270 270 track->textures[i].cube_info[face - 1].offset = idx_value; 271 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 271 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 272 272 track->textures[i].cube_info[face - 1].robj = reloc->robj; 273 273 track->tex_dirty = true; 274 274 break; ··· 287 287 } 288 288 289 289 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 290 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 290 + if (reloc->tiling_flags & RADEON_TILING_MACRO) 291 291 tile_flags |= RADEON_COLOR_TILE_ENABLE; 292 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 292 + if (reloc->tiling_flags & RADEON_TILING_MICRO) 293 293 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 294 294 295 295 tmp = idx_value & ~(0x7 << 16); ··· 362 362 radeon_cs_dump_packet(p, pkt); 363 363 return r; 364 364 } 365 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 365 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 366 366 break; 367 367 case RADEON_PP_CNTL: 368 368 {

+16 -16

drivers/gpu/drm/radeon/r300.c

··· 640 640 track->cb[i].robj = reloc->robj; 641 641 track->cb[i].offset = idx_value; 642 642 track->cb_dirty = true; 643 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 643 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 644 644 break; 645 645 case R300_ZB_DEPTHOFFSET: 646 646 r = radeon_cs_packet_next_reloc(p, &reloc, 0); ··· 653 653 track->zb.robj = reloc->robj; 654 654 track->zb.offset = idx_value; 655 655 track->zb_dirty = true; 656 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 656 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 657 657 break; 658 658 case R300_TX_OFFSET_0: 659 659 case R300_TX_OFFSET_0+4: ··· 682 682 683 683 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 684 684 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 685 - ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); 685 + ((idx_value & ~31) + (u32)reloc->gpu_offset); 686 686 } else { 687 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 687 + if (reloc->tiling_flags & RADEON_TILING_MACRO) 688 688 tile_flags |= R300_TXO_MACRO_TILE; 689 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 689 + if (reloc->tiling_flags & RADEON_TILING_MICRO) 690 690 tile_flags |= R300_TXO_MICRO_TILE; 691 - else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 691 + else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 692 692 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 693 693 694 - tmp = idx_value + ((u32)reloc->lobj.gpu_offset); 694 + tmp = idx_value + ((u32)reloc->gpu_offset); 695 695 tmp |= tile_flags; 696 696 ib[idx] = tmp; 697 697 } ··· 753 753 return r; 754 754 } 755 755 756 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 756 + if (reloc->tiling_flags & RADEON_TILING_MACRO) 757 757 tile_flags |= R300_COLOR_TILE_ENABLE; 758 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 758 + if (reloc->tiling_flags & RADEON_TILING_MICRO) 759 759 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 760 - else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 760 + else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 761 761 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 762 762 763 763 tmp = idx_value & ~(0x7 << 16); ··· 838 838 return r; 839 839 } 840 840 841 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 841 + if (reloc->tiling_flags & RADEON_TILING_MACRO) 842 842 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 843 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 843 + if (reloc->tiling_flags & RADEON_TILING_MICRO) 844 844 tile_flags |= R300_DEPTHMICROTILE_TILED; 845 - else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 845 + else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 846 846 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 847 847 848 848 tmp = idx_value & ~(0x7 << 16); ··· 1052 1052 radeon_cs_dump_packet(p, pkt); 1053 1053 return r; 1054 1054 } 1055 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1055 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1056 1056 break; 1057 1057 case 0x4e0c: 1058 1058 /* RB3D_COLOR_CHANNEL_MASK */ ··· 1097 1097 track->aa.robj = reloc->robj; 1098 1098 track->aa.offset = idx_value; 1099 1099 track->aa_dirty = true; 1100 - ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1100 + ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1101 1101 break; 1102 1102 case R300_RB3D_AARESOLVE_PITCH: 1103 1103 track->aa.pitch = idx_value & 0x3FFE; ··· 1162 1162 radeon_cs_dump_packet(p, pkt); 1163 1163 return r; 1164 1164 } 1165 - ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1165 + ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1166 1166 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1167 1167 if (r) { 1168 1168 return r;

+55 -55

drivers/gpu/drm/radeon/r600_cs.c

··· 1022 1022 "0x%04X\n", reg); 1023 1023 return -EINVAL; 1024 1024 } 1025 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1025 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1026 1026 break; 1027 1027 case SQ_CONFIG: 1028 1028 track->sq_config = radeon_get_ib_value(p, idx); ··· 1043 1043 track->db_depth_info = radeon_get_ib_value(p, idx); 1044 1044 ib[idx] &= C_028010_ARRAY_MODE; 1045 1045 track->db_depth_info &= C_028010_ARRAY_MODE; 1046 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1046 + if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1047 1047 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); 1048 1048 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); 1049 1049 } else { ··· 1084 1084 } 1085 1085 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; 1086 1086 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1087 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1087 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1088 1088 track->vgt_strmout_bo[tmp] = reloc->robj; 1089 - track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset; 1089 + track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; 1090 1090 track->streamout_dirty = true; 1091 1091 break; 1092 1092 case VGT_STRMOUT_BUFFER_SIZE_0: ··· 1105 1105 "0x%04X\n", reg); 1106 1106 return -EINVAL; 1107 1107 } 1108 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1108 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1109 1109 break; 1110 1110 case R_028238_CB_TARGET_MASK: 1111 1111 track->cb_target_mask = radeon_get_ib_value(p, idx); ··· 1142 1142 } 1143 1143 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; 1144 1144 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1145 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1145 + if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1146 1146 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); 1147 1147 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); 1148 - } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1148 + } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1149 1149 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); 1150 1150 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); 1151 1151 } ··· 1214 1214 } 1215 1215 track->cb_color_frag_bo[tmp] = reloc->robj; 1216 1216 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; 1217 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1217 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1218 1218 } 1219 1219 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1220 1220 track->cb_dirty = true; ··· 1245 1245 } 1246 1246 track->cb_color_tile_bo[tmp] = reloc->robj; 1247 1247 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; 1248 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1248 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1249 1249 } 1250 1250 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1251 1251 track->cb_dirty = true; ··· 1281 1281 } 1282 1282 tmp = (reg - CB_COLOR0_BASE) / 4; 1283 1283 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1284 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1284 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1285 1285 track->cb_color_base_last[tmp] = ib[idx]; 1286 1286 track->cb_color_bo[tmp] = reloc->robj; 1287 - track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; 1287 + track->cb_color_bo_mc[tmp] = reloc->gpu_offset; 1288 1288 track->cb_dirty = true; 1289 1289 break; 1290 1290 case DB_DEPTH_BASE: ··· 1295 1295 return -EINVAL; 1296 1296 } 1297 1297 track->db_offset = radeon_get_ib_value(p, idx) << 8; 1298 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1298 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1299 1299 track->db_bo = reloc->robj; 1300 - track->db_bo_mc = reloc->lobj.gpu_offset; 1300 + track->db_bo_mc = reloc->gpu_offset; 1301 1301 track->db_dirty = true; 1302 1302 break; 1303 1303 case DB_HTILE_DATA_BASE: ··· 1308 1308 return -EINVAL; 1309 1309 } 1310 1310 track->htile_offset = radeon_get_ib_value(p, idx) << 8; 1311 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1311 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1312 1312 track->htile_bo = reloc->robj; 1313 1313 track->db_dirty = true; 1314 1314 break; ··· 1377 1377 "0x%04X\n", reg); 1378 1378 return -EINVAL; 1379 1379 } 1380 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1380 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1381 1381 break; 1382 1382 case SX_MEMORY_EXPORT_BASE: 1383 1383 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); ··· 1386 1386 "0x%04X\n", reg); 1387 1387 return -EINVAL; 1388 1388 } 1389 - ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1389 + ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1390 1390 break; 1391 1391 case SX_MISC: 1392 1392 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; ··· 1672 1672 return -EINVAL; 1673 1673 } 1674 1674 1675 - offset = reloc->lobj.gpu_offset + 1675 + offset = reloc->gpu_offset + 1676 1676 (idx_value & 0xfffffff0) + 1677 1677 ((u64)(tmp & 0xff) << 32); 1678 1678 ··· 1713 1713 return -EINVAL; 1714 1714 } 1715 1715 1716 - offset = reloc->lobj.gpu_offset + 1716 + offset = reloc->gpu_offset + 1717 1717 idx_value + 1718 1718 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1719 1719 ··· 1765 1765 return -EINVAL; 1766 1766 } 1767 1767 1768 - offset = reloc->lobj.gpu_offset + 1768 + offset = reloc->gpu_offset + 1769 1769 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + 1770 1770 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1771 1771 ··· 1805 1805 tmp = radeon_get_ib_value(p, idx) + 1806 1806 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1807 1807 1808 - offset = reloc->lobj.gpu_offset + tmp; 1808 + offset = reloc->gpu_offset + tmp; 1809 1809 1810 1810 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1811 1811 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", ··· 1835 1835 tmp = radeon_get_ib_value(p, idx+2) + 1836 1836 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); 1837 1837 1838 - offset = reloc->lobj.gpu_offset + tmp; 1838 + offset = reloc->gpu_offset + tmp; 1839 1839 1840 1840 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1841 1841 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", ··· 1861 1861 DRM_ERROR("bad SURFACE_SYNC\n"); 1862 1862 return -EINVAL; 1863 1863 } 1864 - ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1864 + ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1865 1865 } 1866 1866 break; 1867 1867 case PACKET3_EVENT_WRITE: ··· 1877 1877 DRM_ERROR("bad EVENT_WRITE\n"); 1878 1878 return -EINVAL; 1879 1879 } 1880 - offset = reloc->lobj.gpu_offset + 1880 + offset = reloc->gpu_offset + 1881 1881 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + 1882 1882 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1883 1883 ··· 1899 1899 return -EINVAL; 1900 1900 } 1901 1901 1902 - offset = reloc->lobj.gpu_offset + 1902 + offset = reloc->gpu_offset + 1903 1903 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 1904 1904 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1905 1905 ··· 1964 1964 DRM_ERROR("bad SET_RESOURCE\n"); 1965 1965 return -EINVAL; 1966 1966 } 1967 - base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1967 + base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1968 1968 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1969 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1969 + if (reloc->tiling_flags & RADEON_TILING_MACRO) 1970 1970 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1971 - else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1971 + else if (reloc->tiling_flags & RADEON_TILING_MICRO) 1972 1972 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1973 1973 } 1974 1974 texture = reloc->robj; ··· 1978 1978 DRM_ERROR("bad SET_RESOURCE\n"); 1979 1979 return -EINVAL; 1980 1980 } 1981 - mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1981 + mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1982 1982 mipmap = reloc->robj; 1983 1983 r = r600_check_texture_resource(p, idx+(i*7)+1, 1984 1984 texture, mipmap, 1985 1985 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), 1986 1986 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), 1987 - reloc->lobj.tiling_flags); 1987 + reloc->tiling_flags); 1988 1988 if (r) 1989 1989 return r; 1990 1990 ib[idx+1+(i*7)+2] += base_offset; ··· 2008 2008 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; 2009 2009 } 2010 2010 2011 - offset64 = reloc->lobj.gpu_offset + offset; 2011 + offset64 = reloc->gpu_offset + offset; 2012 2012 ib[idx+1+(i*8)+0] = offset64; 2013 2013 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | 2014 2014 (upper_32_bits(offset64) & 0xff); ··· 2118 2118 offset + 4, radeon_bo_size(reloc->robj)); 2119 2119 return -EINVAL; 2120 2120 } 2121 - ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2121 + ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 2122 2122 } 2123 2123 break; 2124 2124 case PACKET3_SURFACE_BASE_UPDATE: ··· 2151 2151 offset + 4, radeon_bo_size(reloc->robj)); 2152 2152 return -EINVAL; 2153 2153 } 2154 - offset += reloc->lobj.gpu_offset; 2154 + offset += reloc->gpu_offset; 2155 2155 ib[idx+1] = offset; 2156 2156 ib[idx+2] = upper_32_bits(offset) & 0xff; 2157 2157 } ··· 2170 2170 offset + 4, radeon_bo_size(reloc->robj)); 2171 2171 return -EINVAL; 2172 2172 } 2173 - offset += reloc->lobj.gpu_offset; 2173 + offset += reloc->gpu_offset; 2174 2174 ib[idx+3] = offset; 2175 2175 ib[idx+4] = upper_32_bits(offset) & 0xff; 2176 2176 } ··· 2199 2199 offset + 8, radeon_bo_size(reloc->robj)); 2200 2200 return -EINVAL; 2201 2201 } 2202 - offset += reloc->lobj.gpu_offset; 2202 + offset += reloc->gpu_offset; 2203 2203 ib[idx+0] = offset; 2204 2204 ib[idx+1] = upper_32_bits(offset) & 0xff; 2205 2205 break; ··· 2224 2224 offset + 4, radeon_bo_size(reloc->robj)); 2225 2225 return -EINVAL; 2226 2226 } 2227 - offset += reloc->lobj.gpu_offset; 2227 + offset += reloc->gpu_offset; 2228 2228 ib[idx+1] = offset; 2229 2229 ib[idx+2] = upper_32_bits(offset) & 0xff; 2230 2230 } else { ··· 2248 2248 offset + 4, radeon_bo_size(reloc->robj)); 2249 2249 return -EINVAL; 2250 2250 } 2251 - offset += reloc->lobj.gpu_offset; 2251 + offset += reloc->gpu_offset; 2252 2252 ib[idx+3] = offset; 2253 2253 ib[idx+4] = upper_32_bits(offset) & 0xff; 2254 2254 } else { ··· 2505 2505 dst_offset = radeon_get_ib_value(p, idx+1); 2506 2506 dst_offset <<= 8; 2507 2507 2508 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2508 + ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2509 2509 p->idx += count + 5; 2510 2510 } else { 2511 2511 dst_offset = radeon_get_ib_value(p, idx+1); 2512 2512 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2513 2513 2514 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2515 - ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2514 + ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2515 + ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2516 2516 p->idx += count + 3; 2517 2517 } 2518 2518 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { ··· 2539 2539 /* tiled src, linear dst */ 2540 2540 src_offset = radeon_get_ib_value(p, idx+1); 2541 2541 src_offset <<= 8; 2542 - ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); 2542 + ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 2543 2543 2544 2544 dst_offset = radeon_get_ib_value(p, idx+5); 2545 2545 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 2546 - ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2547 - ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2546 + ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2547 + ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2548 2548 } else { 2549 2549 /* linear src, tiled dst */ 2550 2550 src_offset = radeon_get_ib_value(p, idx+5); 2551 2551 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 2552 - ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2553 - ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2552 + ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2553 + ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2554 2554 2555 2555 dst_offset = radeon_get_ib_value(p, idx+1); 2556 2556 dst_offset <<= 8; 2557 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2557 + ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2558 2558 } 2559 2559 p->idx += 7; 2560 2560 } else { ··· 2564 2564 dst_offset = radeon_get_ib_value(p, idx+1); 2565 2565 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2566 2566 2567 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2568 - ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2569 - ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2570 - ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2567 + ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2568 + ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2569 + ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2570 + ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2571 2571 p->idx += 5; 2572 2572 } else { 2573 2573 src_offset = radeon_get_ib_value(p, idx+2); ··· 2575 2575 dst_offset = radeon_get_ib_value(p, idx+1); 2576 2576 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; 2577 2577 2578 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2579 - ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2580 - ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2581 - ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16; 2578 + ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2579 + ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2580 + ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2581 + ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; 2582 2582 p->idx += 4; 2583 2583 } 2584 2584 } ··· 2610 2610 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2611 2611 return -EINVAL; 2612 2612 } 2613 - ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2614 - ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000; 2613 + ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2614 + ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; 2615 2615 p->idx += 4; 2616 2616 break; 2617 2617 case DMA_PACKET_NOP:

+9 -15

drivers/gpu/drm/radeon/radeon.h

··· 479 479 }; 480 480 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 481 481 482 - struct radeon_bo_list { 483 - struct ttm_validate_buffer tv; 484 - struct radeon_bo *bo; 485 - uint64_t gpu_offset; 486 - unsigned domain; 487 - unsigned alt_domain; 488 - u32 tiling_flags; 489 - }; 490 - 491 482 int radeon_gem_debugfs_init(struct radeon_device *rdev); 492 483 493 484 /* sub-allocation manager, it has to be protected by another lock. ··· 978 987 struct radeon_cs_reloc { 979 988 struct drm_gem_object *gobj; 980 989 struct radeon_bo *robj; 981 - struct radeon_bo_list lobj; 990 + struct ttm_validate_buffer tv; 991 + uint64_t gpu_offset; 992 + unsigned domain; 993 + unsigned alt_domain; 994 + uint32_t tiling_flags; 982 995 uint32_t handle; 983 - uint32_t flags; 984 996 }; 985 997 986 998 struct radeon_cs_chunk { ··· 1007 1013 unsigned nrelocs; 1008 1014 struct radeon_cs_reloc *relocs; 1009 1015 struct radeon_cs_reloc **relocs_ptr; 1010 - struct radeon_bo_list *vm_bos; 1016 + struct radeon_cs_reloc *vm_bos; 1011 1017 struct list_head validated; 1012 1018 unsigned dma_reloc_idx; 1013 1019 /* indices of various chunks */ ··· 2797 2803 void radeon_vm_manager_fini(struct radeon_device *rdev); 2798 2804 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2799 2805 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2800 - struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2801 - struct radeon_vm *vm, 2802 - struct list_head *head); 2806 + struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2807 + struct radeon_vm *vm, 2808 + struct list_head *head); 2803 2809 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2804 2810 struct radeon_vm *vm, int ring); 2805 2811 void radeon_vm_flush(struct radeon_device *rdev,

+11 -12

drivers/gpu/drm/radeon/radeon_cs.c

··· 125 125 } 126 126 p->relocs_ptr[i] = &p->relocs[i]; 127 127 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); 128 - p->relocs[i].lobj.bo = p->relocs[i].robj; 129 128 130 129 /* The userspace buffer priorities are from 0 to 15. A higher 131 130 * number means the buffer is more important. ··· 140 141 if (p->ring == R600_RING_TYPE_UVD_INDEX && 141 142 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) { 142 143 /* TODO: is this still needed for NI+ ? */ 143 - p->relocs[i].lobj.domain = 144 + p->relocs[i].domain = 144 145 RADEON_GEM_DOMAIN_VRAM; 145 146 146 - p->relocs[i].lobj.alt_domain = 147 + p->relocs[i].alt_domain = 147 148 RADEON_GEM_DOMAIN_VRAM; 148 149 149 150 /* prioritize this over any other relocation */ ··· 152 153 uint32_t domain = r->write_domain ? 153 154 r->write_domain : r->read_domains; 154 155 155 - p->relocs[i].lobj.domain = domain; 156 + p->relocs[i].domain = domain; 156 157 if (domain == RADEON_GEM_DOMAIN_VRAM) 157 158 domain |= RADEON_GEM_DOMAIN_GTT; 158 - p->relocs[i].lobj.alt_domain = domain; 159 + p->relocs[i].alt_domain = domain; 159 160 } 160 161 161 - p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; 162 + p->relocs[i].tv.bo = &p->relocs[i].robj->tbo; 162 163 p->relocs[i].handle = r->handle; 163 164 164 - radeon_cs_buckets_add(&buckets, &p->relocs[i].lobj.tv.head, 165 + radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head, 165 166 priority); 166 167 } 167 168 ··· 355 356 static int cmp_size_smaller_first(void *priv, struct list_head *a, 356 357 struct list_head *b) 357 358 { 358 - struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head); 359 - struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head); 359 + struct radeon_cs_reloc *la = list_entry(a, struct radeon_cs_reloc, tv.head); 360 + struct radeon_cs_reloc *lb = list_entry(b, struct radeon_cs_reloc, tv.head); 360 361 361 362 /* Sort A before B if A is smaller. */ 362 - return (int)la->bo->tbo.num_pages - (int)lb->bo->tbo.num_pages; 363 + return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; 363 364 } 364 365 365 366 /** ··· 785 786 /* FIXME: we assume reloc size is 4 dwords */ 786 787 if (nomm) { 787 788 *cs_reloc = p->relocs; 788 - (*cs_reloc)->lobj.gpu_offset = 789 + (*cs_reloc)->gpu_offset = 789 790 (u64)relocs_chunk->kdata[idx + 3] << 32; 790 - (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; 791 + (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; 791 792 } else 792 793 *cs_reloc = p->relocs_ptr[(idx / 4)]; 793 794 return 0;

+2 -2

drivers/gpu/drm/radeon/radeon_object.c

··· 422 422 struct ww_acquire_ctx *ticket, 423 423 struct list_head *head, int ring) 424 424 { 425 - struct radeon_bo_list *lobj; 425 + struct radeon_cs_reloc *lobj; 426 426 struct radeon_bo *bo; 427 427 int r; 428 428 u64 bytes_moved = 0, initial_bytes_moved; ··· 434 434 } 435 435 436 436 list_for_each_entry(lobj, head, tv.head) { 437 - bo = lobj->bo; 437 + bo = lobj->robj; 438 438 if (!bo->pin_count) { 439 439 u32 domain = lobj->domain; 440 440 u32 current_domain =

+1 -1

drivers/gpu/drm/radeon/radeon_uvd.c

··· 453 453 } 454 454 455 455 reloc = p->relocs_ptr[(idx / 4)]; 456 - start = reloc->lobj.gpu_offset; 456 + start = reloc->gpu_offset; 457 457 end = start + radeon_bo_size(reloc->robj); 458 458 start += offset; 459 459

+1 -1

drivers/gpu/drm/radeon/radeon_vce.c

··· 461 461 return -EINVAL; 462 462 } 463 463 464 - offset += p->relocs_ptr[(idx / 4)]->lobj.gpu_offset; 464 + offset += p->relocs_ptr[(idx / 4)]->gpu_offset; 465 465 466 466 p->ib.ptr[lo] = offset & 0xFFFFFFFF; 467 467 p->ib.ptr[hi] = offset >> 32;

+14 -8

drivers/gpu/drm/radeon/radeon_vm.c

··· 125 125 * Add the page directory to the list of BOs to 126 126 * validate for command submission (cayman+). 127 127 */ 128 - struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 129 - struct radeon_vm *vm, 130 - struct list_head *head) 128 + struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 129 + struct radeon_vm *vm, 130 + struct list_head *head) 131 131 { 132 - struct radeon_bo_list *list; 132 + struct radeon_cs_reloc *list; 133 133 unsigned i, idx, size; 134 134 135 - size = (radeon_vm_num_pdes(rdev) + 1) * sizeof(struct radeon_bo_list); 135 + size = (radeon_vm_num_pdes(rdev) + 1) * sizeof(struct radeon_cs_reloc); 136 136 list = kmalloc(size, GFP_KERNEL); 137 137 if (!list) 138 138 return NULL; 139 139 140 140 /* add the vm page table to the list */ 141 - list[0].bo = vm->page_directory; 141 + list[0].gobj = NULL; 142 + list[0].robj = vm->page_directory; 142 143 list[0].domain = RADEON_GEM_DOMAIN_VRAM; 143 144 list[0].alt_domain = RADEON_GEM_DOMAIN_VRAM; 144 145 list[0].tv.bo = &vm->page_directory->tbo; 146 + list[0].tiling_flags = 0; 147 + list[0].handle = 0; 145 148 list_add(&list[0].tv.head, head); 146 149 147 150 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) { 148 151 if (!vm->page_tables[i].bo) 149 152 continue; 150 153 151 - list[idx].bo = vm->page_tables[i].bo; 154 + list[idx].gobj = NULL; 155 + list[idx].robj = vm->page_tables[i].bo; 152 156 list[idx].domain = RADEON_GEM_DOMAIN_VRAM; 153 157 list[idx].alt_domain = RADEON_GEM_DOMAIN_VRAM; 154 - list[idx].tv.bo = &list[idx].bo->tbo; 158 + list[idx].tv.bo = &list[idx].robj->tbo; 159 + list[idx].tiling_flags = 0; 160 + list[idx].handle = 0; 155 161 list_add(&list[idx++].tv.head, head); 156 162 } 157 163