ASoC: dt-bindings: fsl_spdif: Add two PLL clock source

Add two PLL clock source, they are the parent clocks of root clock
one is for 8kHz series rates, another one is for 11kHz series rates.
They are optional clocks, if there are such clocks, then driver
can switch between them for supporting more accurate rates.

Signed-off-by: Shengjiu Wang <[e-mail]>
Acked-by: Rob Herring <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Mark Brown <[e-mail]>

Documentation/devicetree/bindings/sound/fsl,spdif.yaml

···
           slave of the Shared Peripheral Bus and when two or more bus masters
           (CPU, DMA or DSP) try to access it. This property is optional depending
           on the SoC design.
+      - description: PLL clock source for 8kHz series rate, optional.
+      - description: PLL clock source for 11khz series rate, optional.
     minItems: 9
 
   clock-names:
···
       - const: rxtx6
       - const: rxtx7
       - const: spba
+      - const: pll8k
+      - const: pll11k
     minItems: 9
 
   big-endian: