···3535int tegra_core_process_id;3636enum tegra_revision tegra_revision;37373838+/* The BCT to use at boot is specified by board straps that can be read3939+ * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.4040+ */4141+int tegra_bct_strapping;4242+4343+#define STRAP_OPT 0x0084444+#define GMI_AD0 (1 << 4)4545+#define GMI_AD1 (1 << 5)4646+#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)4747+#define RAM_CODE_SHIFT 44848+3849static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {3950 [TEGRA_REVISION_UNKNOWN] = "unknown",4051 [TEGRA_REVISION_A01] = "A01",···1039210493 reg = tegra_fuse_readl(FUSE_SPARE_BIT);10594 tegra_core_process_id = (reg >> 12) & 3;9595+9696+ reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);9797+ tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;1069810799 tegra_revision = tegra_get_revision();108100
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arch/arm/mach-tegra/fuse.h
···4040extern int tegra_core_process_id;4141extern enum tegra_revision tegra_revision;42424343+extern int tegra_bct_strapping;4444+4345unsigned long long tegra_chip_uid(void);4446void tegra_init_fuse(void);4547