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dt-bindings: Document MIPS Broadcom STB power management nodes
Document the different nodes required for supporting S2/S3/S5 suspend
states on MIPS-based Broadcom STB SoCs.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Documentation/devicetree/bindings/mips/brcm/soc.txt
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Documentation/devicetree/bindings/mips/brcm/soc.txt
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The experimental -viper variants are for running Linux on the 3384's
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BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
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Power management
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----------------
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For power management (particularly, S2/S3/S5 system suspend), the following SoC
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components are needed:
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= Always-On control block (AON CTRL)
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This hardware provides control registers for the "always-on" (even in low-power
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modes) hardware, such as the Power Management State Machine (PMSM).
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Required properties:
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- compatible : should be one of
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"brcm,bcm7425-aon-ctrl"
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"brcm,bcm7429-aon-ctrl"
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"brcm,bcm7435-aon-ctrl" and
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"brcm,brcmstb-aon-ctrl"
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- reg : the register start and length for the AON CTRL block
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Example:
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syscon@410000 {
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compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
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reg = <0x410000 0x400>;
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};
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= Memory controllers
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A Broadcom STB SoC typically has a number of independent memory controllers,
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each of which may have several associated hardware blocks, which are versioned
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independently (control registers, DDR PHYs, etc.). One might consider
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describing these controllers as a parent "memory controllers" block, which
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contains N sub-nodes (one for each controller in the system), each of which is
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associated with a number of hardware register resources (e.g., its PHY.
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== MEMC (MEMory Controller)
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Represents a single memory controller instance.
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Required properties:
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- compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
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- ranges : should contain the child address in the parent address
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space, must be 0 here, and the register start and length of
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the entire memory controller (including all sub nodes: DDR PHY,
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arbiter, etc.)
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- #address-cells : must be 1
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- #size-cells : must be 1
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Example:
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memory-controller@0 {
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compatible = "brcm,brcmstb-memc", "simple-bus";
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ranges = <0x0 0x0 0xa000>;
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#address-cells = <1>;
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#size-cells = <1>;
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memc-arb@1000 {
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...
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};
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memc-ddr@2000 {
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...
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};
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ddr-phy@6000 {
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...
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};
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};
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Should contain subnodes for any of the following relevant hardware resources:
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== DDR PHY control
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Control registers for this memory controller's DDR PHY.
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Required properties:
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- compatible : should contain one of these
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"brcm,brcmstb-ddr-phy-v64.5"
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"brcm,brcmstb-ddr-phy"
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- reg : the DDR PHY register range and length
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Example:
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ddr-phy@6000 {
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compatible = "brcm,brcmstb-ddr-phy-v64.5";
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reg = <0x6000 0xc8>;
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};
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== DDR memory controller sequencer
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Control registers for this memory controller's DDR memory sequencer
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Required properties:
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- compatible : should contain one of these
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"brcm,bcm7425-memc-ddr"
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"brcm,bcm7429-memc-ddr"
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"brcm,bcm7435-memc-ddr" and
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"brcm,brcmstb-memc-ddr"
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- reg : the DDR sequencer register range and length
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Example:
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memc-ddr@2000 {
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compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";
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reg = <0x2000 0x300>;
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};
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== MEMC Arbiter
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The memory controller arbiter is responsible for memory clients allocation
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(bandwidth, priorities etc.) and needs to have its contents restored during
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deep sleep states (S3).
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Required properties:
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- compatible : should contain one of these
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"brcm,brcmstb-memc-arb-v10.0.0.0"
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"brcm,brcmstb-memc-arb"
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- reg : the DDR Arbiter register range and length
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Example:
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memc-arb@1000 {
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compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
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reg = <0x1000 0x248>;
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};
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== Timers
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The Broadcom STB chips contain a timer block with several general purpose
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timers that can be used.
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Required properties:
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- compatible : should contain one of:
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"brcm,bcm7425-timers"
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"brcm,bcm7429-timers"
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"brcm,bcm7435-timers and
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"brcm,brcmstb-timers"
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- reg : the timers register range
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- interrupts : the interrupt line for this timer block
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Example:
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timers: timer@4067c0 {
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compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";
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reg = <0x4067c0 0x40>;
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interrupts = <&periph_intc 19>;
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};