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tools/power turbostat: Add fixed RAPL PSYS divisor for SPR

Intel Sapphire Rapids is an exception and has fixed divisor for RAPL PSYS
counter set to 1.0. Add a platform bit and enable it for SPR.

Reported-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>

authored by Patryk Wlazlyn and committed by Len Brown debe797c 2f60f039

+9 -2
unified split
+9 -2
tools/power/x86/turbostat/turbostat.c
··· 358 unsigned int tj_max; 359 unsigned int tj_max_override; 360 double rapl_power_units, rapl_time_units; 361 - double rapl_dram_energy_units, rapl_energy_units; 362 double rapl_joule_counter_range; 363 unsigned int crystal_hz; 364 unsigned long long tsc_hz; ··· 424 bool has_per_core_rapl; /* Indicates cores energy collection is per-core, not per-package. AMD specific for now */ 425 bool has_rapl_divisor; /* Divisor for Energy unit raw value from MSR_RAPL_POWER_UNIT */ 426 bool has_fixed_rapl_unit; /* Fixed Energy Unit used for DRAM RAPL Domain */ 427 int rapl_quirk_tdp; /* Hardcoded TDP value when cannot be retrieved from hardware */ 428 int tcc_offset_bits; /* TCC Offset bits in MSR_IA32_TEMPERATURE_TARGET */ 429 bool enable_tsc_tweak; /* Use CPU Base freq instead of TSC freq for aperf/mperf counter */ ··· 825 .has_msr_core_c1_res = 1, 826 .has_irtl_msrs = 1, 827 .has_cst_prewake_bit = 1, 828 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 829 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL | RAPL_PSYS, 830 }; ··· 1294 .msr = MSR_PLATFORM_ENERGY_STATUS, 1295 .msr_mask = 0x00000000FFFFFFFF, 1296 .msr_shift = 0, 1297 - .platform_rapl_msr_scale = &rapl_energy_units, 1298 .rci_index = RAPL_RCI_INDEX_ENERGY_PLATFORM, 1299 .bic = BIC_SysWatt | BIC_Sys_J, 1300 .compat_scale = 1.0, ··· 7113 rapl_dram_energy_units = (15.3 / 1000000); 7114 else 7115 rapl_dram_energy_units = rapl_energy_units; 7116 7117 time_unit = msr >> 16 & 0xF; 7118 if (time_unit == 0)
··· 358 unsigned int tj_max; 359 unsigned int tj_max_override; 360 double rapl_power_units, rapl_time_units; 361 + double rapl_dram_energy_units, rapl_energy_units, rapl_psys_energy_units; 362 double rapl_joule_counter_range; 363 unsigned int crystal_hz; 364 unsigned long long tsc_hz; ··· 424 bool has_per_core_rapl; /* Indicates cores energy collection is per-core, not per-package. AMD specific for now */ 425 bool has_rapl_divisor; /* Divisor for Energy unit raw value from MSR_RAPL_POWER_UNIT */ 426 bool has_fixed_rapl_unit; /* Fixed Energy Unit used for DRAM RAPL Domain */ 427 + bool has_fixed_rapl_psys_unit; /* Fixed Energy Unit used for PSYS RAPL Domain */ 428 int rapl_quirk_tdp; /* Hardcoded TDP value when cannot be retrieved from hardware */ 429 int tcc_offset_bits; /* TCC Offset bits in MSR_IA32_TEMPERATURE_TARGET */ 430 bool enable_tsc_tweak; /* Use CPU Base freq instead of TSC freq for aperf/mperf counter */ ··· 824 .has_msr_core_c1_res = 1, 825 .has_irtl_msrs = 1, 826 .has_cst_prewake_bit = 1, 827 + .has_fixed_rapl_psys_unit = 1, 828 .trl_msrs = TRL_BASE | TRL_CORECOUNT, 829 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL | RAPL_PSYS, 830 }; ··· 1292 .msr = MSR_PLATFORM_ENERGY_STATUS, 1293 .msr_mask = 0x00000000FFFFFFFF, 1294 .msr_shift = 0, 1295 + .platform_rapl_msr_scale = &rapl_psys_energy_units, 1296 .rci_index = RAPL_RCI_INDEX_ENERGY_PLATFORM, 1297 .bic = BIC_SysWatt | BIC_Sys_J, 1298 .compat_scale = 1.0, ··· 7111 rapl_dram_energy_units = (15.3 / 1000000); 7112 else 7113 rapl_dram_energy_units = rapl_energy_units; 7114 + 7115 + if (platform->has_fixed_rapl_psys_unit) 7116 + rapl_psys_energy_units = 1.0; 7117 + else 7118 + rapl_psys_energy_units = rapl_energy_units; 7119 7120 time_unit = msr >> 16 & 0xF; 7121 if (time_unit == 0)