Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch 'clk-ux500' into clk-next

* clk-ux500:
clk: ux500: Convert ABx500 clocks to use OF probing
clk: ux500: Add device tree bindings for ABx500 clocks
clk: ux500: move AB8500 sysclk over to PRCMU clk driver

+60 -18
+20
Documentation/devicetree/bindings/clock/stericsson,abx500.txt
··· 1 + Clock bindings for ST-Ericsson ABx500 clocks 2 + 3 + Required properties : 4 + - compatible : shall contain the following: 5 + "stericsson,ab8500-clk" 6 + - #clock-cells should be <1> 7 + 8 + The ABx500 clocks need to be placed as a subnode of an AB8500 9 + device node, see mfd/ab8500.txt 10 + 11 + All available clocks are defined as preprocessor macros in 12 + dt-bindings/clock/ste-ab8500.h header and can be used in device 13 + tree sources. 14 + 15 + Example: 16 + 17 + clock-controller { 18 + compatible = "stericsson,ab8500-clk"; 19 + #clock-cells = <1>; 20 + };
+26 -18
drivers/clk/ux500/abx500-clk.c
··· 10 10 #include <linux/err.h> 11 11 #include <linux/module.h> 12 12 #include <linux/device.h> 13 + #include <linux/of.h> 13 14 #include <linux/platform_device.h> 14 15 #include <linux/mfd/abx500/ab8500.h> 15 16 #include <linux/mfd/abx500/ab8500-sysctrl.h> 16 17 #include <linux/clkdev.h> 17 18 #include <linux/clk-provider.h> 18 - #include <linux/mfd/dbx500-prcmu.h> 19 + #include <dt-bindings/clock/ste-ab8500.h> 19 20 #include "clk.h" 21 + 22 + #define AB8500_NUM_CLKS 6 23 + 24 + static struct clk *ab8500_clks[AB8500_NUM_CLKS]; 25 + static struct clk_onecell_data ab8500_clk_data; 20 26 21 27 /* Clock definitions for ab8500 */ 22 28 static int ab8500_reg_clks(struct device *dev) 23 29 { 24 30 int ret; 25 31 struct clk *clk; 26 - 32 + struct device_node *np = dev->of_node; 27 33 const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"}; 28 34 u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1}; 29 35 u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK}; ··· 38 32 (1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT) 39 33 }; 40 34 41 - dev_info(dev, "register clocks for ab850x\n"); 42 - 43 35 /* Enable SWAT */ 44 36 ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE); 45 37 if (ret) 46 38 return ret; 47 39 48 - /* ab8500_sysclk */ 49 - clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0); 50 - clk_register_clkdev(clk, "sysclk", "ab8500-usb.0"); 51 - clk_register_clkdev(clk, "sysclk", "ab-iddet.0"); 52 - clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0"); 53 - clk_register_clkdev(clk, "sysclk", "shrm_bus"); 54 - 55 40 /* ab8500_sysclk2 */ 56 41 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk", 57 42 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 58 43 AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0); 59 - clk_register_clkdev(clk, "sysclk", "0-0070"); 44 + ab8500_clks[AB8500_SYSCLK_BUF2] = clk; 60 45 61 46 /* ab8500_sysclk3 */ 62 47 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk", 63 48 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 64 49 AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0); 65 - clk_register_clkdev(clk, "sysclk", "cg1960_core.0"); 50 + ab8500_clks[AB8500_SYSCLK_BUF3] = clk; 66 51 67 52 /* ab8500_sysclk4 */ 68 53 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk", 69 54 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 70 55 AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0); 56 + ab8500_clks[AB8500_SYSCLK_BUF4] = clk; 71 57 72 58 /* ab_ulpclk */ 73 59 clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL, 74 60 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ, 75 61 AB8500_SYSULPCLKCTRL1_ULPCLKREQ, 76 62 38400000, 9000, 0); 77 - clk_register_clkdev(clk, "ulpclk", "snd-soc-mop500.0"); 63 + ab8500_clks[AB8500_SYSCLK_ULP] = clk; 78 64 79 65 /* ab8500_intclk */ 80 66 clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2, 81 67 intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0); 82 - clk_register_clkdev(clk, "intclk", "snd-soc-mop500.0"); 83 - clk_register_clkdev(clk, NULL, "ab8500-pwm.1"); 68 + ab8500_clks[AB8500_SYSCLK_INT] = clk; 84 69 85 70 /* ab8500_audioclk */ 86 71 clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk", 87 72 AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 88 73 AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0); 89 - clk_register_clkdev(clk, "audioclk", "ab8500-codec.0"); 74 + ab8500_clks[AB8500_SYSCLK_AUDIO] = clk; 75 + 76 + ab8500_clk_data.clks = ab8500_clks; 77 + ab8500_clk_data.clk_num = ARRAY_SIZE(ab8500_clks); 78 + of_clk_add_provider(np, of_clk_src_onecell_get, &ab8500_clk_data); 79 + 80 + dev_info(dev, "registered clocks for ab850x\n"); 90 81 91 82 return 0; 92 83 } ··· 119 116 return ret; 120 117 } 121 118 119 + static const struct of_device_id abx500_clk_match[] = { 120 + { .compatible = "stericsson,ab8500-clk", }, 121 + {} 122 + }; 123 + 122 124 static struct platform_driver abx500_clk_driver = { 123 125 .driver = { 124 126 .name = "abx500-clk", 127 + .of_match_table = abx500_clk_match, 125 128 }, 126 129 .probe = abx500_clk_probe, 127 130 }; ··· 136 127 { 137 128 return platform_driver_register(&abx500_clk_driver); 138 129 } 139 - 140 130 arch_initcall(abx500_clk_init); 141 131 142 132 MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org");
+3
drivers/clk/ux500/u8500_of_clk.c
··· 206 206 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0); 207 207 prcmu_clk[PRCMU_TIMCLK] = clk; 208 208 209 + clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0); 210 + prcmu_clk[PRCMU_SYSCLK] = clk; 211 + 209 212 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, 210 213 100000000, CLK_SET_RATE_GATE); 211 214 prcmu_clk[PRCMU_SDMMCCLK] = clk;
+11
include/dt-bindings/clock/ste-ab8500.h
··· 1 + #ifndef __STE_CLK_AB8500_H__ 2 + #define __STE_CLK_AB8500_H__ 3 + 4 + #define AB8500_SYSCLK_BUF2 0 5 + #define AB8500_SYSCLK_BUF3 1 6 + #define AB8500_SYSCLK_BUF4 2 7 + #define AB8500_SYSCLK_ULP 3 8 + #define AB8500_SYSCLK_INT 4 9 + #define AB8500_SYSCLK_AUDIO 5 10 + 11 + #endif