tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/radeon: add new firmware header definitions (v3)
These are needed to properly handle more frequently
updated firmware.
v2: add new firmware helper functions as well.
v3: update to latest format
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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drivers/gpu/drm/radeon/Makefile
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drivers/gpu/drm/radeon/Makefile
···
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r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
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rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
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trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \
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ci_dpm.o dce6_afmt.o radeon_vm.o
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ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o
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# add async DMA block
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radeon-y += \
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drivers/gpu/drm/radeon/radeon_ucode.c
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drivers/gpu/drm/radeon/radeon_ucode.c
···
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_ucode.h"
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static void radeon_ucode_print_common_hdr(const struct common_firmware_header *hdr)
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{
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DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
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DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
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DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
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DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
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DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
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DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
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DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
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DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
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DRM_DEBUG("ucode_array_offset_bytes: %u\n",
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le32_to_cpu(hdr->ucode_array_offset_bytes));
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DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
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}
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void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("MC\n");
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radeon_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct mc_firmware_header_v1_0 *mc_hdr =
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container_of(hdr, struct mc_firmware_header_v1_0, header);
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DRM_DEBUG("io_debug_size_bytes: %u\n",
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le32_to_cpu(mc_hdr->io_debug_size_bytes));
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DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
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le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
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} else {
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DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
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}
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}
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void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("SMC\n");
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radeon_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct smc_firmware_header_v1_0 *smc_hdr =
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container_of(hdr, struct smc_firmware_header_v1_0, header);
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DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
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} else {
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DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
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}
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}
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void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("GFX\n");
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radeon_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct gfx_firmware_header_v1_0 *gfx_hdr =
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container_of(hdr, struct gfx_firmware_header_v1_0, header);
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DRM_DEBUG("ucode_feature_version: %u\n",
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le32_to_cpu(gfx_hdr->ucode_feature_version));
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DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
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DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
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} else {
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DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
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}
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}
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void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("RLC\n");
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radeon_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct rlc_firmware_header_v1_0 *rlc_hdr =
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container_of(hdr, struct rlc_firmware_header_v1_0, header);
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DRM_DEBUG("ucode_feature_version: %u\n",
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le32_to_cpu(rlc_hdr->ucode_feature_version));
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DRM_DEBUG("save_and_restore_offset: %u\n",
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le32_to_cpu(rlc_hdr->save_and_restore_offset));
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DRM_DEBUG("clear_state_descriptor_offset: %u\n",
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le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
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DRM_DEBUG("avail_scratch_ram_locations: %u\n",
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le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
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DRM_DEBUG("master_pkt_description_offset: %u\n",
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le32_to_cpu(rlc_hdr->master_pkt_description_offset));
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} else {
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DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
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}
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}
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void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
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{
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uint16_t version_major = le16_to_cpu(hdr->header_version_major);
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uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
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DRM_DEBUG("SDMA\n");
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radeon_ucode_print_common_hdr(hdr);
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if (version_major == 1) {
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const struct sdma_firmware_header_v1_0 *sdma_hdr =
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container_of(hdr, struct sdma_firmware_header_v1_0, header);
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DRM_DEBUG("ucode_feature_version: %u\n",
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le32_to_cpu(sdma_hdr->ucode_feature_version));
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DRM_DEBUG("ucode_change_version: %u\n",
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le32_to_cpu(sdma_hdr->ucode_change_version));
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DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
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DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
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} else {
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DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
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version_major, version_minor);
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}
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}
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int radeon_ucode_validate(const struct firmware *fw)
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{
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const struct common_firmware_header *hdr =
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(const struct common_firmware_header *)fw->data;
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if (fw->size == le32_to_cpu(hdr->size_bytes))
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return 0;
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return -EINVAL;
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}
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+71
drivers/gpu/drm/radeon/radeon_ucode.h
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drivers/gpu/drm/radeon/radeon_ucode.h
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#define HAWAII_SMC_UCODE_START 0x20000
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#define HAWAII_SMC_UCODE_SIZE 0x1FDEC
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struct common_firmware_header {
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uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
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uint32_t header_size_bytes; /* size of just the header in bytes */
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uint16_t header_version_major; /* header version */
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uint16_t header_version_minor; /* header version */
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uint16_t ip_version_major; /* IP version */
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uint16_t ip_version_minor; /* IP version */
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uint32_t ucode_version;
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uint32_t ucode_size_bytes; /* size of ucode in bytes */
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uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
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uint32_t crc32; /* crc32 checksum of the payload */
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};
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/* version_major=1, version_minor=0 */
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struct mc_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t io_debug_size_bytes; /* size of debug array in dwords */
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uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
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};
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/* version_major=1, version_minor=0 */
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struct smc_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_start_addr;
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};
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/* version_major=1, version_minor=0 */
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struct gfx_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t jt_offset; /* jt location */
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uint32_t jt_size; /* size of jt */
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};
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/* version_major=1, version_minor=0 */
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struct rlc_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t save_and_restore_offset;
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uint32_t clear_state_descriptor_offset;
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uint32_t avail_scratch_ram_locations;
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uint32_t master_pkt_description_offset;
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};
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/* version_major=1, version_minor=0 */
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struct sdma_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t ucode_change_version;
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uint32_t jt_offset; /* jt location */
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uint32_t jt_size; /* size of jt */
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};
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/* header is fixed size */
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union radeon_firmware_header {
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struct common_firmware_header common;
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struct mc_firmware_header_v1_0 mc;
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struct smc_firmware_header_v1_0 smc;
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struct gfx_firmware_header_v1_0 gfx;
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struct rlc_firmware_header_v1_0 rlc;
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struct sdma_firmware_header_v1_0 sdma;
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uint8_t raw[0x100];
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};
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void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
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void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
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void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
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void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
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void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
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int radeon_ucode_validate(const struct firmware *fw);
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#endif