Merge tag 'ib-mfd-gpio-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into devel

+1 -1

Documentation/devicetree/bindings/mfd/stmpe.txt

··· 4 4 keypad, touchscreen, adc, pwm, rotator. 5 5 6 6 Required properties: 7 - - compatible : "st,stmpe[610|801|811|1601|2401|2403]" 7 + - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]" 8 8 - reg : I2C/SPI address of the device 9 9 10 10 Optional properties:

+120 -47

drivers/gpio/gpio-stmpe.c

··· 20 20 */ 21 21 enum { REG_RE, REG_FE, REG_IE }; 22 22 23 + enum { LSB, CSB, MSB }; 24 + 23 25 #define CACHE_NR_REGS 3 24 26 /* No variant has more than 24 GPIOs */ 25 27 #define CACHE_NR_BANKS (24 / 8) ··· 41 39 { 42 40 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 43 41 struct stmpe *stmpe = stmpe_gpio->stmpe; 44 - u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); 42 + u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; 45 43 u8 mask = 1 << (offset % 8); 46 44 int ret; 47 45 ··· 57 55 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 58 56 struct stmpe *stmpe = stmpe_gpio->stmpe; 59 57 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; 60 - u8 reg = stmpe->regs[which] - (offset / 8); 58 + u8 reg = stmpe->regs[which + (offset / 8)]; 61 59 u8 mask = 1 << (offset % 8); 62 60 63 61 /* ··· 91 89 { 92 90 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 93 91 struct stmpe *stmpe = stmpe_gpio->stmpe; 94 - u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 92 + u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; 95 93 u8 mask = 1 << (offset % 8); 96 94 97 95 stmpe_gpio_set(chip, offset, val); ··· 104 102 { 105 103 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 106 104 struct stmpe *stmpe = stmpe_gpio->stmpe; 107 - u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 105 + u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; 108 106 u8 mask = 1 << (offset % 8); 109 107 110 108 return stmpe_set_bits(stmpe, reg, mask, 0); ··· 144 142 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) 145 143 return -EINVAL; 146 144 147 - /* STMPE801 doesn't have RE and FE registers */ 148 - if (stmpe_gpio->stmpe->partnum == STMPE801) 145 + /* STMPE801 and STMPE 1600 don't have RE and FE registers */ 146 + if (stmpe_gpio->stmpe->partnum == STMPE801 || 147 + stmpe_gpio->stmpe->partnum == STMPE1600) 149 148 return 0; 150 149 151 150 if (type & IRQ_TYPE_EDGE_RISING) ··· 176 173 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 177 174 struct stmpe *stmpe = stmpe_gpio->stmpe; 178 175 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 179 - static const u8 regmap[] = { 180 - [REG_RE] = STMPE_IDX_GPRER_LSB, 181 - [REG_FE] = STMPE_IDX_GPFER_LSB, 182 - [REG_IE] = STMPE_IDX_IEGPIOR_LSB, 176 + static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = { 177 + [REG_RE][LSB] = STMPE_IDX_GPRER_LSB, 178 + [REG_RE][CSB] = STMPE_IDX_GPRER_CSB, 179 + [REG_RE][MSB] = STMPE_IDX_GPRER_MSB, 180 + [REG_FE][LSB] = STMPE_IDX_GPFER_LSB, 181 + [REG_FE][CSB] = STMPE_IDX_GPFER_CSB, 182 + [REG_FE][MSB] = STMPE_IDX_GPFER_MSB, 183 + [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB, 184 + [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB, 185 + [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB, 183 186 }; 184 187 int i, j; 185 188 186 189 for (i = 0; i < CACHE_NR_REGS; i++) { 187 - /* STMPE801 doesn't have RE and FE registers */ 188 - if ((stmpe->partnum == STMPE801) && 189 - (i != REG_IE)) 190 + /* STMPE801 and STMPE1600 don't have RE and FE registers */ 191 + if ((stmpe->partnum == STMPE801 || 192 + stmpe->partnum == STMPE1600) && 193 + (i != REG_IE)) 190 194 continue; 191 195 192 196 for (j = 0; j < num_banks; j++) { ··· 204 194 continue; 205 195 206 196 stmpe_gpio->oldregs[i][j] = new; 207 - stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); 197 + stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new); 208 198 } 209 199 } 210 200 ··· 226 216 { 227 217 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 228 218 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 219 + struct stmpe *stmpe = stmpe_gpio->stmpe; 229 220 int offset = d->hwirq; 230 221 int regoffset = offset / 8; 231 222 int mask = 1 << (offset % 8); 232 223 233 224 stmpe_gpio->regs[REG_IE][regoffset] |= mask; 225 + 226 + /* 227 + * STMPE1600 workaround: to be able to get IRQ from pins, 228 + * a read must be done on GPMR register, or a write in 229 + * GPSR or GPCR registers 230 + */ 231 + if (stmpe->partnum == STMPE1600) 232 + stmpe_reg_read(stmpe, 233 + stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]); 234 234 } 235 235 236 236 static void stmpe_dbg_show_one(struct seq_file *s, ··· 250 230 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 251 231 struct stmpe *stmpe = stmpe_gpio->stmpe; 252 232 const char *label = gpiochip_is_requested(gc, offset); 253 - int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 254 233 bool val = !!stmpe_gpio_get(gc, offset); 255 - u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 234 + u8 bank = offset / 8; 235 + u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank]; 256 236 u8 mask = 1 << (offset % 8); 257 237 int ret; 258 238 u8 dir; ··· 267 247 gpio, label ?: "(none)", 268 248 val ? "hi" : "lo"); 269 249 } else { 270 - u8 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_MSB] + num_banks - 1 - (offset / 8); 271 - u8 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB] - (offset / 8); 272 - u8 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB] - (offset / 8); 273 - u8 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB] - (offset / 8); 274 - bool edge_det; 275 - bool rise; 276 - bool fall; 250 + u8 edge_det_reg; 251 + u8 rise_reg; 252 + u8 fall_reg; 253 + u8 irqen_reg; 254 + 255 + char *edge_det_values[] = {"edge-inactive", 256 + "edge-asserted", 257 + "not-supported"}; 258 + char *rise_values[] = {"no-rising-edge-detection", 259 + "rising-edge-detection", 260 + "not-supported"}; 261 + char *fall_values[] = {"no-falling-edge-detection", 262 + "falling-edge-detection", 263 + "not-supported"}; 264 + #define NOT_SUPPORTED_IDX 2 265 + u8 edge_det = NOT_SUPPORTED_IDX; 266 + u8 rise = NOT_SUPPORTED_IDX; 267 + u8 fall = NOT_SUPPORTED_IDX; 277 268 bool irqen; 278 269 279 - ret = stmpe_reg_read(stmpe, edge_det_reg); 280 - if (ret < 0) 270 + switch (stmpe->partnum) { 271 + case STMPE610: 272 + case STMPE811: 273 + case STMPE1601: 274 + case STMPE2401: 275 + case STMPE2403: 276 + edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank]; 277 + ret = stmpe_reg_read(stmpe, edge_det_reg); 278 + if (ret < 0) 279 + return; 280 + edge_det = !!(ret & mask); 281 + 282 + case STMPE1801: 283 + rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank]; 284 + fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank]; 285 + 286 + ret = stmpe_reg_read(stmpe, rise_reg); 287 + if (ret < 0) 288 + return; 289 + rise = !!(ret & mask); 290 + ret = stmpe_reg_read(stmpe, fall_reg); 291 + if (ret < 0) 292 + return; 293 + fall = !!(ret & mask); 294 + 295 + case STMPE801: 296 + case STMPE1600: 297 + irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank]; 298 + break; 299 + 300 + default: 281 301 return; 282 - edge_det = !!(ret & mask); 283 - ret = stmpe_reg_read(stmpe, rise_reg); 284 - if (ret < 0) 285 - return; 286 - rise = !!(ret & mask); 287 - ret = stmpe_reg_read(stmpe, fall_reg); 288 - if (ret < 0) 289 - return; 290 - fall = !!(ret & mask); 302 + } 303 + 291 304 ret = stmpe_reg_read(stmpe, irqen_reg); 292 305 if (ret < 0) 293 306 return; 294 307 irqen = !!(ret & mask); 295 308 296 - seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s %s%s%s", 309 + seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", 297 310 gpio, label ?: "(none)", 298 311 val ? "hi" : "lo", 299 - edge_det ? "edge-asserted" : "edge-inactive", 300 - irqen ? "IRQ-enabled" : "", 301 - rise ? " rising-edge-detection" : "", 302 - fall ? " falling-edge-detection" : ""); 312 + edge_det_values[edge_det], 313 + irqen ? "IRQ-enabled" : "IRQ-disabled", 314 + rise_values[rise], 315 + fall_values[fall]); 303 316 } 304 317 } 305 318 ··· 360 307 { 361 308 struct stmpe_gpio *stmpe_gpio = dev; 362 309 struct stmpe *stmpe = stmpe_gpio->stmpe; 363 - u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; 310 + u8 statmsbreg; 364 311 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 365 312 u8 status[num_banks]; 366 313 int ret; 367 314 int i; 315 + 316 + /* 317 + * the stmpe_block_read() call below, imposes to set statmsbreg 318 + * with the register located at the lowest address. As STMPE1600 319 + * variant is the only one which respect registers address's order 320 + * (LSB regs located at lowest address than MSB ones) whereas all 321 + * the others have a registers layout with MSB located before the 322 + * LSB regs. 323 + */ 324 + if (stmpe->partnum == STMPE1600) 325 + statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB]; 326 + else 327 + statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; 368 328 369 329 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); 370 330 if (ret < 0) 371 331 return IRQ_NONE; 372 332 373 333 for (i = 0; i < num_banks; i++) { 374 - int bank = num_banks - i - 1; 334 + int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i : 335 + num_banks - i - 1; 375 336 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; 376 337 unsigned int stat = status[i]; 377 338 ··· 403 336 stat &= ~(1 << bit); 404 337 } 405 338 406 - stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 407 - 408 - /* Edge detect register is not present on 801 */ 409 - if (stmpe->partnum != STMPE801) 410 - stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] 411 - + i, status[i]); 339 + /* 340 + * interrupt status register write has no effect on 341 + * 801/1801/1600, bits are cleared when read. 342 + * Edge detect register is not present on 801/1600/1801 343 + */ 344 + if (stmpe->partnum != STMPE801 || stmpe->partnum != STMPE1600 || 345 + stmpe->partnum != STMPE1801) { 346 + stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 347 + stmpe_reg_write(stmpe, 348 + stmpe->regs[STMPE_IDX_GPEDR_LSB + i], 349 + status[i]); 350 + } 412 351 } 413 352 414 353 return IRQ_HANDLED;

+2

drivers/mfd/stmpe-i2c.c

··· 57 57 { .compatible = "st,stmpe610", .data = (void *)STMPE610, }, 58 58 { .compatible = "st,stmpe801", .data = (void *)STMPE801, }, 59 59 { .compatible = "st,stmpe811", .data = (void *)STMPE811, }, 60 + { .compatible = "st,stmpe1600", .data = (void *)STMPE1600, }, 60 61 { .compatible = "st,stmpe1601", .data = (void *)STMPE1601, }, 61 62 { .compatible = "st,stmpe1801", .data = (void *)STMPE1801, }, 62 63 { .compatible = "st,stmpe2401", .data = (void *)STMPE2401, }, ··· 102 101 { "stmpe610", STMPE610 }, 103 102 { "stmpe801", STMPE801 }, 104 103 { "stmpe811", STMPE811 }, 104 + { "stmpe1600", STMPE1600 }, 105 105 { "stmpe1601", STMPE1601 }, 106 106 { "stmpe1801", STMPE1801 }, 107 107 { "stmpe2401", STMPE2401 },

+135 -26

drivers/mfd/stmpe.c

··· 469 469 470 470 static const u8 stmpe811_regs[] = { 471 471 [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID, 472 + [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL, 473 + [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2, 472 474 [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL, 473 475 [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN, 474 476 [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA, ··· 483 481 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF, 484 482 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN, 485 483 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA, 486 - [STMPE_IDX_GPEDR_MSB] = STMPE811_REG_GPIO_ED, 484 + [STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED, 487 485 }; 488 486 489 487 static struct stmpe_variant_block stmpe811_blocks[] = { ··· 513 511 if (blocks & STMPE_BLOCK_TOUCHSCREEN) 514 512 mask |= STMPE811_SYS_CTRL2_TSC_OFF; 515 513 516 - return __stmpe_set_bits(stmpe, STMPE811_REG_SYS_CTRL2, mask, 514 + return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask, 517 515 enable ? 0 : mask); 518 516 } 519 517 ··· 553 551 }; 554 552 555 553 /* 554 + * STMPE1600 555 + * Compared to all others STMPE variant, LSB and MSB regs are located in this 556 + * order : LSB addr 557 + * MSB addr + 1 558 + * As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers 559 + */ 560 + 561 + static const u8 stmpe1600_regs[] = { 562 + [STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID, 563 + [STMPE_IDX_SYS_CTRL] = STMPE1600_REG_SYS_CTRL, 564 + [STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL, 565 + [STMPE_IDX_GPMR_LSB] = STMPE1600_REG_GPMR_LSB, 566 + [STMPE_IDX_GPMR_CSB] = STMPE1600_REG_GPMR_MSB, 567 + [STMPE_IDX_GPSR_LSB] = STMPE1600_REG_GPSR_LSB, 568 + [STMPE_IDX_GPSR_CSB] = STMPE1600_REG_GPSR_MSB, 569 + [STMPE_IDX_GPDR_LSB] = STMPE1600_REG_GPDR_LSB, 570 + [STMPE_IDX_GPDR_CSB] = STMPE1600_REG_GPDR_MSB, 571 + [STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB, 572 + [STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB, 573 + [STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB, 574 + }; 575 + 576 + static struct stmpe_variant_block stmpe1600_blocks[] = { 577 + { 578 + .cell = &stmpe_gpio_cell, 579 + .irq = 0, 580 + .block = STMPE_BLOCK_GPIO, 581 + }, 582 + }; 583 + 584 + static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks, 585 + bool enable) 586 + { 587 + if (blocks & STMPE_BLOCK_GPIO) 588 + return 0; 589 + else 590 + return -EINVAL; 591 + } 592 + 593 + static struct stmpe_variant_info stmpe1600 = { 594 + .name = "stmpe1600", 595 + .id_val = STMPE1600_ID, 596 + .id_mask = 0xffff, 597 + .num_gpios = 16, 598 + .af_bits = 0, 599 + .regs = stmpe1600_regs, 600 + .blocks = stmpe1600_blocks, 601 + .num_blocks = ARRAY_SIZE(stmpe1600_blocks), 602 + .num_irqs = STMPE1600_NR_INTERNAL_IRQS, 603 + .enable = stmpe1600_enable, 604 + }; 605 + 606 + /* 556 607 * STMPE1601 557 608 */ 558 609 559 610 static const u8 stmpe1601_regs[] = { 560 611 [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID, 612 + [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL, 613 + [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2, 561 614 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB, 615 + [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB, 562 616 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB, 563 617 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB, 564 618 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB, 619 + [STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB, 565 620 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB, 621 + [STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB, 566 622 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB, 623 + [STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB, 567 624 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB, 625 + [STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB, 626 + [STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB, 627 + [STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB, 568 628 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB, 629 + [STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB, 569 630 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB, 631 + [STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB, 570 632 [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB, 571 633 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB, 572 634 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB, 635 + [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB, 573 636 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB, 574 - [STMPE_IDX_GPEDR_MSB] = STMPE1601_REG_GPIO_ED_MSB, 575 637 }; 576 638 577 639 static struct stmpe_variant_block stmpe1601_blocks[] = { ··· 706 640 return timeout; 707 641 } 708 642 709 - ret = __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2, 643 + ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 710 644 STMPE1601_AUTOSLEEP_TIMEOUT_MASK, 711 645 timeout); 712 646 if (ret < 0) 713 647 return ret; 714 648 715 - return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2, 649 + return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 716 650 STPME1601_AUTOSLEEP_ENABLE, 717 651 STPME1601_AUTOSLEEP_ENABLE); 718 652 } ··· 737 671 else 738 672 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM; 739 673 740 - return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL, mask, 674 + return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 741 675 enable ? mask : 0); 742 676 } 743 677 ··· 776 710 */ 777 711 static const u8 stmpe1801_regs[] = { 778 712 [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID, 713 + [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL, 779 714 [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW, 780 715 [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW, 781 716 [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW, 782 717 [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW, 718 + [STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID, 719 + [STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH, 783 720 [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW, 721 + [STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID, 722 + [STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH, 784 723 [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW, 724 + [STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID, 725 + [STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH, 785 726 [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW, 727 + [STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID, 728 + [STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH, 786 729 [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW, 730 + [STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID, 731 + [STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH, 787 732 [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW, 733 + [STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID, 734 + [STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH, 788 735 [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW, 789 736 [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW, 790 - [STMPE_IDX_ISGPIOR_LSB] = STMPE1801_REG_INT_STA_GPIO_LOW, 737 + [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID, 738 + [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH, 739 + [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH, 791 740 }; 792 741 793 742 static struct stmpe_variant_block stmpe1801_blocks[] = { ··· 832 751 enable ? mask : 0); 833 752 } 834 753 835 - static int stmpe1801_reset(struct stmpe *stmpe) 754 + static int stmpe_reset(struct stmpe *stmpe) 836 755 { 756 + u16 id_val = stmpe->variant->id_val; 837 757 unsigned long timeout; 838 758 int ret = 0; 759 + u8 reset_bit; 839 760 840 - ret = __stmpe_set_bits(stmpe, STMPE1801_REG_SYS_CTRL, 841 - STMPE1801_MSK_SYS_CTRL_RESET, STMPE1801_MSK_SYS_CTRL_RESET); 761 + if (id_val == STMPE811_ID) 762 + /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */ 763 + reset_bit = STMPE811_SYS_CTRL_RESET; 764 + else 765 + /* all other STMPE variant use bit 7 of SYS_CTRL register */ 766 + reset_bit = STMPE_SYS_CTRL_RESET; 767 + 768 + ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], 769 + reset_bit, reset_bit); 842 770 if (ret < 0) 843 771 return ret; 844 772 845 773 timeout = jiffies + msecs_to_jiffies(100); 846 774 while (time_before(jiffies, timeout)) { 847 - ret = __stmpe_reg_read(stmpe, STMPE1801_REG_SYS_CTRL); 775 + ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]); 848 776 if (ret < 0) 849 777 return ret; 850 - if (!(ret & STMPE1801_MSK_SYS_CTRL_RESET)) 778 + if (!(ret & reset_bit)) 851 779 return 0; 852 780 usleep_range(100, 200); 853 781 } ··· 884 794 885 795 static const u8 stmpe24xx_regs[] = { 886 796 [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID, 797 + [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL, 798 + [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2, 887 799 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB, 800 + [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB, 888 801 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB, 889 802 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB, 890 803 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB, 804 + [STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB, 805 + [STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB, 891 806 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB, 807 + [STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB, 808 + [STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB, 892 809 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB, 810 + [STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB, 811 + [STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB, 893 812 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB, 813 + [STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB, 814 + [STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB, 894 815 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB, 816 + [STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB, 817 + [STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB, 895 818 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB, 819 + [STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB, 820 + [STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB, 896 821 [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB, 897 822 [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB, 898 823 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB, 899 824 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB, 825 + [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB, 826 + [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB, 900 827 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB, 828 + [STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB, 829 + [STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB, 901 830 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB, 902 831 }; 903 832 ··· 949 840 if (blocks & STMPE_BLOCK_KEYPAD) 950 841 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC; 951 842 952 - return __stmpe_set_bits(stmpe, STMPE24XX_REG_SYS_CTRL, mask, 843 + return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 953 844 enable ? mask : 0); 954 845 } 955 846 ··· 1002 893 [STMPE610] = &stmpe610, 1003 894 [STMPE801] = &stmpe801, 1004 895 [STMPE811] = &stmpe811, 896 + [STMPE1600] = &stmpe1600, 1005 897 [STMPE1601] = &stmpe1601, 1006 898 [STMPE1801] = &stmpe1801, 1007 899 [STMPE2401] = &stmpe2401, ··· 1029 919 int ret; 1030 920 int i; 1031 921 1032 - if (variant->id_val == STMPE801_ID) { 922 + if (variant->id_val == STMPE801_ID || 923 + variant->id_val == STMPE1600_ID) { 1033 924 int base = irq_create_mapping(stmpe->domain, 0); 1034 925 1035 926 handle_nested_irq(base); ··· 1093 982 continue; 1094 983 1095 984 stmpe->oldier[i] = new; 1096 - stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB] - i, new); 985 + stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new); 1097 986 } 1098 987 1099 988 mutex_unlock(&stmpe->irq_lock); ··· 1199 1088 if (ret) 1200 1089 return ret; 1201 1090 1202 - if (id == STMPE1801_ID) { 1203 - ret = stmpe1801_reset(stmpe); 1204 - if (ret < 0) 1205 - return ret; 1206 - } 1091 + ret = stmpe_reset(stmpe); 1092 + if (ret < 0) 1093 + return ret; 1207 1094 1208 1095 if (stmpe->irq >= 0) { 1209 - if (id == STMPE801_ID) 1210 - icr = STMPE801_REG_SYS_CTRL_INT_EN; 1096 + if (id == STMPE801_ID || id == STMPE1600_ID) 1097 + icr = STMPE_SYS_CTRL_INT_EN; 1211 1098 else 1212 1099 icr = STMPE_ICR_LSB_GIM; 1213 1100 1214 - /* STMPE801 doesn't support Edge interrupts */ 1215 - if (id != STMPE801_ID) { 1101 + /* STMPE801 and STMPE1600 don't support Edge interrupts */ 1102 + if (id != STMPE801_ID && id != STMPE1600_ID) { 1216 1103 if (irq_trigger == IRQF_TRIGGER_FALLING || 1217 1104 irq_trigger == IRQF_TRIGGER_RISING) 1218 1105 icr |= STMPE_ICR_LSB_EDGE; ··· 1218 1109 1219 1110 if (irq_trigger == IRQF_TRIGGER_RISING || 1220 1111 irq_trigger == IRQF_TRIGGER_HIGH) { 1221 - if (id == STMPE801_ID) 1222 - icr |= STMPE801_REG_SYS_CTRL_INT_HI; 1112 + if (id == STMPE801_ID || id == STMPE1600_ID) 1113 + icr |= STMPE_SYS_CTRL_INT_HI; 1223 1114 else 1224 1115 icr |= STMPE_ICR_LSB_HIGH; 1225 1116 }

+73 -12

drivers/mfd/stmpe.h

··· 104 104 #define STMPE_ICR_LSB_EDGE (1 << 1) 105 105 #define STMPE_ICR_LSB_GIM (1 << 0) 106 106 107 + #define STMPE_SYS_CTRL_RESET (1 << 7) 108 + #define STMPE_SYS_CTRL_INT_EN (1 << 2) 109 + #define STMPE_SYS_CTRL_INT_HI (1 << 0) 110 + 107 111 /* 108 112 * STMPE801 109 113 */ ··· 123 119 #define STMPE801_REG_GPIO_SET_PIN 0x11 124 120 #define STMPE801_REG_GPIO_DIR 0x12 125 121 126 - #define STMPE801_REG_SYS_CTRL_RESET (1 << 7) 127 - #define STMPE801_REG_SYS_CTRL_INT_EN (1 << 2) 128 - #define STMPE801_REG_SYS_CTRL_INT_HI (1 << 0) 129 - 130 122 /* 131 123 * STMPE811 132 124 */ 125 + #define STMPE811_ID 0x0811 133 126 134 127 #define STMPE811_IRQ_TOUCH_DET 0 135 128 #define STMPE811_IRQ_FIFO_TH 1 ··· 139 138 #define STMPE811_NR_INTERNAL_IRQS 8 140 139 141 140 #define STMPE811_REG_CHIP_ID 0x00 141 + #define STMPE811_REG_SYS_CTRL 0x03 142 142 #define STMPE811_REG_SYS_CTRL2 0x04 143 143 #define STMPE811_REG_SPI_CFG 0x08 144 144 #define STMPE811_REG_INT_CTRL 0x09 ··· 156 154 #define STMPE811_REG_GPIO_FE 0x16 157 155 #define STMPE811_REG_GPIO_AF 0x17 158 156 157 + #define STMPE811_SYS_CTRL_RESET (1 << 1) 158 + 159 159 #define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0) 160 160 #define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1) 161 161 #define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2) 162 162 #define STMPE811_SYS_CTRL2_TS_OFF (1 << 3) 163 + 164 + /* 165 + * STMPE1600 166 + */ 167 + #define STMPE1600_ID 0x0016 168 + #define STMPE1600_NR_INTERNAL_IRQS 16 169 + 170 + #define STMPE1600_REG_CHIP_ID 0x00 171 + #define STMPE1600_REG_SYS_CTRL 0x03 172 + #define STMPE1600_REG_IEGPIOR_LSB 0x08 173 + #define STMPE1600_REG_IEGPIOR_MSB 0x09 174 + #define STMPE1600_REG_ISGPIOR_LSB 0x0A 175 + #define STMPE1600_REG_ISGPIOR_MSB 0x0B 176 + #define STMPE1600_REG_GPMR_LSB 0x10 177 + #define STMPE1600_REG_GPMR_MSB 0x11 178 + #define STMPE1600_REG_GPSR_LSB 0x12 179 + #define STMPE1600_REG_GPSR_MSB 0x13 180 + #define STMPE1600_REG_GPDR_LSB 0x14 181 + #define STMPE1600_REG_GPDR_MSB 0x15 182 + #define STMPE1600_REG_GPPIR_LSB 0x16 183 + #define STMPE1600_REG_GPPIR_MSB 0x17 163 184 164 185 /* 165 186 * STMPE1601 ··· 200 175 201 176 #define STMPE1601_REG_SYS_CTRL 0x02 202 177 #define STMPE1601_REG_SYS_CTRL2 0x03 178 + #define STMPE1601_REG_ICR_MSB 0x10 203 179 #define STMPE1601_REG_ICR_LSB 0x11 180 + #define STMPE1601_REG_IER_MSB 0x12 204 181 #define STMPE1601_REG_IER_LSB 0x13 205 182 #define STMPE1601_REG_ISR_MSB 0x14 206 - #define STMPE1601_REG_CHIP_ID 0x80 183 + #define STMPE1601_REG_ISR_LSB 0x15 184 + #define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16 207 185 #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17 208 186 #define STMPE1601_REG_INT_STA_GPIO_MSB 0x18 209 - #define STMPE1601_REG_GPIO_MP_LSB 0x87 187 + #define STMPE1601_REG_INT_STA_GPIO_LSB 0x19 188 + #define STMPE1601_REG_CHIP_ID 0x80 189 + #define STMPE1601_REG_GPIO_SET_MSB 0x82 210 190 #define STMPE1601_REG_GPIO_SET_LSB 0x83 191 + #define STMPE1601_REG_GPIO_CLR_MSB 0x84 211 192 #define STMPE1601_REG_GPIO_CLR_LSB 0x85 193 + #define STMPE1601_REG_GPIO_MP_MSB 0x86 194 + #define STMPE1601_REG_GPIO_MP_LSB 0x87 195 + #define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88 212 196 #define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89 213 197 #define STMPE1601_REG_GPIO_ED_MSB 0x8A 198 + #define STMPE1601_REG_GPIO_ED_LSB 0x8B 199 + #define STMPE1601_REG_GPIO_RE_MSB 0x8C 214 200 #define STMPE1601_REG_GPIO_RE_LSB 0x8D 201 + #define STMPE1601_REG_GPIO_FE_MSB 0x8E 215 202 #define STMPE1601_REG_GPIO_FE_LSB 0x8F 203 + #define STMPE1601_REG_GPIO_PU_MSB 0x90 216 204 #define STMPE1601_REG_GPIO_PU_LSB 0x91 217 205 #define STMPE1601_REG_GPIO_AF_U_MSB 0x92 218 206 ··· 281 243 #define STMPE1801_REG_GPIO_PULL_UP_MID 0x23 282 244 #define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24 283 245 284 - #define STMPE1801_MSK_SYS_CTRL_RESET (1 << 7) 285 - 286 246 #define STMPE1801_MSK_INT_EN_KPC (1 << 1) 287 247 #define STMPE1801_MSK_INT_EN_GPIO (1 << 3) 288 248 ··· 300 264 #define STMPE24XX_NR_INTERNAL_IRQS 9 301 265 302 266 #define STMPE24XX_REG_SYS_CTRL 0x02 267 + #define STMPE24XX_REG_SYS_CTRL2 0x03 268 + #define STMPE24XX_REG_ICR_MSB 0x10 303 269 #define STMPE24XX_REG_ICR_LSB 0x11 270 + #define STMPE24XX_REG_IER_MSB 0x12 304 271 #define STMPE24XX_REG_IER_LSB 0x13 305 272 #define STMPE24XX_REG_ISR_MSB 0x14 306 - #define STMPE24XX_REG_CHIP_ID 0x80 273 + #define STMPE24XX_REG_ISR_LSB 0x15 274 + #define STMPE24XX_REG_IEGPIOR_MSB 0x16 275 + #define STMPE24XX_REG_IEGPIOR_CSB 0x17 307 276 #define STMPE24XX_REG_IEGPIOR_LSB 0x18 308 277 #define STMPE24XX_REG_ISGPIOR_MSB 0x19 309 - #define STMPE24XX_REG_GPMR_LSB 0xA4 278 + #define STMPE24XX_REG_ISGPIOR_CSB 0x1A 279 + #define STMPE24XX_REG_ISGPIOR_LSB 0x1B 280 + #define STMPE24XX_REG_CHIP_ID 0x80 281 + #define STMPE24XX_REG_GPSR_MSB 0x83 282 + #define STMPE24XX_REG_GPSR_CSB 0x84 310 283 #define STMPE24XX_REG_GPSR_LSB 0x85 284 + #define STMPE24XX_REG_GPCR_MSB 0x86 285 + #define STMPE24XX_REG_GPCR_CSB 0x87 311 286 #define STMPE24XX_REG_GPCR_LSB 0x88 287 + #define STMPE24XX_REG_GPDR_MSB 0x89 288 + #define STMPE24XX_REG_GPDR_CSB 0x8A 312 289 #define STMPE24XX_REG_GPDR_LSB 0x8B 313 290 #define STMPE24XX_REG_GPEDR_MSB 0x8C 291 + #define STMPE24XX_REG_GPEDR_CSB 0x8D 292 + #define STMPE24XX_REG_GPEDR_LSB 0x8E 293 + #define STMPE24XX_REG_GPRER_MSB 0x8F 294 + #define STMPE24XX_REG_GPRER_CSB 0x90 314 295 #define STMPE24XX_REG_GPRER_LSB 0x91 296 + #define STMPE24XX_REG_GPFER_MSB 0x92 297 + #define STMPE24XX_REG_GPFER_CSB 0x93 315 298 #define STMPE24XX_REG_GPFER_LSB 0x94 299 + #define STMPE24XX_REG_GPPUR_MSB 0x95 300 + #define STMPE24XX_REG_GPPUR_CSB 0x96 316 301 #define STMPE24XX_REG_GPPUR_LSB 0x97 317 - #define STMPE24XX_REG_GPPDR_LSB 0x9a 302 + #define STMPE24XX_REG_GPPDR_MSB 0x98 303 + #define STMPE24XX_REG_GPPDR_CSB 0x99 304 + #define STMPE24XX_REG_GPPDR_LSB 0x9A 318 305 #define STMPE24XX_REG_GPAFR_U_MSB 0x9B 319 - 306 + #define STMPE24XX_REG_GPMR_MSB 0xA2 307 + #define STMPE24XX_REG_GPMR_CSB 0xA3 308 + #define STMPE24XX_REG_GPMR_LSB 0xA4 320 309 #define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3) 321 310 #define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2) 322 311 #define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)

+21

include/linux/mfd/stmpe.h

··· 26 26 STMPE610, 27 27 STMPE801, 28 28 STMPE811, 29 + STMPE1600, 29 30 STMPE1601, 30 31 STMPE1801, 31 32 STMPE2401, ··· 40 39 */ 41 40 enum { 42 41 STMPE_IDX_CHIP_ID, 42 + STMPE_IDX_SYS_CTRL, 43 + STMPE_IDX_SYS_CTRL2, 43 44 STMPE_IDX_ICR_LSB, 44 45 STMPE_IDX_IER_LSB, 46 + STMPE_IDX_IER_MSB, 45 47 STMPE_IDX_ISR_LSB, 46 48 STMPE_IDX_ISR_MSB, 47 49 STMPE_IDX_GPMR_LSB, 50 + STMPE_IDX_GPMR_CSB, 51 + STMPE_IDX_GPMR_MSB, 48 52 STMPE_IDX_GPSR_LSB, 53 + STMPE_IDX_GPSR_CSB, 54 + STMPE_IDX_GPSR_MSB, 49 55 STMPE_IDX_GPCR_LSB, 56 + STMPE_IDX_GPCR_CSB, 57 + STMPE_IDX_GPCR_MSB, 50 58 STMPE_IDX_GPDR_LSB, 59 + STMPE_IDX_GPDR_CSB, 60 + STMPE_IDX_GPDR_MSB, 61 + STMPE_IDX_GPEDR_LSB, 62 + STMPE_IDX_GPEDR_CSB, 51 63 STMPE_IDX_GPEDR_MSB, 52 64 STMPE_IDX_GPRER_LSB, 65 + STMPE_IDX_GPRER_CSB, 66 + STMPE_IDX_GPRER_MSB, 53 67 STMPE_IDX_GPFER_LSB, 68 + STMPE_IDX_GPFER_CSB, 69 + STMPE_IDX_GPFER_MSB, 54 70 STMPE_IDX_GPPUR_LSB, 55 71 STMPE_IDX_GPPDR_LSB, 56 72 STMPE_IDX_GPAFR_U_MSB, 57 73 STMPE_IDX_IEGPIOR_LSB, 74 + STMPE_IDX_IEGPIOR_CSB, 75 + STMPE_IDX_IEGPIOR_MSB, 58 76 STMPE_IDX_ISGPIOR_LSB, 77 + STMPE_IDX_ISGPIOR_CSB, 59 78 STMPE_IDX_ISGPIOR_MSB, 60 79 STMPE_IDX_MAX, 61 80 };