Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Revert "usb:cdns3 Add Cadence USB3 DRD Driver"

This reverts commit 8bc1901ca7b07d864fca11461b3875b31f949765.

It's broken.

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

-6916
-2
drivers/usb/Kconfig
··· 113 113 114 114 endif 115 115 116 - source "drivers/usb/cdns3/Kconfig" 117 - 118 116 source "drivers/usb/mtu3/Kconfig" 119 117 120 118 source "drivers/usb/musb/Kconfig"
-2
drivers/usb/Makefile
··· 13 13 obj-$(CONFIG_USB_DWC2) += dwc2/ 14 14 obj-$(CONFIG_USB_ISP1760) += isp1760/ 15 15 16 - obj-$(CONFIG_USB_CDNS3) += cdns3/ 17 - 18 16 obj-$(CONFIG_USB_MON) += mon/ 19 17 obj-$(CONFIG_USB_MTU3) += mtu3/ 20 18
-44
drivers/usb/cdns3/Kconfig
··· 1 - config USB_CDNS3 2 - tristate "Cadence USB3 Dual-Role Controller" 3 - depends on USB_SUPPORT && (USB || USB_GADGET) && HAS_DMA 4 - help 5 - Say Y here if your system has a Cadence USB3 dual-role controller. 6 - It supports: dual-role switch, Host-only, and Peripheral-only. 7 - 8 - If you choose to build this driver is a dynamically linked 9 - as module, the module will be called cdns3.ko. 10 - 11 - if USB_CDNS3 12 - 13 - config USB_CDNS3_GADGET 14 - bool "Cadence USB3 device controller" 15 - depends on USB_GADGET 16 - help 17 - Say Y here to enable device controller functionality of the 18 - Cadence USBSS-DEV driver. 19 - 20 - This controller supports FF, HS and SS mode. It doesn't support 21 - LS and SSP mode. 22 - 23 - config USB_CDNS3_HOST 24 - bool "Cadence USB3 host controller" 25 - depends on USB_XHCI_HCD 26 - help 27 - Say Y here to enable host controller functionality of the 28 - Cadence driver. 29 - 30 - Host controller is compliant with XHCI so it will use 31 - standard XHCI driver. 32 - 33 - config USB_CDNS3_PCI_WRAP 34 - tristate "Cadence USB3 support on PCIe-based platforms" 35 - depends on USB_PCI && ACPI 36 - default USB_CDNS3 37 - help 38 - If you're using the USBSS Core IP with a PCIe, please say 39 - 'Y' or 'M' here. 40 - 41 - If you choose to build this driver as module it will 42 - be dynamically linked and module will be called cdns3-pci.ko 43 - 44 - endif
-14
drivers/usb/cdns3/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - # define_trace.h needs to know how to find our header 3 - CFLAGS_trace.o := -I$(src) 4 - 5 - cdns3-y := core.o drd.o 6 - 7 - obj-$(CONFIG_USB_CDNS3) += cdns3.o 8 - ifneq ($(CONFIG_DEBUG_FS),) 9 - cdns3-y += debugfs.o 10 - endif 11 - 12 - cdns3-$(CONFIG_USB_CDNS3_GADGET) += gadget.o ep0.o trace.o 13 - cdns3-$(CONFIG_USB_CDNS3_HOST) += host.o 14 - obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
-157
drivers/usb/cdns3/cdns3-pci-wrap.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Cadence USBSS PCI Glue driver 4 - * 5 - * Copyright (C) 2018-2019 Cadence. 6 - * 7 - * Author: Pawel Laszczak <pawell@cadence.com> 8 - */ 9 - 10 - #include <linux/kernel.h> 11 - #include <linux/module.h> 12 - #include <linux/pci.h> 13 - #include <linux/platform_device.h> 14 - #include <linux/dma-mapping.h> 15 - #include <linux/slab.h> 16 - 17 - struct cdns3_wrap { 18 - struct platform_device *plat_dev; 19 - struct pci_dev *hg_dev; 20 - struct resource dev_res[6]; 21 - }; 22 - 23 - #define RES_IRQ_HOST_ID 0 24 - #define RES_IRQ_PERIPHERAL_ID 1 25 - #define RES_IRQ_OTG_ID 2 26 - #define RES_HOST_ID 3 27 - #define RES_DEV_ID 4 28 - #define RES_DRD_ID 5 29 - 30 - #define PCI_BAR_HOST 0 31 - #define PCI_BAR_DEV 2 32 - #define PCI_BAR_OTG 4 33 - 34 - #define PCI_DEV_FN_HOST_DEVICE 0 35 - #define PCI_DEV_FN_OTG 1 36 - 37 - #define PCI_DRIVER_NAME "cdns3-pci-usbss" 38 - #define PLAT_DRIVER_NAME "cdns-usb3" 39 - 40 - #define CDNS_VENDOR_ID 0x17cd 41 - #define CDNS_DEVICE_ID 0x0100 42 - 43 - static int cdns3_pci_probe(struct pci_dev *pdev, 44 - const struct pci_device_id *id) 45 - { 46 - struct platform_device_info plat_info; 47 - struct cdns3_wrap *wrap; 48 - struct resource *res; 49 - int err; 50 - 51 - /* 52 - * for GADGET/HOST PCI (devfn) function number is 0, 53 - * for OTG PCI (devfn) function number is 1 54 - */ 55 - if (!id || pdev->devfn != PCI_DEV_FN_HOST_DEVICE) 56 - return -EINVAL; 57 - 58 - err = pcim_enable_device(pdev); 59 - if (err) { 60 - dev_err(&pdev->dev, "Enabling PCI device has failed %d\n", err); 61 - return err; 62 - } 63 - 64 - pci_set_master(pdev); 65 - wrap = devm_kzalloc(&pdev->dev, sizeof(*wrap), GFP_KERNEL); 66 - if (!wrap) { 67 - pci_disable_device(pdev); 68 - return -ENOMEM; 69 - } 70 - 71 - /* function 0: host(BAR_0) + device(BAR_1) + otg(BAR_2)). */ 72 - dev_dbg(&pdev->dev, "Initialize Device resources\n"); 73 - res = wrap->dev_res; 74 - 75 - res[RES_DEV_ID].start = pci_resource_start(pdev, PCI_BAR_DEV); 76 - res[RES_DEV_ID].end = pci_resource_end(pdev, PCI_BAR_DEV); 77 - res[RES_DEV_ID].name = "dev"; 78 - res[RES_DEV_ID].flags = IORESOURCE_MEM; 79 - dev_dbg(&pdev->dev, "USBSS-DEV physical base addr: %pa\n", 80 - &res[RES_DEV_ID].start); 81 - 82 - res[RES_HOST_ID].start = pci_resource_start(pdev, PCI_BAR_HOST); 83 - res[RES_HOST_ID].end = pci_resource_end(pdev, PCI_BAR_HOST); 84 - res[RES_HOST_ID].name = "xhci"; 85 - res[RES_HOST_ID].flags = IORESOURCE_MEM; 86 - dev_dbg(&pdev->dev, "USBSS-XHCI physical base addr: %pa\n", 87 - &res[RES_HOST_ID].start); 88 - 89 - res[RES_DRD_ID].start = pci_resource_start(pdev, PCI_BAR_OTG); 90 - res[RES_DRD_ID].end = pci_resource_end(pdev, PCI_BAR_OTG); 91 - res[RES_DRD_ID].name = "otg"; 92 - res[RES_DRD_ID].flags = IORESOURCE_MEM; 93 - dev_dbg(&pdev->dev, "USBSS-DRD physical base addr: %pa\n", 94 - &res[RES_DRD_ID].start); 95 - 96 - /* Interrupt for XHCI */ 97 - wrap->dev_res[RES_IRQ_HOST_ID].start = pdev->irq; 98 - wrap->dev_res[RES_IRQ_HOST_ID].name = "host"; 99 - wrap->dev_res[RES_IRQ_HOST_ID].flags = IORESOURCE_IRQ; 100 - 101 - /* Interrupt device. It's the same as for HOST. */ 102 - wrap->dev_res[RES_IRQ_PERIPHERAL_ID].start = pdev->irq; 103 - wrap->dev_res[RES_IRQ_PERIPHERAL_ID].name = "peripheral"; 104 - wrap->dev_res[RES_IRQ_PERIPHERAL_ID].flags = IORESOURCE_IRQ; 105 - 106 - /* Interrupt for OTG/DRD. */ 107 - wrap->dev_res[RES_IRQ_OTG_ID].start = pdev->irq; 108 - wrap->dev_res[RES_IRQ_OTG_ID].name = "otg"; 109 - wrap->dev_res[RES_IRQ_OTG_ID].flags = IORESOURCE_IRQ; 110 - 111 - /* set up platform device info */ 112 - memset(&plat_info, 0, sizeof(plat_info)); 113 - plat_info.parent = &pdev->dev; 114 - plat_info.fwnode = pdev->dev.fwnode; 115 - plat_info.name = PLAT_DRIVER_NAME; 116 - plat_info.id = pdev->devfn; 117 - plat_info.res = wrap->dev_res; 118 - plat_info.num_res = ARRAY_SIZE(wrap->dev_res); 119 - plat_info.dma_mask = pdev->dma_mask; 120 - 121 - /* register platform device */ 122 - wrap->plat_dev = platform_device_register_full(&plat_info); 123 - if (IS_ERR(wrap->plat_dev)) { 124 - pci_disable_device(pdev); 125 - return PTR_ERR(wrap->plat_dev); 126 - } 127 - 128 - pci_set_drvdata(pdev, wrap); 129 - 130 - return err; 131 - } 132 - 133 - static void cdns3_pci_remove(struct pci_dev *pdev) 134 - { 135 - struct cdns3_wrap *wrap = (struct cdns3_wrap *)pci_get_drvdata(pdev); 136 - 137 - platform_device_unregister(wrap->plat_dev); 138 - } 139 - 140 - static const struct pci_device_id cdns3_pci_ids[] = { 141 - { PCI_DEVICE(CDNS_VENDOR_ID, CDNS_DEVICE_ID), }, 142 - { 0, } 143 - }; 144 - 145 - static struct pci_driver cdns3_pci_driver = { 146 - .name = PCI_DRIVER_NAME, 147 - .id_table = cdns3_pci_ids, 148 - .probe = cdns3_pci_probe, 149 - .remove = cdns3_pci_remove, 150 - }; 151 - 152 - module_pci_driver(cdns3_pci_driver); 153 - MODULE_DEVICE_TABLE(pci, cdns3_pci_ids); 154 - 155 - MODULE_AUTHOR("Pawel Laszczak <pawell@cadence.com>"); 156 - MODULE_LICENSE("GPL v2"); 157 - MODULE_DESCRIPTION("Cadence USBSS PCI wrapperr");
-543
drivers/usb/cdns3/core.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Cadence USBSS DRD Driver. 4 - * 5 - * Copyright (C) 2018-2019 Cadence. 6 - * Copyright (C) 2017-2018 NXP 7 - * Copyright (C) 2019 Texas Instruments 8 - * 9 - * Author: Peter Chen <peter.chen@nxp.com> 10 - * Pawel Laszczak <pawell@cadence.com> 11 - * Roger Quadros <rogerq@ti.com> 12 - */ 13 - 14 - #include <linux/dma-mapping.h> 15 - #include <linux/module.h> 16 - #include <linux/kernel.h> 17 - #include <linux/platform_device.h> 18 - #include <linux/interrupt.h> 19 - #include <linux/io.h> 20 - #include <linux/pm_runtime.h> 21 - 22 - #include "gadget.h" 23 - #include "core.h" 24 - #include "host-export.h" 25 - #include "gadget-export.h" 26 - #include "drd.h" 27 - #include "debug.h" 28 - 29 - /** 30 - * cdns3_handshake - spin reading until handshake completes or fails 31 - * @ptr: address of device controller register to be read 32 - * @mask: bits to look at in result of read 33 - * @done: value of those bits when handshake succeeds 34 - * @usec: timeout in microseconds 35 - * 36 - * Returns negative errno, or zero on success 37 - * 38 - * Success happens when the "mask" bits have the specified value (hardware 39 - * handshake done). There are two failure modes: "usec" have passed (major 40 - * hardware flakeout), or the register reads as all-ones (hardware removed). 41 - */ 42 - int cdns3_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) 43 - { 44 - u32 result; 45 - 46 - do { 47 - result = readl(ptr); 48 - if (result == ~(u32)0) /* card removed */ 49 - return -ENODEV; 50 - 51 - result &= mask; 52 - if (result == done) 53 - return 0; 54 - 55 - udelay(1); 56 - usec--; 57 - } while (usec > 0); 58 - 59 - return -ETIMEDOUT; 60 - } 61 - 62 - static inline 63 - struct cdns3_role_driver *cdns3_get_current_role_driver(struct cdns3 *cdns) 64 - { 65 - WARN_ON(cdns->role >= CDNS3_ROLE_END || !cdns->roles[cdns->role]); 66 - return cdns->roles[cdns->role]; 67 - } 68 - 69 - static int cdns3_role_start(struct cdns3 *cdns, enum cdns3_roles role) 70 - { 71 - int ret; 72 - 73 - if (WARN_ON(role >= CDNS3_ROLE_END)) 74 - return 0; 75 - 76 - if (!cdns->roles[role]) 77 - return -ENXIO; 78 - 79 - if (cdns->roles[role]->state == CDNS3_ROLE_STATE_ACTIVE) 80 - return 0; 81 - 82 - mutex_lock(&cdns->mutex); 83 - cdns->role = role; 84 - ret = cdns->roles[role]->start(cdns); 85 - if (!ret) 86 - cdns->roles[role]->state = CDNS3_ROLE_STATE_ACTIVE; 87 - mutex_unlock(&cdns->mutex); 88 - return ret; 89 - } 90 - 91 - void cdns3_role_stop(struct cdns3 *cdns) 92 - { 93 - enum cdns3_roles role = cdns->role; 94 - 95 - if (role >= CDNS3_ROLE_END) { 96 - WARN_ON(role > CDNS3_ROLE_END); 97 - return; 98 - } 99 - 100 - if (cdns->roles[role]->state == CDNS3_ROLE_STATE_INACTIVE) 101 - return; 102 - 103 - mutex_lock(&cdns->mutex); 104 - cdns->roles[role]->stop(cdns); 105 - cdns->roles[role]->state = CDNS3_ROLE_STATE_INACTIVE; 106 - mutex_unlock(&cdns->mutex); 107 - } 108 - 109 - static void cdns3_exit_roles(struct cdns3 *cdns) 110 - { 111 - cdns3_role_stop(cdns); 112 - cdns3_drd_exit(cdns); 113 - } 114 - 115 - enum cdns3_roles cdsn3_get_real_role(struct cdns3 *cdns); 116 - 117 - static int cdns3_idle_role_start(struct cdns3 *cnds) 118 - { /* Hold PHY in RESET */ 119 - return 0; 120 - } 121 - 122 - static void cdns3_idle_role_stop(struct cdns3 *cnds) 123 - { 124 - /* Program Lane swap and bring PHY out of RESET */ 125 - } 126 - 127 - static int cdns3_idle_init(struct cdns3 *cdns) 128 - { 129 - struct cdns3_role_driver *rdrv; 130 - 131 - rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL); 132 - if (!rdrv) 133 - return -ENOMEM; 134 - 135 - rdrv->start = cdns3_idle_role_start; 136 - rdrv->stop = cdns3_idle_role_stop; 137 - rdrv->state = CDNS3_ROLE_STATE_INACTIVE; 138 - rdrv->suspend = NULL; 139 - rdrv->resume = NULL; 140 - rdrv->name = "idle"; 141 - 142 - cdns->roles[CDNS3_ROLE_IDLE] = rdrv; 143 - 144 - return 0; 145 - } 146 - 147 - /** 148 - * cdns3_core_init_role - initialize role of operation 149 - * @cdns: Pointer to cdns3 structure 150 - * 151 - * Returns 0 on success otherwise negative errno 152 - */ 153 - static int cdns3_core_init_role(struct cdns3 *cdns) 154 - { 155 - struct device *dev = cdns->dev; 156 - enum usb_dr_mode best_dr_mode; 157 - enum usb_dr_mode dr_mode; 158 - int ret = 0; 159 - 160 - dr_mode = usb_get_dr_mode(dev); 161 - cdns->role = CDNS3_ROLE_END; 162 - 163 - /* 164 - * If driver can't read mode by means of usb_get_dr_mode function then 165 - * chooses mode according with Kernel configuration. This setting 166 - * can be restricted later depending on strap pin configuration. 167 - */ 168 - if (dr_mode == USB_DR_MODE_UNKNOWN) { 169 - if (IS_ENABLED(CONFIG_USB_CDNS3_HOST) && 170 - IS_ENABLED(CONFIG_USB_CDNS3_GADGET)) 171 - dr_mode = USB_DR_MODE_OTG; 172 - else if (IS_ENABLED(CONFIG_USB_CDNS3_HOST)) 173 - dr_mode = USB_DR_MODE_HOST; 174 - else if (IS_ENABLED(CONFIG_USB_CDNS3_GADGET)) 175 - dr_mode = USB_DR_MODE_PERIPHERAL; 176 - } 177 - 178 - /* 179 - * At this point cdns->dr_mode contains strap configuration. 180 - * Driver try update this setting considering kernel configuration 181 - */ 182 - best_dr_mode = cdns->dr_mode; 183 - 184 - ret = cdns3_idle_init(cdns); 185 - if (ret) 186 - return ret; 187 - 188 - if (dr_mode == USB_DR_MODE_OTG) { 189 - best_dr_mode = cdns->dr_mode; 190 - } else if (cdns->dr_mode == USB_DR_MODE_OTG) { 191 - best_dr_mode = dr_mode; 192 - } else if (cdns->dr_mode != dr_mode) { 193 - dev_err(dev, "Incorrect DRD configuration\n"); 194 - return -EINVAL; 195 - } 196 - 197 - dr_mode = best_dr_mode; 198 - 199 - if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 200 - ret = cdns3_host_init(cdns); 201 - if (ret) { 202 - dev_err(dev, "Host initialization failed with %d\n", 203 - ret); 204 - goto err; 205 - } 206 - } 207 - 208 - if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 209 - ret = cdns3_gadget_init(cdns); 210 - if (ret) { 211 - dev_err(dev, "Device initialization failed with %d\n", 212 - ret); 213 - goto err; 214 - } 215 - } 216 - 217 - cdns->desired_dr_mode = dr_mode; 218 - cdns->dr_mode = dr_mode; 219 - 220 - /* 221 - * desired_dr_mode might have changed so we need to update 222 - * the controller configuration"? 223 - */ 224 - ret = cdns3_drd_update_mode(cdns); 225 - if (ret) 226 - goto err; 227 - 228 - cdns->role = cdsn3_get_real_role(cdns); 229 - 230 - ret = cdns3_role_start(cdns, cdns->role); 231 - if (ret) { 232 - dev_err(dev, "can't start %s role\n", 233 - cdns3_get_current_role_driver(cdns)->name); 234 - goto err; 235 - } 236 - 237 - return ret; 238 - err: 239 - cdns3_exit_roles(cdns); 240 - return ret; 241 - } 242 - 243 - /** 244 - * cdsn3_get_real_role - get real role of controller based on hardware settings. 245 - * @cdns: Pointer to cdns3 structure 246 - * 247 - * Returns role 248 - */ 249 - enum cdns3_roles cdsn3_get_real_role(struct cdns3 *cdns) 250 - { 251 - enum cdns3_roles role; 252 - int id, vbus; 253 - 254 - if (cdns->current_dr_mode != USB_DR_MODE_OTG) 255 - goto not_otg; 256 - 257 - id = cdns3_get_id(cdns); 258 - vbus = cdns3_get_vbus(cdns); 259 - 260 - /* 261 - * Role change state machine 262 - * Inputs: ID, VBUS 263 - * Previous state: cdns->role 264 - * Next state: role 265 - */ 266 - role = cdns->role; 267 - 268 - switch (role) { 269 - case CDNS3_ROLE_IDLE: /* from IDLE, we can change to HOST or GADGET */ 270 - if (!id) 271 - role = CDNS3_ROLE_HOST; 272 - else if (vbus) 273 - role = CDNS3_ROLE_GADGET; 274 - break; 275 - case CDNS3_ROLE_HOST: /* from HOST, we can only change to IDLE */ 276 - if (id) 277 - role = CDNS3_ROLE_IDLE; 278 - break; 279 - case CDNS3_ROLE_GADGET: /* from GADGET, we can only change to IDLE */ 280 - if (!vbus) 281 - role = CDNS3_ROLE_IDLE; 282 - break; 283 - case CDNS3_ROLE_END: /* only at initialization, move to IDLE */ 284 - role = CDNS3_ROLE_IDLE; 285 - break; 286 - } 287 - 288 - dev_dbg(cdns->dev, "role %d -> %d\n", cdns->role, role); 289 - 290 - return role; 291 - 292 - not_otg: 293 - if (cdns3_is_host(cdns)) 294 - role = CDNS3_ROLE_HOST; 295 - if (cdns3_is_device(cdns)) 296 - role = CDNS3_ROLE_GADGET; 297 - 298 - return role; 299 - } 300 - 301 - /** 302 - * cdns3_role_switch - work queue handler for role switch 303 - * 304 - * @work: work queue item structure 305 - * 306 - * Handles below events: 307 - * - Role switch for dual-role devices 308 - * - CDNS3_ROLE_GADGET <--> CDNS3_ROLE_END for peripheral-only devices 309 - */ 310 - static void cdns3_role_switch(struct work_struct *work) 311 - { 312 - enum cdns3_roles role = CDNS3_ROLE_END; 313 - struct cdns3_role_driver *role_drv; 314 - enum cdns3_roles current_role; 315 - struct cdns3 *cdns; 316 - int ret = 0; 317 - 318 - cdns = container_of(work, struct cdns3, role_switch_wq); 319 - 320 - pm_runtime_get_sync(cdns->dev); 321 - 322 - role = cdsn3_get_real_role(cdns); 323 - 324 - role_drv = cdns3_get_current_role_driver(cdns); 325 - 326 - /* Disable current role if requested from debugfs */ 327 - if (cdns->debug_disable && role_drv->state == CDNS3_ROLE_STATE_ACTIVE) { 328 - cdns3_role_stop(cdns); 329 - goto exit; 330 - } 331 - 332 - /* Do nothing if nothing changed */ 333 - if (cdns->role == role && role_drv->state == CDNS3_ROLE_STATE_ACTIVE) 334 - goto exit; 335 - 336 - cdns3_role_stop(cdns); 337 - 338 - role = cdsn3_get_real_role(cdns); 339 - 340 - current_role = cdns->role; 341 - dev_dbg(cdns->dev, "Switching role"); 342 - 343 - ret = cdns3_role_start(cdns, role); 344 - if (ret) { 345 - /* Back to current role */ 346 - dev_err(cdns->dev, "set %d has failed, back to %d\n", 347 - role, current_role); 348 - ret = cdns3_role_start(cdns, current_role); 349 - if (ret) 350 - dev_err(cdns->dev, "back to %d failed too\n", 351 - current_role); 352 - } 353 - exit: 354 - pm_runtime_put_sync(cdns->dev); 355 - } 356 - 357 - /** 358 - * cdns3_probe - probe for cdns3 core device 359 - * @pdev: Pointer to cdns3 core platform device 360 - * 361 - * Returns 0 on success otherwise negative errno 362 - */ 363 - static int cdns3_probe(struct platform_device *pdev) 364 - { 365 - struct device *dev = &pdev->dev; 366 - struct resource *res; 367 - struct cdns3 *cdns; 368 - void __iomem *regs; 369 - int ret; 370 - 371 - ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 372 - if (ret) { 373 - dev_err(dev, "error setting dma mask: %d\n", ret); 374 - return -ENODEV; 375 - } 376 - 377 - cdns = devm_kzalloc(dev, sizeof(*cdns), GFP_KERNEL); 378 - if (!cdns) 379 - return -ENOMEM; 380 - 381 - cdns->dev = dev; 382 - 383 - platform_set_drvdata(pdev, cdns); 384 - 385 - res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host"); 386 - if (!res) { 387 - dev_err(dev, "missing host IRQ\n"); 388 - return -ENODEV; 389 - } 390 - 391 - cdns->xhci_res[0] = *res; 392 - 393 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "xhci"); 394 - if (!res) { 395 - dev_err(dev, "couldn't get xhci resource\n"); 396 - return -ENXIO; 397 - } 398 - 399 - cdns->xhci_res[1] = *res; 400 - 401 - cdns->dev_irq = platform_get_irq_byname(pdev, "peripheral"); 402 - if (cdns->dev_irq == -EPROBE_DEFER) 403 - return cdns->dev_irq; 404 - 405 - if (cdns->dev_irq < 0) 406 - dev_err(dev, "couldn't get peripheral irq\n"); 407 - 408 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dev"); 409 - regs = devm_ioremap_resource(dev, res); 410 - if (IS_ERR(regs)) { 411 - dev_err(dev, "couldn't iomap dev resource\n"); 412 - return PTR_ERR(regs); 413 - } 414 - cdns->dev_regs = regs; 415 - 416 - cdns->otg_irq = platform_get_irq_byname(pdev, "otg"); 417 - if (cdns->otg_irq == -EPROBE_DEFER) 418 - return cdns->otg_irq; 419 - 420 - if (cdns->otg_irq < 0) { 421 - dev_err(dev, "couldn't get otg irq\n"); 422 - return cdns->otg_irq; 423 - } 424 - 425 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otg"); 426 - if (!res) { 427 - dev_err(dev, "couldn't get otg resource\n"); 428 - return -ENXIO; 429 - } 430 - 431 - cdns->otg_res = *res; 432 - 433 - mutex_init(&cdns->mutex); 434 - 435 - cdns->usb2_phy = devm_phy_optional_get(dev, "cdns3,usb2-phy"); 436 - if (IS_ERR(cdns->usb2_phy)) 437 - return PTR_ERR(cdns->usb2_phy); 438 - 439 - phy_init(cdns->usb2_phy); 440 - ret = phy_init(cdns->usb2_phy); 441 - if (ret) 442 - return ret; 443 - 444 - cdns->usb3_phy = devm_phy_optional_get(dev, "cdns3,usb3-phy"); 445 - if (IS_ERR(cdns->usb3_phy)) 446 - return PTR_ERR(cdns->usb3_phy); 447 - 448 - phy_init(cdns->usb3_phy); 449 - ret = phy_init(cdns->usb3_phy); 450 - if (ret) 451 - return ret; 452 - 453 - ret = phy_power_on(cdns->usb2_phy); 454 - if (ret) 455 - return ret; 456 - 457 - ret = phy_power_on(cdns->usb3_phy); 458 - if (ret) 459 - goto err1; 460 - 461 - INIT_WORK(&cdns->role_switch_wq, cdns3_role_switch); 462 - 463 - ret = cdns3_drd_init(cdns); 464 - if (ret) 465 - goto err2; 466 - 467 - ret = cdns3_core_init_role(cdns); 468 - if (ret) 469 - goto err2; 470 - 471 - cdns3_debugfs_init(cdns); 472 - device_set_wakeup_capable(dev, true); 473 - pm_runtime_set_active(dev); 474 - pm_runtime_enable(dev); 475 - 476 - /* 477 - * The controller needs less time between bus and controller suspend, 478 - * and we also needs a small delay to avoid frequently entering low 479 - * power mode. 480 - */ 481 - pm_runtime_set_autosuspend_delay(dev, 20); 482 - pm_runtime_mark_last_busy(dev); 483 - pm_runtime_use_autosuspend(dev); 484 - dev_dbg(dev, "Cadence USB3 core: probe succeed\n"); 485 - 486 - return 0; 487 - 488 - err2: 489 - phy_power_off(cdns->usb3_phy); 490 - 491 - err1: 492 - phy_power_off(cdns->usb2_phy); 493 - phy_exit(cdns->usb2_phy); 494 - phy_exit(cdns->usb3_phy); 495 - 496 - return ret; 497 - } 498 - 499 - /** 500 - * cdns3_remove - unbind drd driver and clean up 501 - * @pdev: Pointer to Linux platform device 502 - * 503 - * Returns 0 on success otherwise negative errno 504 - */ 505 - static int cdns3_remove(struct platform_device *pdev) 506 - { 507 - struct cdns3 *cdns = platform_get_drvdata(pdev); 508 - 509 - pm_runtime_get_sync(&pdev->dev); 510 - pm_runtime_disable(&pdev->dev); 511 - pm_runtime_put_noidle(&pdev->dev); 512 - cdns3_debugfs_exit(cdns); 513 - cdns3_exit_roles(cdns); 514 - phy_power_off(cdns->usb2_phy); 515 - phy_power_off(cdns->usb3_phy); 516 - phy_exit(cdns->usb2_phy); 517 - phy_exit(cdns->usb3_phy); 518 - return 0; 519 - } 520 - 521 - #ifdef CONFIG_OF 522 - static const struct of_device_id of_cdns3_match[] = { 523 - { .compatible = "cdns,usb3" }, 524 - { }, 525 - }; 526 - MODULE_DEVICE_TABLE(of, of_cdns3_match); 527 - #endif 528 - 529 - static struct platform_driver cdns3_driver = { 530 - .probe = cdns3_probe, 531 - .remove = cdns3_remove, 532 - .driver = { 533 - .name = "cdns-usb3", 534 - .of_match_table = of_match_ptr(of_cdns3_match), 535 - }, 536 - }; 537 - 538 - module_platform_driver(cdns3_driver); 539 - 540 - MODULE_ALIAS("platform:cdns3"); 541 - MODULE_AUTHOR("Pawel Laszczak <pawell@cadence.com>"); 542 - MODULE_LICENSE("GPL v2"); 543 - MODULE_DESCRIPTION("Cadence USB3 DRD Controller Driver");
-121
drivers/usb/cdns3/core.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * Cadence USBSS DRD Header File. 4 - * 5 - * Copyright (C) 2017-2018 NXP 6 - * Copyright (C) 2018-2019 Cadence. 7 - * 8 - * Authors: Peter Chen <peter.chen@nxp.com> 9 - * Pawel Laszczak <pawell@cadence.com> 10 - */ 11 - #include <linux/usb/otg.h> 12 - 13 - #ifndef __LINUX_CDNS3_CORE_H 14 - #define __LINUX_CDNS3_CORE_H 15 - 16 - struct cdns3; 17 - enum cdns3_roles { 18 - CDNS3_ROLE_IDLE = 0, 19 - CDNS3_ROLE_HOST, 20 - CDNS3_ROLE_GADGET, 21 - CDNS3_ROLE_END, 22 - }; 23 - 24 - /** 25 - * struct cdns3_role_driver - host/gadget role driver 26 - * @start: start this role 27 - * @stop: stop this role 28 - * @suspend: suspend callback for this role 29 - * @resume: resume callback for this role 30 - * @irq: irq handler for this role 31 - * @name: role name string (host/gadget) 32 - * @state: current state 33 - */ 34 - struct cdns3_role_driver { 35 - int (*start)(struct cdns3 *cdns); 36 - void (*stop)(struct cdns3 *cdns); 37 - int (*suspend)(struct cdns3 *cdns, bool do_wakeup); 38 - int (*resume)(struct cdns3 *cdns, bool hibernated); 39 - const char *name; 40 - #define CDNS3_ROLE_STATE_INACTIVE 0 41 - #define CDNS3_ROLE_STATE_ACTIVE 1 42 - int state; 43 - }; 44 - 45 - #define CDNS3_XHCI_RESOURCES_NUM 2 46 - /** 47 - * struct cdns3 - Representation of Cadence USB3 DRD controller. 48 - * @dev: pointer to Cadence device struct 49 - * @xhci_regs: pointer to base of xhci registers 50 - * @xhci_res: the resource for xhci 51 - * @dev_regs: pointer to base of dev registers 52 - * @otg_res: the resource for otg 53 - * @otg_v0_regs: pointer to base of v0 otg registers 54 - * @otg_v1_regs: pointer to base of v1 otg registers 55 - * @otg_regs: pointer to base of otg registers 56 - * @otg_irq: irq number for otg controller 57 - * @dev_irq: irq number for device controller 58 - * @roles: array of supported roles for this controller 59 - * @role: current role 60 - * @host_dev: the child host device pointer for cdns3 core 61 - * @gadget_dev: the child gadget device pointer for cdns3 core 62 - * @usb2_phy: pointer to USB2 PHY 63 - * @usb3_phy: pointer to USB3 PHY 64 - * @role_switch_wq: work queue item for role switch 65 - * @wakeup_int: the wakeup interrupt 66 - * @mutex: the mutex for concurrent code at driver 67 - * @dr_mode: supported mode of operation it can be only Host, only Device 68 - * or OTG mode that allow to switch between Device and Host mode. 69 - * This field based on firmware setting, kernel configuration 70 - * and hardware configuration. 71 - * @current_dr_mode: current mode of operation when in dual-role mode 72 - * @desired_dr_mode: desired mode of operation when in dual-role mode. 73 - * This value can be changed during runtime. 74 - * Available options depends on dr_mode: 75 - * dr_mode | desired_dr_mode and current_dr_mode 76 - * ---------------------------------------------------------------- 77 - * USB_DR_MODE_HOST | only USB_DR_MODE_HOST 78 - * USB_DR_MODE_PERIPHERAL | only USB_DR_MODE_PERIPHERAL 79 - * USB_DR_MODE_OTG | USB_DR_MODE_OTG or USB_DR_MODE_HOST or 80 - * | USB_DR_MODE_PERIPHERAL 81 - * Desired_dr_role can be changed by means of debugfs. 82 - * @root: debugfs root folder pointer 83 - * @debug_disable: 84 - */ 85 - struct cdns3 { 86 - struct device *dev; 87 - void __iomem *xhci_regs; 88 - struct resource xhci_res[CDNS3_XHCI_RESOURCES_NUM]; 89 - struct cdns3_usb_regs __iomem *dev_regs; 90 - 91 - struct resource otg_res; 92 - struct cdns3_otg_legacy_regs *otg_v0_regs; 93 - struct cdns3_otg_regs *otg_v1_regs; 94 - struct cdns3_otg_common_regs *otg_regs; 95 - #define CDNS3_CONTROLLER_V0 0 96 - #define CDNS3_CONTROLLER_V1 1 97 - u32 version; 98 - 99 - int otg_irq; 100 - int dev_irq; 101 - struct cdns3_role_driver *roles[CDNS3_ROLE_END]; 102 - enum cdns3_roles role; 103 - struct platform_device *host_dev; 104 - struct cdns3_device *gadget_dev; 105 - struct phy *usb2_phy; 106 - struct phy *usb3_phy; 107 - struct work_struct role_switch_wq; 108 - int wakeup_int:1; 109 - /* mutext used in workqueue*/ 110 - struct mutex mutex; 111 - enum usb_dr_mode dr_mode; 112 - enum usb_dr_mode current_dr_mode; 113 - enum usb_dr_mode desired_dr_mode; 114 - struct dentry *root; 115 - int debug_disable:1; 116 - }; 117 - 118 - void cdns3_role_stop(struct cdns3 *cdns); 119 - int cdns3_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 120 - 121 - #endif /* __LINUX_CDNS3_CORE_H */
-173
drivers/usb/cdns3/debug.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * Cadence USBSS DRD Driver. 4 - * Debug header file. 5 - * 6 - * Copyright (C) 2018-2019 Cadence. 7 - * 8 - * Author: Pawel Laszczak <pawell@cadence.com> 9 - */ 10 - #ifndef __LINUX_CDNS3_DEBUG 11 - #define __LINUX_CDNS3_DEBUG 12 - 13 - #include "core.h" 14 - 15 - static inline char *cdns3_decode_usb_irq(char *str, 16 - enum usb_device_speed speed, 17 - u32 usb_ists) 18 - { 19 - int ret; 20 - 21 - ret = sprintf(str, "IRQ %08x = ", usb_ists); 22 - 23 - if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) { 24 - ret += sprintf(str + ret, "Connection %s\n", 25 - usb_speed_string(speed)); 26 - } 27 - if (usb_ists & USB_ISTS_DIS2I || usb_ists & USB_ISTS_DISI) 28 - ret += sprintf(str + ret, "Disconnection "); 29 - if (usb_ists & USB_ISTS_L2ENTI) 30 - ret += sprintf(str + ret, "suspended "); 31 - if (usb_ists & USB_ISTS_L1ENTI) 32 - ret += sprintf(str + ret, "L1 enter "); 33 - if (usb_ists & USB_ISTS_L1EXTI) 34 - ret += sprintf(str + ret, "L1 exit "); 35 - if (usb_ists & USB_ISTS_L2ENTI) 36 - ret += sprintf(str + ret, "L2 enter "); 37 - if (usb_ists & USB_ISTS_L2EXTI) 38 - ret += sprintf(str + ret, "L2 exit "); 39 - if (usb_ists & USB_ISTS_U3EXTI) 40 - ret += sprintf(str + ret, "U3 exit "); 41 - if (usb_ists & USB_ISTS_UWRESI) 42 - ret += sprintf(str + ret, "Warm Reset "); 43 - if (usb_ists & USB_ISTS_UHRESI) 44 - ret += sprintf(str + ret, "Hot Reset "); 45 - if (usb_ists & USB_ISTS_U2RESI) 46 - ret += sprintf(str + ret, "Reset"); 47 - 48 - return str; 49 - } 50 - 51 - static inline char *cdns3_decode_ep_irq(char *str, 52 - u32 ep_sts, 53 - const char *ep_name) 54 - { 55 - int ret; 56 - 57 - ret = sprintf(str, "IRQ for %s: %08x ", ep_name, ep_sts); 58 - 59 - if (ep_sts & EP_STS_SETUP) 60 - ret += sprintf(str + ret, "SETUP "); 61 - if (ep_sts & EP_STS_IOC) 62 - ret += sprintf(str + ret, "IOC "); 63 - if (ep_sts & EP_STS_ISP) 64 - ret += sprintf(str + ret, "ISP "); 65 - if (ep_sts & EP_STS_DESCMIS) 66 - ret += sprintf(str + ret, "DESCMIS "); 67 - if (ep_sts & EP_STS_STREAMR) 68 - ret += sprintf(str + ret, "STREAMR "); 69 - if (ep_sts & EP_STS_MD_EXIT) 70 - ret += sprintf(str + ret, "MD_EXIT "); 71 - if (ep_sts & EP_STS_TRBERR) 72 - ret += sprintf(str + ret, "TRBERR "); 73 - if (ep_sts & EP_STS_NRDY) 74 - ret += sprintf(str + ret, "NRDY "); 75 - if (ep_sts & EP_STS_PRIME) 76 - ret += sprintf(str + ret, "PRIME "); 77 - if (ep_sts & EP_STS_SIDERR) 78 - ret += sprintf(str + ret, "SIDERRT "); 79 - if (ep_sts & EP_STS_OUTSMM) 80 - ret += sprintf(str + ret, "OUTSMM "); 81 - if (ep_sts & EP_STS_ISOERR) 82 - ret += sprintf(str + ret, "ISOERR "); 83 - if (ep_sts & EP_STS_IOT) 84 - ret += sprintf(str + ret, "IOT "); 85 - 86 - return str; 87 - } 88 - 89 - static inline char *cdns3_decode_epx_irq(char *str, 90 - char *ep_name, 91 - u32 ep_sts) 92 - { 93 - return cdns3_decode_ep_irq(str, ep_sts, ep_name); 94 - } 95 - 96 - static inline char *cdns3_decode_ep0_irq(char *str, 97 - int dir, 98 - u32 ep_sts) 99 - { 100 - return cdns3_decode_ep_irq(str, ep_sts, 101 - dir ? "ep0IN" : "ep0OUT"); 102 - } 103 - 104 - /** 105 - * Debug a transfer ring. 106 - * 107 - * Prints out all TRBs in the endpoint ring, even those after the Link TRB. 108 - *. 109 - */ 110 - static inline char *cdns3_dbg_ring(struct cdns3_endpoint *priv_ep, 111 - struct cdns3_trb *ring, char *str) 112 - { 113 - dma_addr_t addr = priv_ep->trb_pool_dma; 114 - struct cdns3_trb *trb; 115 - int trb_per_sector; 116 - int ret = 0; 117 - int i; 118 - 119 - trb_per_sector = GET_TRBS_PER_SEGMENT(priv_ep->type); 120 - 121 - trb = &priv_ep->trb_pool[priv_ep->dequeue]; 122 - ret += sprintf(str + ret, "\n\t\tRing contents for %s:", priv_ep->name); 123 - 124 - ret += sprintf(str + ret, 125 - "\n\t\tRing deq index: %d, trb: %p (virt), 0x%llx (dma)\n", 126 - priv_ep->dequeue, trb, 127 - (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb)); 128 - 129 - trb = &priv_ep->trb_pool[priv_ep->enqueue]; 130 - ret += sprintf(str + ret, 131 - "\t\tRing enq index: %d, trb: %p (virt), 0x%llx (dma)\n", 132 - priv_ep->enqueue, trb, 133 - (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb)); 134 - 135 - ret += sprintf(str + ret, 136 - "\t\tfree trbs: %d, CCS=%d, PCS=%d\n", 137 - priv_ep->free_trbs, priv_ep->ccs, priv_ep->pcs); 138 - 139 - if (trb_per_sector > TRBS_PER_SEGMENT) 140 - trb_per_sector = TRBS_PER_SEGMENT; 141 - 142 - if (trb_per_sector > TRBS_PER_SEGMENT) { 143 - sprintf(str + ret, "\t\tTo big transfer ring %d\n", 144 - trb_per_sector); 145 - return str; 146 - } 147 - 148 - for (i = 0; i < trb_per_sector; ++i) { 149 - trb = &ring[i]; 150 - ret += sprintf(str + ret, 151 - "\t\t@%pad %08x %08x %08x\n", &addr, 152 - le32_to_cpu(trb->buffer), 153 - le32_to_cpu(trb->length), 154 - le32_to_cpu(trb->control)); 155 - addr += sizeof(*trb); 156 - } 157 - 158 - return str; 159 - } 160 - 161 - void cdns3_dbg(struct cdns3_device *priv_dev, const char *fmt, ...); 162 - 163 - #ifdef CONFIG_DEBUG_FS 164 - void cdns3_debugfs_init(struct cdns3 *cdns); 165 - void cdns3_debugfs_exit(struct cdns3 *cdns); 166 - #else 167 - void cdns3_debugfs_init(struct cdns3 *cdns); 168 - { } 169 - void cdns3_debugfs_exit(struct cdns3 *cdns); 170 - { } 171 - #endif 172 - 173 - #endif /*__LINUX_CDNS3_DEBUG*/
-153
drivers/usb/cdns3/debugfs.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Cadence USBSS DRD Controller DebugFS filer. 4 - * 5 - * Copyright (C) 2018-2019 Cadence. 6 - * 7 - * Author: Pawel Laszczak <pawell@cadence.com> 8 - */ 9 - 10 - #include <linux/types.h> 11 - #include <linux/debugfs.h> 12 - #include <linux/seq_file.h> 13 - #include <linux/uaccess.h> 14 - 15 - #include "core.h" 16 - #include "gadget.h" 17 - #include "drd.h" 18 - 19 - static const char *const cdns3_mode[] = { 20 - [USB_DR_MODE_UNKNOWN] = "unknown", 21 - [USB_DR_MODE_OTG] = "otg", 22 - [USB_DR_MODE_HOST] = "host", 23 - [USB_DR_MODE_PERIPHERAL] = "device", 24 - }; 25 - 26 - static int cdns3_mode_show(struct seq_file *s, void *unused) 27 - { 28 - struct cdns3 *cdns = s->private; 29 - 30 - seq_puts(s, cdns3_mode[cdns->current_dr_mode]); 31 - 32 - return 0; 33 - } 34 - 35 - static int cdns3_mode_open(struct inode *inode, struct file *file) 36 - { 37 - return single_open(file, cdns3_mode_show, inode->i_private); 38 - } 39 - 40 - static ssize_t cdns3_mode_write(struct file *file, 41 - const char __user *ubuf, 42 - size_t count, loff_t *ppos) 43 - { 44 - struct seq_file *s = file->private_data; 45 - struct cdns3 *cdns = s->private; 46 - char buf[32]; 47 - int ret; 48 - 49 - if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) 50 - return -EFAULT; 51 - 52 - if (cdns->debug_disable) { 53 - dev_err(cdns->dev, 54 - "Mode can't be changed when disable is set\n"); 55 - return -EPERM; 56 - } 57 - 58 - ret = match_string(cdns3_mode, ARRAY_SIZE(cdns3_mode), buf); 59 - if (ret < 0 || ret == USB_DR_MODE_UNKNOWN) { 60 - dev_err(cdns->dev, "Failed: incorrect mode setting\n"); 61 - return -EINVAL; 62 - } 63 - 64 - if (cdns->current_dr_mode != ret) { 65 - cdns->desired_dr_mode = ret; 66 - cdns3_role_stop(cdns); 67 - ret = cdns3_drd_update_mode(cdns); 68 - if (ret) 69 - return ret; 70 - 71 - queue_work(system_freezable_wq, &cdns->role_switch_wq); 72 - } 73 - 74 - return count; 75 - } 76 - 77 - static const struct file_operations cdns3_mode_fops = { 78 - .open = cdns3_mode_open, 79 - .write = cdns3_mode_write, 80 - .read = seq_read, 81 - .llseek = seq_lseek, 82 - .release = single_release, 83 - }; 84 - 85 - static int cdns3_disable_show(struct seq_file *s, void *unused) 86 - { 87 - struct cdns3 *cdns = s->private; 88 - 89 - if (!cdns->debug_disable) 90 - seq_puts(s, "0\n"); 91 - else 92 - seq_puts(s, "1\n"); 93 - 94 - return 0; 95 - } 96 - 97 - static ssize_t cdns3_disable_write(struct file *file, 98 - const char __user *ubuf, 99 - size_t count, loff_t *ppos) 100 - { 101 - struct seq_file *s = file->private_data; 102 - struct cdns3 *cdns = s->private; 103 - bool disable; 104 - char buf[16]; 105 - 106 - if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) 107 - return -EFAULT; 108 - 109 - if (kstrtobool(buf, &disable)) { 110 - dev_err(cdns->dev, "wrong setting\n"); 111 - return -EINVAL; 112 - } 113 - 114 - if (disable != cdns->debug_disable) { 115 - cdns->debug_disable = disable; 116 - queue_work(system_freezable_wq, &cdns->role_switch_wq); 117 - } 118 - 119 - return count; 120 - } 121 - 122 - static int cdns3_disable_open(struct inode *inode, struct file *file) 123 - { 124 - return single_open(file, cdns3_disable_show, inode->i_private); 125 - } 126 - 127 - static const struct file_operations cdns3_disable_fops = { 128 - .open = cdns3_disable_open, 129 - .write = cdns3_disable_write, 130 - .read = seq_read, 131 - .llseek = seq_lseek, 132 - .release = single_release, 133 - }; 134 - 135 - void cdns3_debugfs_init(struct cdns3 *cdns) 136 - { 137 - struct dentry *root; 138 - 139 - root = debugfs_create_dir(dev_name(cdns->dev), NULL); 140 - cdns->root = root; 141 - if (IS_ENABLED(CONFIG_USB_CDNS3_GADGET) && 142 - IS_ENABLED(CONFIG_USB_CDNS3_HOST)) 143 - debugfs_create_file("mode", 0644, root, cdns, 144 - &cdns3_mode_fops); 145 - 146 - debugfs_create_file("disable", 0644, root, cdns, 147 - &cdns3_disable_fops); 148 - } 149 - 150 - void cdns3_debugfs_exit(struct cdns3 *cdns) 151 - { 152 - debugfs_remove_recursive(cdns->root); 153 - }
-379
drivers/usb/cdns3/drd.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Cadence USBSS DRD Driver. 4 - * 5 - * Copyright (C) 2018-2019 Cadence. 6 - * Copyright (C) 2019 Texas Instruments 7 - * 8 - * Author: Pawel Laszczak <pawell@cadence.com> 9 - * Roger Quadros <rogerq@ti.com> 10 - * 11 - * 12 - */ 13 - #include <linux/kernel.h> 14 - #include <linux/interrupt.h> 15 - #include <linux/delay.h> 16 - #include <linux/usb/otg.h> 17 - 18 - #include "gadget.h" 19 - #include "drd.h" 20 - #include "core.h" 21 - 22 - /** 23 - * cdns3_set_mode - change mode of OTG Core 24 - * @cdns: pointer to context structure 25 - * @mode: selected mode from cdns_role 26 - * 27 - * Returns 0 on success otherwise negative errno 28 - */ 29 - int cdns3_set_mode(struct cdns3 *cdns, enum usb_dr_mode mode) 30 - { 31 - int ret = 0; 32 - u32 reg; 33 - 34 - cdns->current_dr_mode = mode; 35 - 36 - switch (mode) { 37 - case USB_DR_MODE_PERIPHERAL: 38 - break; 39 - case USB_DR_MODE_HOST: 40 - break; 41 - case USB_DR_MODE_OTG: 42 - dev_dbg(cdns->dev, "Set controller to OTG mode\n"); 43 - if (cdns->version == CDNS3_CONTROLLER_V1) { 44 - reg = readl(&cdns->otg_v1_regs->override); 45 - reg |= OVERRIDE_IDPULLUP; 46 - writel(reg, &cdns->otg_v1_regs->override); 47 - } else { 48 - reg = readl(&cdns->otg_v0_regs->ctrl1); 49 - reg |= OVERRIDE_IDPULLUP_V0; 50 - writel(reg, &cdns->otg_v0_regs->ctrl1); 51 - } 52 - 53 - /* 54 - * Hardware specification says: "ID_VALUE must be valid within 55 - * 50ms after idpullup is set to '1" so driver must wait 56 - * 50ms before reading this pin. 57 - */ 58 - usleep_range(50000, 60000); 59 - break; 60 - default: 61 - cdns->current_dr_mode = USB_DR_MODE_UNKNOWN; 62 - dev_err(cdns->dev, "Unsupported mode of operation %d\n", mode); 63 - return -EINVAL; 64 - } 65 - 66 - return ret; 67 - } 68 - 69 - int cdns3_get_id(struct cdns3 *cdns) 70 - { 71 - int id; 72 - 73 - id = readl(&cdns->otg_regs->sts) & OTGSTS_ID_VALUE; 74 - dev_dbg(cdns->dev, "OTG ID: %d", id); 75 - 76 - return id; 77 - } 78 - 79 - int cdns3_get_vbus(struct cdns3 *cdns) 80 - { 81 - int vbus; 82 - 83 - vbus = !!(readl(&cdns->otg_regs->sts) & OTGSTS_VBUS_VALID); 84 - dev_dbg(cdns->dev, "OTG VBUS: %d", vbus); 85 - return vbus; 86 - } 87 - 88 - int cdns3_is_host(struct cdns3 *cdns) 89 - { 90 - if (cdns->current_dr_mode == USB_DR_MODE_HOST) 91 - return 1; 92 - else if (!cdns3_get_id(cdns)) 93 - return 1; 94 - 95 - return 0; 96 - } 97 - 98 - int cdns3_is_device(struct cdns3 *cdns) 99 - { 100 - if (cdns->current_dr_mode == USB_DR_MODE_PERIPHERAL) 101 - return 1; 102 - else if (cdns->current_dr_mode == USB_DR_MODE_OTG) 103 - if (cdns3_get_id(cdns)) 104 - return 1; 105 - 106 - return 0; 107 - } 108 - 109 - /** 110 - * cdns3_otg_disable_irq - Disable all OTG interrupts 111 - * @cdns: Pointer to controller context structure 112 - */ 113 - static void cdns3_otg_disable_irq(struct cdns3 *cdns) 114 - { 115 - writel(0, &cdns->otg_regs->ien); 116 - } 117 - 118 - /** 119 - * cdns3_otg_enable_irq - enable id and sess_valid interrupts 120 - * @cdns: Pointer to controller context structure 121 - */ 122 - static void cdns3_otg_enable_irq(struct cdns3 *cdns) 123 - { 124 - writel(OTGIEN_ID_CHANGE_INT | OTGIEN_VBUSVALID_RISE_INT | 125 - OTGIEN_VBUSVALID_FALL_INT, &cdns->otg_regs->ien); 126 - } 127 - 128 - /** 129 - * cdns3_drd_switch_host - start/stop host 130 - * @cdns: Pointer to controller context structure 131 - * @on: 1 for start, 0 for stop 132 - * 133 - * Returns 0 on success otherwise negative errno 134 - */ 135 - int cdns3_drd_switch_host(struct cdns3 *cdns, int on) 136 - { 137 - int ret; 138 - u32 reg = OTGCMD_OTG_DIS; 139 - 140 - /* switch OTG core */ 141 - if (on) { 142 - writel(OTGCMD_HOST_BUS_REQ | reg, &cdns->otg_regs->cmd); 143 - 144 - dev_dbg(cdns->dev, "Waiting till Host mode is turned on\n"); 145 - ret = cdns3_handshake(&cdns->otg_regs->sts, OTGSTS_XHCI_READY, 146 - OTGSTS_XHCI_READY, 100000); 147 - 148 - if (ret) { 149 - dev_err(cdns->dev, "timeout waiting for xhci_ready\n"); 150 - return ret; 151 - } 152 - } else { 153 - writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP | 154 - OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF, 155 - &cdns->otg_regs->cmd); 156 - /* Waiting till H_IDLE state.*/ 157 - cdns3_handshake(&cdns->otg_regs->state, 158 - OTGSTATE_HOST_STATE_MASK, 159 - 0, 2000000); 160 - } 161 - 162 - return 0; 163 - } 164 - 165 - /** 166 - * cdns3_drd_switch_gadget - start/stop gadget 167 - * @cdns: Pointer to controller context structure 168 - * @on: 1 for start, 0 for stop 169 - * 170 - * Returns 0 on success otherwise negative errno 171 - */ 172 - int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on) 173 - { 174 - int ret; 175 - u32 reg = OTGCMD_OTG_DIS; 176 - 177 - /* switch OTG core */ 178 - if (on) { 179 - writel(OTGCMD_DEV_BUS_REQ | reg, &cdns->otg_regs->cmd); 180 - 181 - dev_dbg(cdns->dev, "Waiting till Device mode is turned on\n"); 182 - 183 - ret = cdns3_handshake(&cdns->otg_regs->sts, OTGSTS_DEV_READY, 184 - OTGSTS_DEV_READY, 100000); 185 - 186 - if (ret) { 187 - dev_err(cdns->dev, "timeout waiting for dev_ready\n"); 188 - return ret; 189 - } 190 - } else { 191 - /* 192 - * driver should wait at least 10us after disabling Device 193 - * before turning-off Device (DEV_BUS_DROP) 194 - */ 195 - usleep_range(20, 30); 196 - writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP | 197 - OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF, 198 - &cdns->otg_regs->cmd); 199 - /* Waiting till DEV_IDLE state.*/ 200 - cdns3_handshake(&cdns->otg_regs->state, OTGSTATE_DEV_STATE_MASK, 201 - 0, 2000000); 202 - } 203 - 204 - return 0; 205 - } 206 - 207 - /** 208 - * cdns3_init_otg_mode - initialize drd controller 209 - * @cdns: Pointer to controller context structure 210 - * 211 - * Returns 0 on success otherwise negative errno 212 - */ 213 - static int cdns3_init_otg_mode(struct cdns3 *cdns) 214 - { 215 - int ret = 0; 216 - 217 - cdns3_otg_disable_irq(cdns); 218 - /* clear all interrupts */ 219 - writel(~0, &cdns->otg_regs->ivect); 220 - 221 - ret = cdns3_set_mode(cdns, USB_DR_MODE_OTG); 222 - if (ret) 223 - return ret; 224 - 225 - cdns3_otg_enable_irq(cdns); 226 - return ret; 227 - } 228 - 229 - /** 230 - * cdns3_drd_update_mode - initialize mode of operation 231 - * @cdns: Pointer to controller context structure 232 - * 233 - * Returns 0 on success otherwise negative errno 234 - */ 235 - int cdns3_drd_update_mode(struct cdns3 *cdns) 236 - { 237 - int ret = 0; 238 - 239 - if (cdns->desired_dr_mode == cdns->current_dr_mode) 240 - return ret; 241 - 242 - switch (cdns->desired_dr_mode) { 243 - case USB_DR_MODE_PERIPHERAL: 244 - ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL); 245 - break; 246 - case USB_DR_MODE_HOST: 247 - ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST); 248 - break; 249 - case USB_DR_MODE_OTG: 250 - ret = cdns3_init_otg_mode(cdns); 251 - break; 252 - default: 253 - dev_err(cdns->dev, "Unsupported mode of operation %d\n", 254 - cdns->dr_mode); 255 - return -EINVAL; 256 - } 257 - 258 - return ret; 259 - } 260 - 261 - /** 262 - * cdns3_drd_irq - interrupt handler for OTG events 263 - * 264 - * @irq: irq number for cdns3 core device 265 - * @data: structure of cdns3 266 - * 267 - * Returns IRQ_HANDLED or IRQ_NONE 268 - */ 269 - static irqreturn_t cdns3_drd_irq(int irq, void *data) 270 - { 271 - irqreturn_t ret = IRQ_NONE; 272 - struct cdns3 *cdns = data; 273 - u32 reg; 274 - 275 - if (cdns->dr_mode != USB_DR_MODE_OTG) 276 - return ret; 277 - 278 - reg = readl(&cdns->otg_regs->ivect); 279 - 280 - if (!reg) 281 - return ret; 282 - 283 - if (reg & OTGIEN_ID_CHANGE_INT) { 284 - dev_dbg(cdns->dev, "OTG IRQ: new ID: %d\n", 285 - cdns3_get_id(cdns)); 286 - 287 - ret = IRQ_HANDLED; 288 - } 289 - 290 - if (reg & (OTGIEN_VBUSVALID_RISE_INT | OTGIEN_VBUSVALID_FALL_INT)) { 291 - dev_dbg(cdns->dev, "OTG IRQ: new VBUS: %d\n", 292 - cdns3_get_vbus(cdns)); 293 - 294 - ret = IRQ_HANDLED; 295 - } 296 - 297 - if (ret == IRQ_HANDLED) 298 - queue_work(system_freezable_wq, &cdns->role_switch_wq); 299 - 300 - writel(~0, &cdns->otg_regs->ivect); 301 - return ret; 302 - } 303 - 304 - int cdns3_drd_init(struct cdns3 *cdns) 305 - { 306 - void __iomem *regs; 307 - int ret = 0; 308 - u32 state; 309 - 310 - regs = devm_ioremap_resource(cdns->dev, &cdns->otg_res); 311 - if (IS_ERR(regs)) 312 - return PTR_ERR(regs); 313 - 314 - /* Detection of DRD version. Controller has been released 315 - * in two versions. Both are similar, but they have same changes 316 - * in register maps. 317 - * The first register in old version is command register and it's read 318 - * only, so driver should read 0 from it. On the other hand, in v1 319 - * the first register contains device ID number which is not set to 0. 320 - * Driver uses this fact to detect the proper version of 321 - * controller. 322 - */ 323 - cdns->otg_v0_regs = regs; 324 - if (!readl(&cdns->otg_v0_regs->cmd)) { 325 - cdns->version = CDNS3_CONTROLLER_V0; 326 - cdns->otg_v1_regs = NULL; 327 - cdns->otg_regs = regs; 328 - writel(1, &cdns->otg_v0_regs->simulate); 329 - dev_info(cdns->dev, "DRD version v0 (%08x)\n", 330 - readl(&cdns->otg_v0_regs->version)); 331 - } else { 332 - cdns->otg_v0_regs = NULL; 333 - cdns->otg_v1_regs = regs; 334 - cdns->otg_regs = (void *)&cdns->otg_v1_regs->cmd; 335 - cdns->version = CDNS3_CONTROLLER_V1; 336 - writel(1, &cdns->otg_v1_regs->simulate); 337 - dev_info(cdns->dev, "DRD version v1 (ID: %08x, rev: %08x)\n", 338 - readl(&cdns->otg_v1_regs->did), 339 - readl(&cdns->otg_v1_regs->rid)); 340 - } 341 - 342 - state = OTGSTS_STRAP(readl(&cdns->otg_regs->sts)); 343 - 344 - /* Update dr_mode according to STRAP configuration. */ 345 - cdns->dr_mode = USB_DR_MODE_OTG; 346 - if (state == OTGSTS_STRAP_HOST) { 347 - dev_dbg(cdns->dev, "Controller strapped to HOST\n"); 348 - cdns->dr_mode = USB_DR_MODE_HOST; 349 - } else if (state == OTGSTS_STRAP_GADGET) { 350 - dev_dbg(cdns->dev, "Controller strapped to PERIPHERAL\n"); 351 - cdns->dr_mode = USB_DR_MODE_PERIPHERAL; 352 - } 353 - 354 - cdns->desired_dr_mode = cdns->dr_mode; 355 - cdns->current_dr_mode = USB_DR_MODE_UNKNOWN; 356 - 357 - ret = devm_request_threaded_irq(cdns->dev, cdns->otg_irq, 358 - cdns3_drd_irq, 359 - NULL, IRQF_SHARED, 360 - dev_name(cdns->dev), cdns); 361 - 362 - if (ret) { 363 - dev_err(cdns->dev, "couldn't get otg_irq\n"); 364 - return ret; 365 - } 366 - 367 - state = readl(&cdns->otg_regs->sts); 368 - if (OTGSTS_OTG_NRDY(state) != 0) { 369 - dev_err(cdns->dev, "Cadence USB3 OTG device not ready\n"); 370 - return -ENODEV; 371 - } 372 - 373 - return ret; 374 - } 375 - 376 - int cdns3_drd_exit(struct cdns3 *cdns) 377 - { 378 - return 0; 379 - }
-166
drivers/usb/cdns3/drd.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * Cadence USB3 DRD header file. 4 - * 5 - * Copyright (C) 2018-2019 Cadence. 6 - * 7 - * Author: Pawel Laszczak <pawell@cadence.com> 8 - */ 9 - #ifndef __LINUX_CDNS3_DRD 10 - #define __LINUX_CDNS3_DRD 11 - 12 - #include <linux/usb/otg.h> 13 - #include <linux/phy/phy.h> 14 - #include "core.h" 15 - 16 - /* DRD register interface for version v1. */ 17 - struct cdns3_otg_regs { 18 - __le32 did; 19 - __le32 rid; 20 - __le32 capabilities; 21 - __le32 reserved1; 22 - __le32 cmd; 23 - __le32 sts; 24 - __le32 state; 25 - __le32 reserved2; 26 - __le32 ien; 27 - __le32 ivect; 28 - __le32 refclk; 29 - __le32 tmr; 30 - __le32 reserved3[4]; 31 - __le32 simulate; 32 - __le32 override; 33 - __le32 susp_ctrl; 34 - __le32 reserved4; 35 - __le32 anasts; 36 - __le32 adp_ramp_time; 37 - __le32 ctrl1; 38 - __le32 ctrl2; 39 - }; 40 - 41 - /* DRD register interface for version v0. */ 42 - struct cdns3_otg_legacy_regs { 43 - __le32 cmd; 44 - __le32 sts; 45 - __le32 state; 46 - __le32 refclk; 47 - __le32 ien; 48 - __le32 ivect; 49 - __le32 reserved1[3]; 50 - __le32 tmr; 51 - __le32 reserved2[2]; 52 - __le32 version; 53 - __le32 capabilities; 54 - __le32 reserved3[2]; 55 - __le32 simulate; 56 - __le32 reserved4[5]; 57 - __le32 ctrl1; 58 - }; 59 - 60 - /* 61 - * Common registers interface for both version of DRD. 62 - */ 63 - struct cdns3_otg_common_regs { 64 - __le32 cmd; 65 - __le32 sts; 66 - __le32 state; 67 - __le32 different1; 68 - __le32 ien; 69 - __le32 ivect; 70 - }; 71 - 72 - /* CDNS_RID - bitmasks */ 73 - #define CDNS_RID(p) ((p) & GENMASK(15, 0)) 74 - 75 - /* CDNS_VID - bitmasks */ 76 - #define CDNS_DID(p) ((p) & GENMASK(31, 0)) 77 - 78 - /* OTGCMD - bitmasks */ 79 - /* "Request the bus for Device mode. */ 80 - #define OTGCMD_DEV_BUS_REQ BIT(0) 81 - /* Request the bus for Host mode */ 82 - #define OTGCMD_HOST_BUS_REQ BIT(1) 83 - /* Enable OTG mode. */ 84 - #define OTGCMD_OTG_EN BIT(2) 85 - /* Disable OTG mode */ 86 - #define OTGCMD_OTG_DIS BIT(3) 87 - /*"Configure OTG as A-Device. */ 88 - #define OTGCMD_A_DEV_EN BIT(4) 89 - /*"Configure OTG as A-Device. */ 90 - #define OTGCMD_A_DEV_DIS BIT(5) 91 - /* Drop the bus for Device mod e. */ 92 - #define OTGCMD_DEV_BUS_DROP BIT(8) 93 - /* Drop the bus for Host mode*/ 94 - #define OTGCMD_HOST_BUS_DROP BIT(9) 95 - /* Power Down USBSS-DEV. */ 96 - #define OTGCMD_DEV_POWER_OFF BIT(11) 97 - /* Power Down CDNSXHCI. */ 98 - #define OTGCMD_HOST_POWER_OFF BIT(12) 99 - 100 - /* OTGIEN - bitmasks */ 101 - /* ID change interrupt enable */ 102 - #define OTGIEN_ID_CHANGE_INT BIT(0) 103 - /* Vbusvalid fall detected interrupt enable.*/ 104 - #define OTGIEN_VBUSVALID_RISE_INT BIT(4) 105 - /* Vbusvalid fall detected interrupt enable */ 106 - #define OTGIEN_VBUSVALID_FALL_INT BIT(5) 107 - 108 - /* OTGSTS - bitmasks */ 109 - /* 110 - * Current value of the ID pin. It is only valid when idpullup in 111 - * OTGCTRL1_TYPE register is set to '1'. 112 - */ 113 - #define OTGSTS_ID_VALUE BIT(0) 114 - /* Current value of the vbus_valid */ 115 - #define OTGSTS_VBUS_VALID BIT(1) 116 - /* Current value of the b_sess_vld */ 117 - #define OTGSTS_SESSION_VALID BIT(2) 118 - /*Device mode is active*/ 119 - #define OTGSTS_DEV_ACTIVE BIT(3) 120 - /* Host mode is active. */ 121 - #define OTGSTS_HOST_ACTIVE BIT(4) 122 - /* OTG Controller not ready. */ 123 - #define OTGSTS_OTG_NRDY_MASK BIT(11) 124 - #define OTGSTS_OTG_NRDY(p) ((p) & OTGSTS_OTG_NRDY_MASK) 125 - /* 126 - * Value of the strap pins. 127 - * 000 - no default configuration 128 - * 010 - Controller initiall configured as Host 129 - * 100 - Controller initially configured as Device 130 - */ 131 - #define OTGSTS_STRAP(p) (((p) & GENMASK(14, 12)) >> 12) 132 - #define OTGSTS_STRAP_NO_DEFAULT_CFG 0x00 133 - #define OTGSTS_STRAP_HOST_OTG 0x01 134 - #define OTGSTS_STRAP_HOST 0x02 135 - #define OTGSTS_STRAP_GADGET 0x04 136 - /* Host mode is turned on. */ 137 - #define OTGSTS_XHCI_READY BIT(26) 138 - /* "Device mode is turned on .*/ 139 - #define OTGSTS_DEV_READY BIT(27) 140 - 141 - /* OTGSTATE- bitmasks */ 142 - #define OTGSTATE_DEV_STATE_MASK GENMASK(2, 0) 143 - #define OTGSTATE_HOST_STATE_MASK GENMASK(5, 3) 144 - #define OTGSTATE_HOST_STATE_IDLE 0x0 145 - #define OTGSTATE_HOST_STATE_VBUS_FALL 0x7 146 - #define OTGSTATE_HOST_STATE(p) (((p) & OTGSTATE_HOST_STATE_MASK) >> 3) 147 - 148 - /* OTGREFCLK - bitmasks */ 149 - #define OTGREFCLK_STB_CLK_SWITCH_EN BIT(31) 150 - 151 - /* OVERRIDE - bitmasks */ 152 - #define OVERRIDE_IDPULLUP BIT(0) 153 - /* Only for CDNS3_CONTROLLER_V0 version */ 154 - #define OVERRIDE_IDPULLUP_V0 BIT(24) 155 - 156 - int cdns3_is_host(struct cdns3 *cdns); 157 - int cdns3_is_device(struct cdns3 *cdns); 158 - int cdns3_get_id(struct cdns3 *cdns); 159 - int cdns3_get_vbus(struct cdns3 *cdns); 160 - int cdns3_drd_init(struct cdns3 *cdns); 161 - int cdns3_drd_exit(struct cdns3 *cdns); 162 - int cdns3_drd_update_mode(struct cdns3 *cdns); 163 - int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on); 164 - int cdns3_drd_switch_host(struct cdns3 *cdns, int on); 165 - 166 - #endif /* __LINUX_CDNS3_DRD */
-920
drivers/usb/cdns3/ep0.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Cadence USBSS DRD Driver - gadget side. 4 - * 5 - * Copyright (C) 2018 Cadence Design Systems. 6 - * Copyright (C) 2017-2018 NXP 7 - * 8 - * Authors: Pawel Jez <pjez@cadence.com>, 9 - * Pawel Laszczak <pawell@cadence.com> 10 - * Peter Chen <peter.chen@nxp.com> 11 - */ 12 - 13 - #include <linux/usb/composite.h> 14 - 15 - #include "gadget.h" 16 - #include "trace.h" 17 - 18 - static struct usb_endpoint_descriptor cdns3_gadget_ep0_desc = { 19 - .bLength = USB_DT_ENDPOINT_SIZE, 20 - .bDescriptorType = USB_DT_ENDPOINT, 21 - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 22 - }; 23 - 24 - /** 25 - * cdns3_ep0_run_transfer - Do transfer on default endpoint hardware 26 - * @priv_dev: extended gadget object 27 - * @dma_addr: physical address where data is/will be stored 28 - * @length: data length 29 - * @erdy: set it to 1 when ERDY packet should be sent - 30 - * exit from flow control state 31 - */ 32 - static void cdns3_ep0_run_transfer(struct cdns3_device *priv_dev, 33 - dma_addr_t dma_addr, 34 - unsigned int length, int erdy, int zlp) 35 - { 36 - struct cdns3_usb_regs __iomem *regs = priv_dev->regs; 37 - struct cdns3_endpoint *priv_ep = priv_dev->eps[0]; 38 - 39 - priv_ep->trb_pool[0].buffer = TRB_BUFFER(dma_addr); 40 - priv_ep->trb_pool[0].length = TRB_LEN(length); 41 - 42 - if (zlp) { 43 - priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_TYPE(TRB_NORMAL); 44 - priv_ep->trb_pool[1].buffer = TRB_BUFFER(dma_addr); 45 - priv_ep->trb_pool[1].length = TRB_LEN(0); 46 - priv_ep->trb_pool[1].control = TRB_CYCLE | TRB_IOC | 47 - TRB_TYPE(TRB_NORMAL); 48 - } else { 49 - priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_IOC | 50 - TRB_TYPE(TRB_NORMAL); 51 - priv_ep->trb_pool[1].control = 0; 52 - } 53 - 54 - trace_cdns3_prepare_trb(priv_ep, priv_ep->trb_pool); 55 - 56 - cdns3_select_ep(priv_dev, priv_dev->ep0_data_dir); 57 - 58 - writel(EP_STS_TRBERR, &regs->ep_sts); 59 - writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma), &regs->ep_traddr); 60 - trace_cdns3_doorbell_ep0(priv_dev->ep0_data_dir ? "ep0in" : "ep0out", 61 - readl(&regs->ep_traddr)); 62 - 63 - /* TRB should be prepared before starting transfer. */ 64 - writel(EP_CMD_DRDY, &regs->ep_cmd); 65 - 66 - /* Resume controller before arming transfer. */ 67 - __cdns3_gadget_wakeup(priv_dev); 68 - 69 - if (erdy) 70 - writel(EP_CMD_ERDY, &priv_dev->regs->ep_cmd); 71 - } 72 - 73 - /** 74 - * cdns3_ep0_delegate_req - Returns status of handling setup packet 75 - * Setup is handled by gadget driver 76 - * @priv_dev: extended gadget object 77 - * @ctrl_req: pointer to received setup packet 78 - * 79 - * Returns zero on success or negative value on failure 80 - */ 81 - static int cdns3_ep0_delegate_req(struct cdns3_device *priv_dev, 82 - struct usb_ctrlrequest *ctrl_req) 83 - { 84 - int ret; 85 - 86 - spin_unlock(&priv_dev->lock); 87 - priv_dev->setup_pending = 1; 88 - ret = priv_dev->gadget_driver->setup(&priv_dev->gadget, ctrl_req); 89 - priv_dev->setup_pending = 0; 90 - spin_lock(&priv_dev->lock); 91 - return ret; 92 - } 93 - 94 - static void cdns3_prepare_setup_packet(struct cdns3_device *priv_dev) 95 - { 96 - priv_dev->ep0_data_dir = 0; 97 - priv_dev->ep0_stage = CDNS3_SETUP_STAGE; 98 - cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma, 99 - sizeof(struct usb_ctrlrequest), 0, 0); 100 - } 101 - 102 - static void cdns3_ep0_complete_setup(struct cdns3_device *priv_dev, 103 - u8 send_stall, u8 send_erdy) 104 - { 105 - struct cdns3_endpoint *priv_ep = priv_dev->eps[0]; 106 - struct usb_request *request; 107 - 108 - request = cdns3_next_request(&priv_ep->pending_req_list); 109 - if (request) 110 - list_del_init(&request->list); 111 - 112 - if (send_stall) { 113 - cdns3_dbg(priv_ep->cdns3_dev, "STALL for ep0\n"); 114 - /* set_stall on ep0 */ 115 - cdns3_select_ep(priv_dev, 0x00); 116 - writel(EP_CMD_SSTALL, &priv_dev->regs->ep_cmd); 117 - } else { 118 - cdns3_prepare_setup_packet(priv_dev); 119 - } 120 - 121 - priv_dev->ep0_stage = CDNS3_SETUP_STAGE; 122 - writel((send_erdy ? EP_CMD_ERDY : 0) | EP_CMD_REQ_CMPL, 123 - &priv_dev->regs->ep_cmd); 124 - 125 - cdns3_allow_enable_l1(priv_dev, 1); 126 - } 127 - 128 - /** 129 - * cdns3_req_ep0_set_configuration - Handling of SET_CONFIG standard USB request 130 - * @priv_dev: extended gadget object 131 - * @ctrl_req: pointer to received setup packet 132 - * 133 - * Returns 0 if success, USB_GADGET_DELAYED_STATUS on deferred status stage, 134 - * error code on error 135 - */ 136 - static int cdns3_req_ep0_set_configuration(struct cdns3_device *priv_dev, 137 - struct usb_ctrlrequest *ctrl_req) 138 - { 139 - enum usb_device_state device_state = priv_dev->gadget.state; 140 - struct cdns3_endpoint *priv_ep; 141 - u32 config = le16_to_cpu(ctrl_req->wValue); 142 - int result = 0; 143 - int i; 144 - 145 - switch (device_state) { 146 - case USB_STATE_ADDRESS: 147 - /* Configure non-control EPs */ 148 - for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) { 149 - priv_ep = priv_dev->eps[i]; 150 - if (!priv_ep) 151 - continue; 152 - 153 - if (priv_ep->flags & EP_CLAIMED) 154 - cdns3_ep_config(priv_ep); 155 - } 156 - 157 - result = cdns3_ep0_delegate_req(priv_dev, ctrl_req); 158 - 159 - if (result) 160 - return result; 161 - 162 - if (config) { 163 - cdns3_set_hw_configuration(priv_dev); 164 - } else { 165 - cdns3_hw_reset_eps_config(priv_dev); 166 - usb_gadget_set_state(&priv_dev->gadget, 167 - USB_STATE_ADDRESS); 168 - } 169 - break; 170 - case USB_STATE_CONFIGURED: 171 - result = cdns3_ep0_delegate_req(priv_dev, ctrl_req); 172 - 173 - if (!config && !result) { 174 - cdns3_hw_reset_eps_config(priv_dev); 175 - usb_gadget_set_state(&priv_dev->gadget, 176 - USB_STATE_ADDRESS); 177 - } 178 - break; 179 - default: 180 - result = -EINVAL; 181 - } 182 - 183 - return result; 184 - } 185 - 186 - /** 187 - * cdns3_req_ep0_set_address - Handling of SET_ADDRESS standard USB request 188 - * @priv_dev: extended gadget object 189 - * @ctrl_req: pointer to received setup packet 190 - * 191 - * Returns 0 if success, error code on error 192 - */ 193 - static int cdns3_req_ep0_set_address(struct cdns3_device *priv_dev, 194 - struct usb_ctrlrequest *ctrl_req) 195 - { 196 - enum usb_device_state device_state = priv_dev->gadget.state; 197 - u32 reg; 198 - u32 addr; 199 - 200 - addr = le16_to_cpu(ctrl_req->wValue); 201 - 202 - if (addr > USB_DEVICE_MAX_ADDRESS) { 203 - dev_err(priv_dev->dev, 204 - "Device address (%d) cannot be greater than %d\n", 205 - addr, USB_DEVICE_MAX_ADDRESS); 206 - return -EINVAL; 207 - } 208 - 209 - if (device_state == USB_STATE_CONFIGURED) { 210 - dev_err(priv_dev->dev, 211 - "can't set_address from configured state\n"); 212 - return -EINVAL; 213 - } 214 - 215 - reg = readl(&priv_dev->regs->usb_cmd); 216 - 217 - writel(reg | USB_CMD_FADDR(addr) | USB_CMD_SET_ADDR, 218 - &priv_dev->regs->usb_cmd); 219 - 220 - usb_gadget_set_state(&priv_dev->gadget, 221 - (addr ? USB_STATE_ADDRESS : USB_STATE_DEFAULT)); 222 - 223 - return 0; 224 - } 225 - 226 - /** 227 - * cdns3_req_ep0_get_status - Handling of GET_STATUS standard USB request 228 - * @priv_dev: extended gadget object 229 - * @ctrl_req: pointer to received setup packet 230 - * 231 - * Returns 0 if success, error code on error 232 - */ 233 - static int cdns3_req_ep0_get_status(struct cdns3_device *priv_dev, 234 - struct usb_ctrlrequest *ctrl) 235 - { 236 - __le16 *response_pkt; 237 - u16 usb_status = 0; 238 - u32 recip; 239 - u32 reg; 240 - 241 - recip = ctrl->bRequestType & USB_RECIP_MASK; 242 - 243 - switch (recip) { 244 - case USB_RECIP_DEVICE: 245 - /* self powered */ 246 - if (priv_dev->is_selfpowered) 247 - usb_status = BIT(USB_DEVICE_SELF_POWERED); 248 - 249 - if (priv_dev->wake_up_flag) 250 - usb_status |= BIT(USB_DEVICE_REMOTE_WAKEUP); 251 - 252 - if (priv_dev->gadget.speed != USB_SPEED_SUPER) 253 - break; 254 - 255 - reg = readl(&priv_dev->regs->usb_sts); 256 - 257 - if (priv_dev->u1_allowed) 258 - usb_status |= BIT(USB_DEV_STAT_U1_ENABLED); 259 - 260 - if (priv_dev->u2_allowed) 261 - usb_status |= BIT(USB_DEV_STAT_U2_ENABLED); 262 - 263 - break; 264 - case USB_RECIP_INTERFACE: 265 - return cdns3_ep0_delegate_req(priv_dev, ctrl); 266 - case USB_RECIP_ENDPOINT: 267 - /* check if endpoint is stalled */ 268 - cdns3_select_ep(priv_dev, ctrl->wIndex); 269 - if (EP_STS_STALL(readl(&priv_dev->regs->ep_sts))) 270 - usb_status = BIT(USB_ENDPOINT_HALT); 271 - break; 272 - default: 273 - return -EINVAL; 274 - } 275 - 276 - response_pkt = (__le16 *)priv_dev->setup_buf; 277 - *response_pkt = cpu_to_le16(usb_status); 278 - 279 - cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma, 280 - sizeof(*response_pkt), 1, 0); 281 - return 0; 282 - } 283 - 284 - static int cdns3_ep0_feature_handle_device(struct cdns3_device *priv_dev, 285 - struct usb_ctrlrequest *ctrl, 286 - int set) 287 - { 288 - enum usb_device_state state; 289 - enum usb_device_speed speed; 290 - int ret = 0; 291 - u32 wValue; 292 - u32 wIndex; 293 - u16 tmode; 294 - 295 - wValue = le16_to_cpu(ctrl->wValue); 296 - wIndex = le16_to_cpu(ctrl->wIndex); 297 - state = priv_dev->gadget.state; 298 - speed = priv_dev->gadget.speed; 299 - 300 - switch (ctrl->wValue) { 301 - case USB_DEVICE_REMOTE_WAKEUP: 302 - priv_dev->wake_up_flag = !!set; 303 - break; 304 - case USB_DEVICE_U1_ENABLE: 305 - if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER) 306 - return -EINVAL; 307 - 308 - priv_dev->u1_allowed = !!set; 309 - break; 310 - case USB_DEVICE_U2_ENABLE: 311 - if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER) 312 - return -EINVAL; 313 - 314 - priv_dev->u2_allowed = !!set; 315 - break; 316 - case USB_DEVICE_LTM_ENABLE: 317 - ret = -EINVAL; 318 - break; 319 - case USB_DEVICE_TEST_MODE: 320 - if (state != USB_STATE_CONFIGURED || speed > USB_SPEED_HIGH) 321 - return -EINVAL; 322 - 323 - tmode = le16_to_cpu(ctrl->wIndex); 324 - 325 - if (!set || (tmode & 0xff) != 0) 326 - return -EINVAL; 327 - 328 - switch (tmode >> 8) { 329 - case TEST_J: 330 - case TEST_K: 331 - case TEST_SE0_NAK: 332 - case TEST_PACKET: 333 - cdns3_ep0_complete_setup(priv_dev, 0, 1); 334 - /** 335 - * Little delay to give the controller some time 336 - * for sending status stage. 337 - * This time should be less then 3ms. 338 - */ 339 - usleep_range(1000, 2000); 340 - cdns3_set_register_bit(&priv_dev->regs->usb_cmd, 341 - USB_CMD_STMODE | 342 - USB_STS_TMODE_SEL(tmode - 1)); 343 - break; 344 - default: 345 - ret = -EINVAL; 346 - } 347 - break; 348 - default: 349 - ret = -EINVAL; 350 - } 351 - 352 - return ret; 353 - } 354 - 355 - static int cdns3_ep0_feature_handle_intf(struct cdns3_device *priv_dev, 356 - struct usb_ctrlrequest *ctrl, 357 - int set) 358 - { 359 - u32 wValue; 360 - int ret = 0; 361 - 362 - wValue = le16_to_cpu(ctrl->wValue); 363 - 364 - switch (wValue) { 365 - case USB_INTRF_FUNC_SUSPEND: 366 - break; 367 - default: 368 - ret = -EINVAL; 369 - } 370 - 371 - return ret; 372 - } 373 - 374 - static int cdns3_ep0_feature_handle_endpoint(struct cdns3_device *priv_dev, 375 - struct usb_ctrlrequest *ctrl, 376 - int set) 377 - { 378 - struct cdns3_endpoint *priv_ep; 379 - int ret = 0; 380 - u8 index; 381 - 382 - if (le16_to_cpu(ctrl->wValue) != USB_ENDPOINT_HALT) 383 - return -EINVAL; 384 - 385 - if (!(ctrl->wIndex & ~USB_DIR_IN)) 386 - return 0; 387 - 388 - index = cdns3_ep_addr_to_index(ctrl->wIndex); 389 - priv_ep = priv_dev->eps[index]; 390 - 391 - cdns3_select_ep(priv_dev, ctrl->wIndex); 392 - 393 - if (set) { 394 - cdns3_dbg(priv_ep->cdns3_dev, "Stall endpoint %s\n", 395 - priv_ep->name); 396 - writel(EP_CMD_SSTALL, &priv_dev->regs->ep_cmd); 397 - priv_ep->flags |= EP_STALL; 398 - } else { 399 - struct usb_request *request; 400 - 401 - if (priv_dev->eps[index]->flags & EP_WEDGE) { 402 - cdns3_select_ep(priv_dev, 0x00); 403 - return 0; 404 - } 405 - 406 - cdns3_dbg(priv_ep->cdns3_dev, "Clear Stalled endpoint %s\n", 407 - priv_ep->name); 408 - 409 - writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd); 410 - 411 - /* wait for EPRST cleared */ 412 - ret = cdns3_handshake(&priv_dev->regs->ep_cmd, 413 - EP_CMD_EPRST, 0, 100); 414 - if (ret) 415 - return -EINVAL; 416 - 417 - priv_ep->flags &= ~EP_STALL; 418 - 419 - request = cdns3_next_request(&priv_ep->pending_req_list); 420 - if (request) { 421 - cdns3_dbg(priv_ep->cdns3_dev, "Resume transfer for %s\n", 422 - priv_ep->name); 423 - 424 - cdns3_rearm_transfer(priv_ep, 1); 425 - } 426 - } 427 - 428 - return ret; 429 - } 430 - 431 - /** 432 - * cdns3_req_ep0_handle_feature - 433 - * Handling of GET/SET_FEATURE standard USB request 434 - * 435 - * @priv_dev: extended gadget object 436 - * @ctrl_req: pointer to received setup packet 437 - * @set: must be set to 1 for SET_FEATURE request 438 - * 439 - * Returns 0 if success, error code on error 440 - */ 441 - static int cdns3_req_ep0_handle_feature(struct cdns3_device *priv_dev, 442 - struct usb_ctrlrequest *ctrl, 443 - int set) 444 - { 445 - int ret = 0; 446 - u32 recip; 447 - 448 - recip = ctrl->bRequestType & USB_RECIP_MASK; 449 - 450 - switch (recip) { 451 - case USB_RECIP_DEVICE: 452 - ret = cdns3_ep0_feature_handle_device(priv_dev, ctrl, set); 453 - break; 454 - case USB_RECIP_INTERFACE: 455 - ret = cdns3_ep0_feature_handle_intf(priv_dev, ctrl, set); 456 - break; 457 - case USB_RECIP_ENDPOINT: 458 - ret = cdns3_ep0_feature_handle_endpoint(priv_dev, ctrl, set); 459 - break; 460 - default: 461 - return -EINVAL; 462 - } 463 - 464 - return ret; 465 - } 466 - 467 - /** 468 - * cdns3_req_ep0_set_sel - Handling of SET_SEL standard USB request 469 - * @priv_dev: extended gadget object 470 - * @ctrl_req: pointer to received setup packet 471 - * 472 - * Returns 0 if success, error code on error 473 - */ 474 - static int cdns3_req_ep0_set_sel(struct cdns3_device *priv_dev, 475 - struct usb_ctrlrequest *ctrl_req) 476 - { 477 - if (priv_dev->gadget.state < USB_STATE_ADDRESS) 478 - return -EINVAL; 479 - 480 - if (ctrl_req->wLength != 6) { 481 - dev_err(priv_dev->dev, "Set SEL should be 6 bytes, got %d\n", 482 - ctrl_req->wLength); 483 - return -EINVAL; 484 - } 485 - 486 - cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma, 6, 1, 0); 487 - return 0; 488 - } 489 - 490 - /** 491 - * cdns3_req_ep0_set_isoch_delay - 492 - * Handling of GET_ISOCH_DELAY standard USB request 493 - * @priv_dev: extended gadget object 494 - * @ctrl_req: pointer to received setup packet 495 - * 496 - * Returns 0 if success, error code on error 497 - */ 498 - static int cdns3_req_ep0_set_isoch_delay(struct cdns3_device *priv_dev, 499 - struct usb_ctrlrequest *ctrl_req) 500 - { 501 - if (ctrl_req->wIndex || ctrl_req->wLength) 502 - return -EINVAL; 503 - 504 - priv_dev->isoch_delay = ctrl_req->wValue; 505 - 506 - return 0; 507 - } 508 - 509 - /** 510 - * cdns3_ep0_standard_request - Handling standard USB requests 511 - * @priv_dev: extended gadget object 512 - * @ctrl_req: pointer to received setup packet 513 - * 514 - * Returns 0 if success, error code on error 515 - */ 516 - static int cdns3_ep0_standard_request(struct cdns3_device *priv_dev, 517 - struct usb_ctrlrequest *ctrl_req) 518 - { 519 - int ret; 520 - 521 - switch (ctrl_req->bRequest) { 522 - case USB_REQ_SET_ADDRESS: 523 - ret = cdns3_req_ep0_set_address(priv_dev, ctrl_req); 524 - break; 525 - case USB_REQ_SET_CONFIGURATION: 526 - ret = cdns3_req_ep0_set_configuration(priv_dev, ctrl_req); 527 - break; 528 - case USB_REQ_GET_STATUS: 529 - ret = cdns3_req_ep0_get_status(priv_dev, ctrl_req); 530 - break; 531 - case USB_REQ_CLEAR_FEATURE: 532 - ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 0); 533 - break; 534 - case USB_REQ_SET_FEATURE: 535 - ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 1); 536 - break; 537 - case USB_REQ_SET_SEL: 538 - ret = cdns3_req_ep0_set_sel(priv_dev, ctrl_req); 539 - break; 540 - case USB_REQ_SET_ISOCH_DELAY: 541 - ret = cdns3_req_ep0_set_isoch_delay(priv_dev, ctrl_req); 542 - break; 543 - default: 544 - ret = cdns3_ep0_delegate_req(priv_dev, ctrl_req); 545 - break; 546 - } 547 - 548 - return ret; 549 - } 550 - 551 - static void __pending_setup_status_handler(struct cdns3_device *priv_dev) 552 - { 553 - struct usb_request *request = priv_dev->pending_status_request; 554 - 555 - if (priv_dev->status_completion_no_call && request && 556 - request->complete) { 557 - request->complete(&priv_dev->eps[0]->endpoint, request); 558 - priv_dev->status_completion_no_call = 0; 559 - } 560 - } 561 - 562 - void cdns3_pending_setup_status_handler(struct work_struct *work) 563 - { 564 - struct cdns3_device *priv_dev = container_of(work, struct cdns3_device, 565 - pending_status_wq); 566 - unsigned long flags; 567 - 568 - spin_lock_irqsave(&priv_dev->lock, flags); 569 - __pending_setup_status_handler(priv_dev); 570 - spin_unlock_irqrestore(&priv_dev->lock, flags); 571 - } 572 - 573 - /** 574 - * cdns3_ep0_setup_phase - Handling setup USB requests 575 - * @priv_dev: extended gadget object 576 - */ 577 - static void cdns3_ep0_setup_phase(struct cdns3_device *priv_dev) 578 - { 579 - struct usb_ctrlrequest *ctrl = priv_dev->setup_buf; 580 - struct cdns3_endpoint *priv_ep = priv_dev->eps[0]; 581 - int result; 582 - 583 - priv_dev->ep0_data_dir = ctrl->bRequestType & USB_DIR_IN; 584 - 585 - trace_cdns3_ctrl_req(ctrl); 586 - 587 - if (!list_empty(&priv_ep->pending_req_list)) { 588 - struct usb_request *request; 589 - 590 - request = cdns3_next_request(&priv_ep->pending_req_list); 591 - priv_ep->dir = priv_dev->ep0_data_dir; 592 - cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), 593 - -ECONNRESET); 594 - } 595 - 596 - if (le16_to_cpu(ctrl->wLength)) 597 - priv_dev->ep0_stage = CDNS3_DATA_STAGE; 598 - else 599 - priv_dev->ep0_stage = CDNS3_STATUS_STAGE; 600 - 601 - if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 602 - result = cdns3_ep0_standard_request(priv_dev, ctrl); 603 - else 604 - result = cdns3_ep0_delegate_req(priv_dev, ctrl); 605 - 606 - if (result == USB_GADGET_DELAYED_STATUS) 607 - return; 608 - 609 - if (result < 0) 610 - cdns3_ep0_complete_setup(priv_dev, 1, 1); 611 - else if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE) 612 - cdns3_ep0_complete_setup(priv_dev, 0, 1); 613 - } 614 - 615 - static void cdns3_transfer_completed(struct cdns3_device *priv_dev) 616 - { 617 - struct cdns3_endpoint *priv_ep = priv_dev->eps[0]; 618 - 619 - if (!list_empty(&priv_ep->pending_req_list)) { 620 - struct usb_request *request; 621 - 622 - trace_cdns3_complete_trb(priv_ep, priv_ep->trb_pool); 623 - request = cdns3_next_request(&priv_ep->pending_req_list); 624 - 625 - request->actual = 626 - TRB_LEN(le32_to_cpu(priv_ep->trb_pool->length)); 627 - 628 - priv_ep->dir = priv_dev->ep0_data_dir; 629 - cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), 0); 630 - } 631 - 632 - cdns3_ep0_complete_setup(priv_dev, 0, 0); 633 - } 634 - 635 - /** 636 - * cdns3_check_new_setup - Check if controller receive new SETUP packet. 637 - * @priv_dev: extended gadget object 638 - * 639 - * The SETUP packet can be kept in on-chip memory or in system memory. 640 - */ 641 - static bool cdns3_check_new_setup(struct cdns3_device *priv_dev) 642 - { 643 - u32 ep_sts_reg; 644 - 645 - cdns3_select_ep(priv_dev, 0 | USB_DIR_OUT); 646 - ep_sts_reg = readl(&priv_dev->regs->ep_sts); 647 - 648 - return !!(ep_sts_reg & (EP_STS_SETUP | EP_STS_STPWAIT)); 649 - } 650 - 651 - /** 652 - * cdns3_check_ep0_interrupt_proceed - Processes interrupt related to endpoint 0 653 - * @priv_dev: extended gadget object 654 - * @dir: USB_DIR_IN for IN direction, USB_DIR_OUT for OUT direction 655 - */ 656 - void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir) 657 - { 658 - u32 ep_sts_reg; 659 - 660 - cdns3_select_ep(priv_dev, dir); 661 - 662 - ep_sts_reg = readl(&priv_dev->regs->ep_sts); 663 - writel(ep_sts_reg, &priv_dev->regs->ep_sts); 664 - 665 - trace_cdns3_ep0_irq(priv_dev, ep_sts_reg); 666 - 667 - __pending_setup_status_handler(priv_dev); 668 - 669 - if (ep_sts_reg & EP_STS_SETUP) 670 - priv_dev->wait_for_setup = 1; 671 - 672 - if (priv_dev->wait_for_setup && ep_sts_reg & EP_STS_IOC) { 673 - priv_dev->wait_for_setup = 0; 674 - cdns3_allow_enable_l1(priv_dev, 0); 675 - cdns3_ep0_setup_phase(priv_dev); 676 - } else if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) { 677 - priv_dev->ep0_data_dir = dir; 678 - cdns3_transfer_completed(priv_dev); 679 - } 680 - 681 - if (ep_sts_reg & EP_STS_DESCMIS) { 682 - if (dir == 0 && !priv_dev->setup_pending) 683 - cdns3_prepare_setup_packet(priv_dev); 684 - } 685 - } 686 - 687 - /** 688 - * cdns3_gadget_ep0_enable 689 - * Function shouldn't be called by gadget driver, 690 - * endpoint 0 is allways active 691 - */ 692 - static int cdns3_gadget_ep0_enable(struct usb_ep *ep, 693 - const struct usb_endpoint_descriptor *desc) 694 - { 695 - return -EINVAL; 696 - } 697 - 698 - /** 699 - * cdns3_gadget_ep0_disable 700 - * Function shouldn't be called by gadget driver, 701 - * endpoint 0 is allways active 702 - */ 703 - static int cdns3_gadget_ep0_disable(struct usb_ep *ep) 704 - { 705 - return -EINVAL; 706 - } 707 - 708 - /** 709 - * cdns3_gadget_ep0_set_halt 710 - * @ep: pointer to endpoint zero object 711 - * @value: 1 for set stall, 0 for clear stall 712 - * 713 - * Returns 0 714 - */ 715 - static int cdns3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 716 - { 717 - /* TODO */ 718 - return 0; 719 - } 720 - 721 - /** 722 - * cdns3_gadget_ep0_queue Transfer data on endpoint zero 723 - * @ep: pointer to endpoint zero object 724 - * @request: pointer to request object 725 - * @gfp_flags: gfp flags 726 - * 727 - * Returns 0 on success, error code elsewhere 728 - */ 729 - static int cdns3_gadget_ep0_queue(struct usb_ep *ep, 730 - struct usb_request *request, 731 - gfp_t gfp_flags) 732 - { 733 - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); 734 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 735 - unsigned long flags; 736 - int erdy_sent = 0; 737 - int ret = 0; 738 - u8 zlp = 0; 739 - 740 - cdns3_dbg(priv_ep->cdns3_dev, "Queue to Ep0%s L: %d\n", 741 - priv_dev->ep0_data_dir ? "IN" : "OUT", 742 - request->length); 743 - 744 - /* cancel the request if controller receive new SETUP packet. */ 745 - if (cdns3_check_new_setup(priv_dev)) 746 - return -ECONNRESET; 747 - 748 - /* send STATUS stage. Should be called only for SET_CONFIGURATION */ 749 - if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE) { 750 - spin_lock_irqsave(&priv_dev->lock, flags); 751 - cdns3_select_ep(priv_dev, 0x00); 752 - 753 - erdy_sent = !priv_dev->hw_configured_flag; 754 - cdns3_set_hw_configuration(priv_dev); 755 - 756 - if (!erdy_sent) 757 - cdns3_ep0_complete_setup(priv_dev, 0, 1); 758 - 759 - cdns3_allow_enable_l1(priv_dev, 1); 760 - 761 - request->actual = 0; 762 - priv_dev->status_completion_no_call = true; 763 - priv_dev->pending_status_request = request; 764 - spin_unlock_irqrestore(&priv_dev->lock, flags); 765 - 766 - /* 767 - * Since there is no completion interrupt for status stage, 768 - * it needs to call ->completion in software after 769 - * ep0_queue is back. 770 - */ 771 - queue_work(system_freezable_wq, &priv_dev->pending_status_wq); 772 - return 0; 773 - } 774 - 775 - spin_lock_irqsave(&priv_dev->lock, flags); 776 - if (!list_empty(&priv_ep->pending_req_list)) { 777 - dev_err(priv_dev->dev, 778 - "can't handle multiple requests for ep0\n"); 779 - spin_unlock_irqrestore(&priv_dev->lock, flags); 780 - return -EBUSY; 781 - } 782 - 783 - ret = usb_gadget_map_request_by_dev(priv_dev->sysdev, request, 784 - priv_dev->ep0_data_dir); 785 - if (ret) { 786 - spin_unlock_irqrestore(&priv_dev->lock, flags); 787 - dev_err(priv_dev->dev, "failed to map request\n"); 788 - return -EINVAL; 789 - } 790 - 791 - request->status = -EINPROGRESS; 792 - list_add_tail(&request->list, &priv_ep->pending_req_list); 793 - 794 - if (request->zero && request->length && 795 - (request->length % ep->maxpacket == 0)) 796 - zlp = 1; 797 - 798 - cdns3_ep0_run_transfer(priv_dev, request->dma, request->length, 1, zlp); 799 - 800 - spin_unlock_irqrestore(&priv_dev->lock, flags); 801 - 802 - return ret; 803 - } 804 - 805 - /** 806 - * cdns3_gadget_ep_set_wedge Set wedge on selected endpoint 807 - * @ep: endpoint object 808 - * 809 - * Returns 0 810 - */ 811 - int cdns3_gadget_ep_set_wedge(struct usb_ep *ep) 812 - { 813 - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); 814 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 815 - 816 - dev_dbg(priv_dev->dev, "Wedge for %s\n", ep->name); 817 - cdns3_gadget_ep_set_halt(ep, 1); 818 - priv_ep->flags |= EP_WEDGE; 819 - 820 - return 0; 821 - } 822 - 823 - const struct usb_ep_ops cdns3_gadget_ep0_ops = { 824 - .enable = cdns3_gadget_ep0_enable, 825 - .disable = cdns3_gadget_ep0_disable, 826 - .alloc_request = cdns3_gadget_ep_alloc_request, 827 - .free_request = cdns3_gadget_ep_free_request, 828 - .queue = cdns3_gadget_ep0_queue, 829 - .dequeue = cdns3_gadget_ep_dequeue, 830 - .set_halt = cdns3_gadget_ep0_set_halt, 831 - .set_wedge = cdns3_gadget_ep_set_wedge, 832 - }; 833 - 834 - /** 835 - * cdns3_ep0_config - Configures default endpoint 836 - * @priv_dev: extended gadget object 837 - * 838 - * Functions sets parameters: maximal packet size and enables interrupts 839 - */ 840 - void cdns3_ep0_config(struct cdns3_device *priv_dev) 841 - { 842 - struct cdns3_usb_regs __iomem *regs; 843 - struct cdns3_endpoint *priv_ep; 844 - u32 max_packet_size = 64; 845 - 846 - regs = priv_dev->regs; 847 - 848 - if (priv_dev->gadget.speed == USB_SPEED_SUPER) 849 - max_packet_size = 512; 850 - 851 - priv_ep = priv_dev->eps[0]; 852 - 853 - if (!list_empty(&priv_ep->pending_req_list)) { 854 - struct usb_request *request; 855 - 856 - request = cdns3_next_request(&priv_ep->pending_req_list); 857 - list_del_init(&request->list); 858 - } 859 - 860 - priv_dev->u1_allowed = 0; 861 - priv_dev->u2_allowed = 0; 862 - 863 - priv_dev->gadget.ep0->maxpacket = max_packet_size; 864 - cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(max_packet_size); 865 - 866 - /* init ep out */ 867 - cdns3_select_ep(priv_dev, USB_DIR_OUT); 868 - 869 - if (priv_dev->dev_ver >= DEV_VER_V3) { 870 - cdns3_set_register_bit(&priv_dev->regs->dtrans, 871 - BIT(0) | BIT(16)); 872 - cdns3_set_register_bit(&priv_dev->regs->tdl_from_trb, 873 - BIT(0) | BIT(16)); 874 - } 875 - 876 - writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size), 877 - &regs->ep_cfg); 878 - 879 - writel(EP_STS_EN_SETUPEN | EP_STS_EN_DESCMISEN | EP_STS_EN_TRBERREN, 880 - &regs->ep_sts_en); 881 - 882 - /* init ep in */ 883 - cdns3_select_ep(priv_dev, USB_DIR_IN); 884 - 885 - writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size), 886 - &regs->ep_cfg); 887 - 888 - writel(EP_STS_EN_SETUPEN | EP_STS_EN_TRBERREN, &regs->ep_sts_en); 889 - 890 - cdns3_set_register_bit(&regs->usb_conf, USB_CONF_U1DS | USB_CONF_U2DS); 891 - } 892 - 893 - /** 894 - * cdns3_init_ep0 Initializes software endpoint 0 of gadget 895 - * @priv_dev: extended gadget object 896 - * @ep_priv: extended endpoint object 897 - * 898 - * Returns 0 on success else error code. 899 - */ 900 - int cdns3_init_ep0(struct cdns3_device *priv_dev, 901 - struct cdns3_endpoint *priv_ep) 902 - { 903 - sprintf(priv_ep->name, "ep0"); 904 - 905 - /* fill linux fields */ 906 - priv_ep->endpoint.ops = &cdns3_gadget_ep0_ops; 907 - priv_ep->endpoint.maxburst = 1; 908 - usb_ep_set_maxpacket_limit(&priv_ep->endpoint, 909 - CDNS3_EP0_MAX_PACKET_LIMIT); 910 - priv_ep->endpoint.address = 0; 911 - priv_ep->endpoint.caps.type_control = 1; 912 - priv_ep->endpoint.caps.dir_in = 1; 913 - priv_ep->endpoint.caps.dir_out = 1; 914 - priv_ep->endpoint.name = priv_ep->name; 915 - priv_ep->endpoint.desc = &cdns3_gadget_ep0_desc; 916 - priv_dev->gadget.ep0 = &priv_ep->endpoint; 917 - priv_ep->type = USB_ENDPOINT_XFER_CONTROL; 918 - 919 - return cdns3_allocate_trb_pool(priv_ep); 920 - }
-28
drivers/usb/cdns3/gadget-export.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * Cadence USBSS DRD Driver - Gadget Export APIs. 4 - * 5 - * Copyright (C) 2017 NXP 6 - * Copyright (C) 2017-2018 NXP 7 - * 8 - * Authors: Peter Chen <peter.chen@nxp.com> 9 - */ 10 - #ifndef __LINUX_CDNS3_GADGET_EXPORT 11 - #define __LINUX_CDNS3_GADGET_EXPORT 12 - 13 - #ifdef CONFIG_USB_CDNS3_GADGET 14 - 15 - int cdns3_gadget_init(struct cdns3 *cdns); 16 - void cdns3_gadget_exit(struct cdns3 *cdns); 17 - #else 18 - 19 - static inline int cdns3_gadget_init(struct cdns3 *cdns) 20 - { 21 - return -ENXIO; 22 - } 23 - 24 - static inline void cdns3_gadget_exit(struct cdns3 *cdns) { } 25 - 26 - #endif 27 - 28 - #endif /* __LINUX_CDNS3_GADGET_EXPORT */
-2319
drivers/usb/cdns3/gadget.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Cadence USBSS DRD Driver - gadget side. 4 - * 5 - * Copyright (C) 2018-2019 Cadence Design Systems. 6 - * Copyright (C) 2017-2018 NXP 7 - * 8 - * Authors: Pawel Jez <pjez@cadence.com>, 9 - * Pawel Laszczak <pawell@cadence.com> 10 - * Peter Chen <peter.chen@nxp.com> 11 - */ 12 - 13 - /* 14 - * Work around 1: 15 - * At some situations, the controller may get stale data address in TRB 16 - * at below sequences: 17 - * 1. Controller read TRB includes data address 18 - * 2. Software updates TRBs includes data address and Cycle bit 19 - * 3. Controller read TRB which includes Cycle bit 20 - * 4. DMA run with stale data address 21 - * 22 - * To fix this problem, driver needs to make the first TRB in TD as invalid. 23 - * After preparing all TRBs driver needs to check the position of DMA and 24 - * if the DMA point to the first just added TRB and doorbell is 1, 25 - * then driver must defer making this TRB as valid. This TRB will be make 26 - * as valid during adding next TRB only if DMA is stopped or at TRBERR 27 - * interrupt. 28 - * 29 - * Issue has been fixed in DEV_VER_V3 version of controller. 30 - * 31 - */ 32 - 33 - #include <linux/dma-mapping.h> 34 - #include <linux/usb/gadget.h> 35 - #include <linux/module.h> 36 - 37 - #include "core.h" 38 - #include "gadget-export.h" 39 - #include "gadget.h" 40 - #include "trace.h" 41 - #include "drd.h" 42 - 43 - static int __cdns3_gadget_ep_queue(struct usb_ep *ep, 44 - struct usb_request *request, 45 - gfp_t gfp_flags); 46 - 47 - /** 48 - * cdns3_set_register_bit - set bit in given register. 49 - * @ptr: address of device controller register to be read and changed 50 - * @mask: bits requested to set 51 - */ 52 - void cdns3_set_register_bit(void __iomem *ptr, u32 mask) 53 - { 54 - mask = readl(ptr) | mask; 55 - writel(mask, ptr); 56 - } 57 - 58 - /** 59 - * cdns3_ep_addr_to_index - Macro converts endpoint address to 60 - * index of endpoint object in cdns3_device.eps[] container 61 - * @ep_addr: endpoint address for which endpoint object is required 62 - * 63 - */ 64 - u8 cdns3_ep_addr_to_index(u8 ep_addr) 65 - { 66 - return (((ep_addr & 0x7F)) + ((ep_addr & USB_DIR_IN) ? 16 : 0)); 67 - } 68 - 69 - static int cdns3_get_dma_pos(struct cdns3_device *priv_dev, 70 - struct cdns3_endpoint *priv_ep) 71 - { 72 - int dma_index; 73 - 74 - dma_index = readl(&priv_dev->regs->ep_traddr) - priv_ep->trb_pool_dma; 75 - 76 - return dma_index / TRB_SIZE; 77 - } 78 - 79 - /** 80 - * cdns3_next_request - returns next request from list 81 - * @list: list containing requests 82 - * 83 - * Returns request or NULL if no requests in list 84 - */ 85 - struct usb_request *cdns3_next_request(struct list_head *list) 86 - { 87 - return list_first_entry_or_null(list, struct usb_request, list); 88 - } 89 - 90 - /** 91 - * cdns3_next_align_buf - returns next buffer from list 92 - * @list: list containing buffers 93 - * 94 - * Returns buffer or NULL if no buffers in list 95 - */ 96 - struct cdns3_aligned_buf *cdns3_next_align_buf(struct list_head *list) 97 - { 98 - return list_first_entry_or_null(list, struct cdns3_aligned_buf, list); 99 - } 100 - 101 - /** 102 - * select_ep - selects endpoint 103 - * @priv_dev: extended gadget object 104 - * @ep: endpoint address 105 - */ 106 - void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep) 107 - { 108 - if (priv_dev->selected_ep == ep) 109 - return; 110 - 111 - priv_dev->selected_ep = ep; 112 - writel(ep, &priv_dev->regs->ep_sel); 113 - } 114 - 115 - dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep, 116 - struct cdns3_trb *trb) 117 - { 118 - u32 offset = (char *)trb - (char *)priv_ep->trb_pool; 119 - 120 - return priv_ep->trb_pool_dma + offset; 121 - } 122 - 123 - int cdns3_ring_size(struct cdns3_endpoint *priv_ep) 124 - { 125 - switch (priv_ep->type) { 126 - case USB_ENDPOINT_XFER_ISOC: 127 - return TRB_ISO_RING_SIZE; 128 - case USB_ENDPOINT_XFER_CONTROL: 129 - return TRB_CTRL_RING_SIZE; 130 - default: 131 - return TRB_RING_SIZE; 132 - } 133 - } 134 - 135 - /** 136 - * cdns3_allocate_trb_pool - Allocates TRB's pool for selected endpoint 137 - * @priv_ep: endpoint object 138 - * 139 - * Function will return 0 on success or -ENOMEM on allocation error 140 - */ 141 - int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep) 142 - { 143 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 144 - int ring_size = cdns3_ring_size(priv_ep); 145 - struct cdns3_trb *link_trb; 146 - 147 - if (!priv_ep->trb_pool) { 148 - priv_ep->trb_pool = dma_alloc_coherent(priv_dev->sysdev, 149 - ring_size, 150 - &priv_ep->trb_pool_dma, 151 - GFP_DMA32 | GFP_ATOMIC); 152 - if (!priv_ep->trb_pool) 153 - return -ENOMEM; 154 - } else { 155 - memset(priv_ep->trb_pool, 0, ring_size); 156 - } 157 - 158 - if (!priv_ep->num) 159 - return 0; 160 - 161 - priv_ep->num_trbs = ring_size / TRB_SIZE; 162 - /* Initialize the last TRB as Link TRB */ 163 - link_trb = (priv_ep->trb_pool + (priv_ep->num_trbs - 1)); 164 - link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma); 165 - link_trb->control = TRB_CYCLE | TRB_TYPE(TRB_LINK) | TRB_TOGGLE; 166 - 167 - return 0; 168 - } 169 - 170 - static void cdns3_free_trb_pool(struct cdns3_endpoint *priv_ep) 171 - { 172 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 173 - 174 - if (priv_ep->trb_pool) { 175 - dma_free_coherent(priv_dev->sysdev, 176 - cdns3_ring_size(priv_ep), 177 - priv_ep->trb_pool, priv_ep->trb_pool_dma); 178 - priv_ep->trb_pool = NULL; 179 - } 180 - } 181 - 182 - /** 183 - * cdns3_ep_stall_flush - Stalls and flushes selected endpoint 184 - * @priv_ep: endpoint object 185 - * 186 - * Endpoint must be selected before call to this function 187 - */ 188 - static void cdns3_ep_stall_flush(struct cdns3_endpoint *priv_ep) 189 - { 190 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 191 - 192 - cdns3_dbg(priv_ep->cdns3_dev, "Stall & flush endpoint %s\n", 193 - priv_ep->name); 194 - 195 - writel(EP_CMD_DFLUSH | EP_CMD_ERDY | EP_CMD_SSTALL, 196 - &priv_dev->regs->ep_cmd); 197 - 198 - /* wait for DFLUSH cleared */ 199 - cdns3_handshake(&priv_dev->regs->ep_cmd, EP_CMD_DFLUSH, 0, 1000); 200 - priv_ep->flags |= EP_STALL; 201 - } 202 - 203 - /** 204 - * cdns3_hw_reset_eps_config - reset endpoints configuration kept by controller. 205 - * @priv_dev: extended gadget object 206 - */ 207 - void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev) 208 - { 209 - writel(USB_CONF_CFGRST, &priv_dev->regs->usb_conf); 210 - 211 - cdns3_allow_enable_l1(priv_dev, 0); 212 - priv_dev->hw_configured_flag = 0; 213 - priv_dev->onchip_used_size = 0; 214 - priv_dev->out_mem_is_allocated = 0; 215 - priv_dev->wait_for_setup = 0; 216 - } 217 - 218 - /** 219 - * cdns3_ep_inc_trb - increment a trb index. 220 - * @index: Pointer to the TRB index to increment. 221 - * @cs: Cycle state 222 - * @trb_in_seg: number of TRBs in segment 223 - * 224 - * The index should never point to the link TRB. After incrementing, 225 - * if it is point to the link TRB, wrap around to the beginning and revert 226 - * cycle state bit The 227 - * link TRB is always at the last TRB entry. 228 - */ 229 - static void cdns3_ep_inc_trb(int *index, u8 *cs, int trb_in_seg) 230 - { 231 - (*index)++; 232 - if (*index == (trb_in_seg - 1)) { 233 - *index = 0; 234 - *cs ^= 1; 235 - } 236 - } 237 - 238 - /** 239 - * cdns3_ep_inc_enq - increment endpoint's enqueue pointer 240 - * @priv_ep: The endpoint whose enqueue pointer we're incrementing 241 - */ 242 - static void cdns3_ep_inc_enq(struct cdns3_endpoint *priv_ep) 243 - { 244 - priv_ep->free_trbs--; 245 - cdns3_ep_inc_trb(&priv_ep->enqueue, &priv_ep->pcs, priv_ep->num_trbs); 246 - } 247 - 248 - /** 249 - * cdns3_ep_inc_deq - increment endpoint's dequeue pointer 250 - * @priv_ep: The endpoint whose dequeue pointer we're incrementing 251 - */ 252 - static void cdns3_ep_inc_deq(struct cdns3_endpoint *priv_ep) 253 - { 254 - priv_ep->free_trbs++; 255 - cdns3_ep_inc_trb(&priv_ep->dequeue, &priv_ep->ccs, priv_ep->num_trbs); 256 - } 257 - 258 - void cdns3_move_deq_to_next_trb(struct cdns3_request *priv_req) 259 - { 260 - struct cdns3_endpoint *priv_ep = priv_req->priv_ep; 261 - int current_trb = priv_req->start_trb; 262 - 263 - while (current_trb != priv_req->end_trb) { 264 - cdns3_ep_inc_deq(priv_ep); 265 - current_trb = priv_ep->dequeue; 266 - } 267 - 268 - cdns3_ep_inc_deq(priv_ep); 269 - } 270 - 271 - /** 272 - * cdns3_allow_enable_l1 - enable/disable permits to transition to L1. 273 - * @priv_dev: Extended gadget object 274 - * @enable: Enable/disable permit to transition to L1. 275 - * 276 - * If bit USB_CONF_L1EN is set and device receive Extended Token packet, 277 - * then controller answer with ACK handshake. 278 - * If bit USB_CONF_L1DS is set and device receive Extended Token packet, 279 - * then controller answer with NYET handshake. 280 - */ 281 - void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable) 282 - { 283 - if (enable) 284 - writel(USB_CONF_L1EN, &priv_dev->regs->usb_conf); 285 - else 286 - writel(USB_CONF_L1DS, &priv_dev->regs->usb_conf); 287 - } 288 - 289 - enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev) 290 - { 291 - u32 reg; 292 - 293 - reg = readl(&priv_dev->regs->usb_sts); 294 - 295 - if (DEV_SUPERSPEED(reg)) 296 - return USB_SPEED_SUPER; 297 - else if (DEV_HIGHSPEED(reg)) 298 - return USB_SPEED_HIGH; 299 - else if (DEV_FULLSPEED(reg)) 300 - return USB_SPEED_FULL; 301 - else if (DEV_LOWSPEED(reg)) 302 - return USB_SPEED_LOW; 303 - return USB_SPEED_UNKNOWN; 304 - } 305 - 306 - /** 307 - * cdns3_start_all_request - add to ring all request not started 308 - * @priv_dev: Extended gadget object 309 - * @priv_ep: The endpoint for whom request will be started. 310 - * 311 - * Returns return ENOMEM if transfer ring i not enough TRBs to start 312 - * all requests. 313 - */ 314 - static int cdns3_start_all_request(struct cdns3_device *priv_dev, 315 - struct cdns3_endpoint *priv_ep) 316 - { 317 - struct cdns3_request *priv_req; 318 - struct usb_request *request; 319 - int ret = 0; 320 - 321 - while (!list_empty(&priv_ep->deferred_req_list)) { 322 - request = cdns3_next_request(&priv_ep->deferred_req_list); 323 - priv_req = to_cdns3_request(request); 324 - 325 - ret = cdns3_ep_run_transfer(priv_ep, request); 326 - if (ret) 327 - return ret; 328 - 329 - list_del(&request->list); 330 - list_add_tail(&request->list, 331 - &priv_ep->pending_req_list); 332 - } 333 - 334 - priv_ep->flags &= ~EP_RING_FULL; 335 - return ret; 336 - } 337 - 338 - /** 339 - * cdns3_gadget_giveback - call struct usb_request's ->complete callback 340 - * @priv_ep: The endpoint to whom the request belongs to 341 - * @priv_req: The request we're giving back 342 - * @status: completion code for the request 343 - * 344 - * Must be called with controller's lock held and interrupts disabled. This 345 - * function will unmap @req and call its ->complete() callback to notify upper 346 - * layers that it has completed. 347 - */ 348 - void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep, 349 - struct cdns3_request *priv_req, 350 - int status) 351 - { 352 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 353 - struct usb_request *request = &priv_req->request; 354 - 355 - list_del_init(&request->list); 356 - 357 - if (request->status == -EINPROGRESS) 358 - request->status = status; 359 - 360 - usb_gadget_unmap_request_by_dev(priv_dev->sysdev, request, 361 - priv_ep->dir); 362 - 363 - if ((priv_req->flags & REQUEST_UNALIGNED) && 364 - priv_ep->dir == USB_DIR_OUT && !request->status) 365 - memcpy(request->buf, priv_req->aligned_buf->buf, 366 - request->length); 367 - 368 - priv_req->flags &= ~(REQUEST_PENDING | REQUEST_UNALIGNED); 369 - trace_cdns3_gadget_giveback(priv_req); 370 - 371 - if (request->complete) { 372 - spin_unlock(&priv_dev->lock); 373 - usb_gadget_giveback_request(&priv_ep->endpoint, 374 - request); 375 - spin_lock(&priv_dev->lock); 376 - } 377 - 378 - if (request->buf == priv_dev->zlp_buf) 379 - cdns3_gadget_ep_free_request(&priv_ep->endpoint, request); 380 - } 381 - 382 - void cdns3_wa1_restore_cycle_bit(struct cdns3_endpoint *priv_ep) 383 - { 384 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 385 - 386 - /* Work around for stale data address in TRB*/ 387 - if (priv_ep->wa1_set) { 388 - cdns3_dbg(priv_dev, "WA1: update cycle bit\n"); 389 - priv_ep->wa1_set = 0; 390 - priv_ep->wa1_trb_index = 0xFFFF; 391 - if (priv_ep->wa1_cycle_bit) { 392 - priv_ep->wa1_trb->control = 393 - priv_ep->wa1_trb->control | 0x1; 394 - } else { 395 - priv_ep->wa1_trb->control = 396 - priv_ep->wa1_trb->control & ~0x1; 397 - } 398 - } 399 - } 400 - 401 - static int cdns3_prepare_aligned_request_buf(struct cdns3_request *priv_req) 402 - { 403 - struct cdns3_endpoint *priv_ep = priv_req->priv_ep; 404 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 405 - struct cdns3_aligned_buf *buf; 406 - 407 - /* check if buffer is aligned to 8. */ 408 - if (!((uintptr_t)priv_req->request.buf & 0x7)) 409 - return 0; 410 - 411 - buf = priv_req->aligned_buf; 412 - 413 - if (!buf || priv_req->request.length > buf->size) { 414 - buf = kzalloc(sizeof(*buf), GFP_ATOMIC); 415 - if (!buf) 416 - return -ENOMEM; 417 - 418 - buf->size = priv_req->request.length; 419 - 420 - buf->buf = dma_alloc_coherent(priv_dev->sysdev, 421 - buf->size, 422 - &buf->dma, 423 - GFP_ATOMIC); 424 - if (!buf->buf) { 425 - kfree(buf); 426 - return -ENOMEM; 427 - } 428 - 429 - if (priv_req->aligned_buf) { 430 - trace_cdns3_free_aligned_request(priv_req); 431 - priv_req->aligned_buf->in_use = 0; 432 - priv_dev->run_garbage_colector = 1; 433 - } 434 - 435 - buf->in_use = 1; 436 - priv_req->aligned_buf = buf; 437 - 438 - list_add_tail(&buf->list, 439 - &priv_dev->aligned_buf_list); 440 - } 441 - 442 - if (priv_ep->dir == USB_DIR_IN) { 443 - memcpy(buf->buf, priv_req->request.buf, 444 - priv_req->request.length); 445 - } 446 - 447 - priv_req->flags |= REQUEST_UNALIGNED; 448 - trace_cdns3_prepare_aligned_request(priv_req); 449 - 450 - return 0; 451 - } 452 - 453 - static int cdns3_wa1_update_guard(struct cdns3_endpoint *priv_ep, 454 - struct cdns3_trb *trb) 455 - { 456 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 457 - 458 - if (!priv_ep->wa1_set) { 459 - u32 doorbell; 460 - 461 - doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); 462 - 463 - if (doorbell) { 464 - priv_ep->wa1_cycle_bit = priv_ep->pcs ? TRB_CYCLE : 0; 465 - priv_ep->wa1_set = 1; 466 - priv_ep->wa1_trb = trb; 467 - priv_ep->wa1_trb_index = priv_ep->enqueue; 468 - cdns3_dbg(priv_dev, "WA1 set guard\n"); 469 - return 0; 470 - } 471 - } 472 - return 1; 473 - } 474 - 475 - static void cdns3_wa1_tray_restore_cycle_bit(struct cdns3_device *priv_dev, 476 - struct cdns3_endpoint *priv_ep) 477 - { 478 - int dma_index; 479 - u32 doorbell; 480 - 481 - doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); 482 - dma_index = cdns3_get_dma_pos(priv_dev, priv_ep); 483 - 484 - if (!doorbell || dma_index != priv_ep->wa1_trb_index) 485 - cdns3_wa1_restore_cycle_bit(priv_ep); 486 - } 487 - 488 - /** 489 - * cdns3_ep_run_transfer - start transfer on no-default endpoint hardware 490 - * @priv_ep: endpoint object 491 - * 492 - * Returns zero on success or negative value on failure 493 - */ 494 - int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep, 495 - struct usb_request *request) 496 - { 497 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 498 - struct cdns3_request *priv_req; 499 - struct cdns3_trb *trb; 500 - dma_addr_t trb_dma; 501 - u32 togle_pcs = 1; 502 - int sg_iter = 0; 503 - int num_trb; 504 - int address; 505 - u32 control; 506 - int pcs; 507 - 508 - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) 509 - num_trb = priv_ep->interval; 510 - else 511 - num_trb = request->num_sgs ? request->num_sgs : 1; 512 - 513 - if (num_trb > priv_ep->free_trbs) { 514 - priv_ep->flags |= EP_RING_FULL; 515 - return -ENOBUFS; 516 - } 517 - 518 - priv_req = to_cdns3_request(request); 519 - address = priv_ep->endpoint.desc->bEndpointAddress; 520 - 521 - priv_ep->flags |= EP_PENDING_REQUEST; 522 - 523 - /* must allocate buffer aligned to 8 */ 524 - if (priv_req->flags & REQUEST_UNALIGNED) 525 - trb_dma = priv_req->aligned_buf->dma; 526 - else 527 - trb_dma = request->dma; 528 - 529 - trb = priv_ep->trb_pool + priv_ep->enqueue; 530 - priv_req->start_trb = priv_ep->enqueue; 531 - priv_req->trb = trb; 532 - 533 - cdns3_select_ep(priv_ep->cdns3_dev, address); 534 - 535 - /* prepare ring */ 536 - if ((priv_ep->enqueue + num_trb) >= (priv_ep->num_trbs - 1)) { 537 - struct cdns3_trb *link_trb; 538 - int doorbell, dma_index; 539 - u32 ch_bit = 0; 540 - 541 - doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); 542 - dma_index = cdns3_get_dma_pos(priv_dev, priv_ep); 543 - 544 - /* Driver can't update LINK TRB if it is current processed. */ 545 - if (doorbell && dma_index == priv_ep->num_trbs - 1) { 546 - priv_ep->flags |= EP_DEFERRED_DRDY; 547 - return -ENOBUFS; 548 - } 549 - 550 - /*updating C bt in Link TRB before starting DMA*/ 551 - link_trb = priv_ep->trb_pool + (priv_ep->num_trbs - 1); 552 - /* 553 - * For TRs size equal 2 enabling TRB_CHAIN for epXin causes 554 - * that DMA stuck at the LINK TRB. 555 - * On the other hand, removing TRB_CHAIN for longer TRs for 556 - * epXout cause that DMA stuck after handling LINK TRB. 557 - * To eliminate this strange behavioral driver set TRB_CHAIN 558 - * bit only for TR size > 2. 559 - */ 560 - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC || 561 - TRBS_PER_SEGMENT > 2) 562 - ch_bit = TRB_CHAIN; 563 - 564 - link_trb->control = ((priv_ep->pcs) ? TRB_CYCLE : 0) | 565 - TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit; 566 - } 567 - 568 - if (priv_dev->dev_ver <= DEV_VER_V2) 569 - togle_pcs = cdns3_wa1_update_guard(priv_ep, trb); 570 - 571 - /* set incorrect Cycle Bit for first trb*/ 572 - control = priv_ep->pcs ? 0 : TRB_CYCLE; 573 - 574 - do { 575 - u32 length; 576 - u16 td_size = 0; 577 - 578 - /* fill TRB */ 579 - control |= TRB_TYPE(TRB_NORMAL); 580 - trb->buffer = TRB_BUFFER(request->num_sgs == 0 581 - ? trb_dma : request->sg[sg_iter].dma_address); 582 - 583 - if (likely(!request->num_sgs)) 584 - length = request->length; 585 - else 586 - length = request->sg[sg_iter].length; 587 - 588 - if (likely(priv_dev->dev_ver >= DEV_VER_V2)) 589 - td_size = DIV_ROUND_UP(length, 590 - priv_ep->endpoint.maxpacket); 591 - 592 - trb->length = TRB_BURST_LEN(priv_ep->trb_burst_size) | 593 - TRB_LEN(length); 594 - if (priv_dev->gadget.speed == USB_SPEED_SUPER) 595 - trb->length |= TRB_TDL_SS_SIZE(td_size); 596 - else 597 - control |= TRB_TDL_HS_SIZE(td_size); 598 - 599 - pcs = priv_ep->pcs ? TRB_CYCLE : 0; 600 - 601 - /* 602 - * first trb should be prepared as last to avoid processing 603 - * transfer to early 604 - */ 605 - if (sg_iter != 0) 606 - control |= pcs; 607 - 608 - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) { 609 - control |= TRB_IOC | TRB_ISP; 610 - } else { 611 - /* for last element in TD or in SG list */ 612 - if (sg_iter == (num_trb - 1) && sg_iter != 0) 613 - control |= pcs | TRB_IOC | TRB_ISP; 614 - } 615 - 616 - if (sg_iter) 617 - trb->control = control; 618 - else 619 - priv_req->trb->control = control; 620 - 621 - control = 0; 622 - ++sg_iter; 623 - priv_req->end_trb = priv_ep->enqueue; 624 - cdns3_ep_inc_enq(priv_ep); 625 - trb = priv_ep->trb_pool + priv_ep->enqueue; 626 - } while (sg_iter < num_trb); 627 - 628 - trb = priv_req->trb; 629 - 630 - priv_req->flags |= REQUEST_PENDING; 631 - 632 - if (sg_iter == 1) 633 - trb->control |= TRB_IOC | TRB_ISP; 634 - /* 635 - * Memory barrier - cycle bit must be set before other filds in trb. 636 - */ 637 - wmb(); 638 - 639 - /* give the TD to the consumer*/ 640 - if (togle_pcs) 641 - trb->control = trb->control ^ 1; 642 - 643 - if (priv_dev->dev_ver <= DEV_VER_V2) 644 - cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep); 645 - 646 - trace_cdns3_prepare_trb(priv_ep, priv_req->trb); 647 - 648 - /* 649 - * Memory barrier - Cycle Bit must be set before trb->length and 650 - * trb->buffer fields. 651 - */ 652 - wmb(); 653 - 654 - /* 655 - * For DMULT mode we can set address to transfer ring only once after 656 - * enabling endpoint. 657 - */ 658 - if (priv_ep->flags & EP_UPDATE_EP_TRBADDR) { 659 - /* 660 - * Until SW is not ready to handle the OUT transfer the ISO OUT 661 - * Endpoint should be disabled (EP_CFG.ENABLE = 0). 662 - * EP_CFG_ENABLE must be set before updating ep_traddr. 663 - */ 664 - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir && 665 - !(priv_ep->flags & EP_QUIRK_ISO_OUT_EN)) { 666 - priv_ep->flags |= EP_QUIRK_ISO_OUT_EN; 667 - cdns3_set_register_bit(&priv_dev->regs->ep_cfg, 668 - EP_CFG_ENABLE); 669 - } 670 - 671 - writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma + 672 - priv_req->start_trb * TRB_SIZE), 673 - &priv_dev->regs->ep_traddr); 674 - 675 - cdns3_dbg(priv_ep->cdns3_dev, "Update ep_trbaddr for %s to %08x\n", 676 - priv_ep->name, readl(&priv_dev->regs->ep_traddr)); 677 - 678 - priv_ep->flags &= ~EP_UPDATE_EP_TRBADDR; 679 - } 680 - 681 - if (!priv_ep->wa1_set && !(priv_ep->flags & EP_STALL)) { 682 - trace_cdns3_ring(priv_ep); 683 - /*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/ 684 - writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts); 685 - writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd); 686 - trace_cdns3_doorbell_epx(priv_ep->name, 687 - readl(&priv_dev->regs->ep_traddr)); 688 - } 689 - 690 - /* WORKAROUND for transition to L0 */ 691 - __cdns3_gadget_wakeup(priv_dev); 692 - 693 - return 0; 694 - } 695 - 696 - void cdns3_set_hw_configuration(struct cdns3_device *priv_dev) 697 - { 698 - struct cdns3_endpoint *priv_ep; 699 - struct usb_ep *ep; 700 - int result = 0; 701 - 702 - if (priv_dev->hw_configured_flag) 703 - return; 704 - 705 - writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf); 706 - writel(EP_CMD_ERDY | EP_CMD_REQ_CMPL, &priv_dev->regs->ep_cmd); 707 - 708 - cdns3_set_register_bit(&priv_dev->regs->usb_conf, 709 - USB_CONF_U1EN | USB_CONF_U2EN); 710 - 711 - /* wait until configuration set */ 712 - result = cdns3_handshake(&priv_dev->regs->usb_sts, 713 - USB_STS_CFGSTS_MASK, 1, 100); 714 - 715 - priv_dev->hw_configured_flag = 1; 716 - 717 - list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) { 718 - if (ep->enabled) { 719 - priv_ep = ep_to_cdns3_ep(ep); 720 - cdns3_start_all_request(priv_dev, priv_ep); 721 - } 722 - } 723 - } 724 - 725 - /** 726 - * cdns3_request_handled - check whether request has been handled by DMA 727 - * 728 - * @priv_ep: extended endpoint object. 729 - * @priv_req: request object for checking 730 - * 731 - * Endpoint must be selected before invoking this function. 732 - * 733 - * Returns false if request has not been handled by DMA, else returns true. 734 - * 735 - * SR - start ring 736 - * ER - end ring 737 - * DQ = priv_ep->dequeue - dequeue position 738 - * EQ = priv_ep->enqueue - enqueue position 739 - * ST = priv_req->start_trb - index of first TRB in transfer ring 740 - * ET = priv_req->end_trb - index of last TRB in transfer ring 741 - * CI = current_index - index of processed TRB by DMA. 742 - * 743 - * As first step, function checks if cycle bit for priv_req->start_trb is 744 - * correct. 745 - * 746 - * some rules: 747 - * 1. priv_ep->dequeue never exceed current_index. 748 - * 2 priv_ep->enqueue never exceed priv_ep->dequeue 749 - * 3. exception: priv_ep->enqueue == priv_ep->dequeue 750 - * and priv_ep->free_trbs is zero. 751 - * This case indicate that TR is full. 752 - * 753 - * Then We can split recognition into two parts: 754 - * Case 1 - priv_ep->dequeue < current_index 755 - * SR ... EQ ... DQ ... CI ... ER 756 - * SR ... DQ ... CI ... EQ ... ER 757 - * 758 - * Request has been handled by DMA if ST and ET is between DQ and CI. 759 - * 760 - * Case 2 - priv_ep->dequeue > current_index 761 - * This situation take place when CI go through the LINK TRB at the end of 762 - * transfer ring. 763 - * SR ... CI ... EQ ... DQ ... ER 764 - * 765 - * Request has been handled by DMA if ET is less then CI or 766 - * ET is greater or equal DQ. 767 - */ 768 - static bool cdns3_request_handled(struct cdns3_endpoint *priv_ep, 769 - struct cdns3_request *priv_req) 770 - { 771 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 772 - struct cdns3_trb *trb = priv_req->trb; 773 - int current_index = 0; 774 - int handled = 0; 775 - int doorbell; 776 - 777 - current_index = cdns3_get_dma_pos(priv_dev, priv_ep); 778 - doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); 779 - 780 - trb = &priv_ep->trb_pool[priv_req->start_trb]; 781 - 782 - if ((trb->control & TRB_CYCLE) != priv_ep->ccs) 783 - goto finish; 784 - 785 - if (doorbell == 1 && current_index == priv_ep->dequeue) 786 - goto finish; 787 - 788 - /* The corner case for TRBS_PER_SEGMENT equal 2). */ 789 - if (TRBS_PER_SEGMENT == 2 && priv_ep->type != USB_ENDPOINT_XFER_ISOC) { 790 - handled = 1; 791 - goto finish; 792 - } 793 - 794 - if (priv_ep->enqueue == priv_ep->dequeue && 795 - priv_ep->free_trbs == 0) { 796 - handled = 1; 797 - } else if (priv_ep->dequeue < current_index) { 798 - if ((current_index == (priv_ep->num_trbs - 1)) && 799 - !priv_ep->dequeue) 800 - goto finish; 801 - 802 - if (priv_req->end_trb >= priv_ep->dequeue && 803 - priv_req->end_trb < current_index) 804 - handled = 1; 805 - } else if (priv_ep->dequeue > current_index) { 806 - if (priv_req->end_trb < current_index || 807 - priv_req->end_trb >= priv_ep->dequeue) 808 - handled = 1; 809 - } 810 - 811 - finish: 812 - trace_cdns3_request_handled(priv_req, current_index, handled); 813 - 814 - return handled; 815 - } 816 - 817 - static void cdns3_transfer_completed(struct cdns3_device *priv_dev, 818 - struct cdns3_endpoint *priv_ep) 819 - { 820 - struct cdns3_request *priv_req; 821 - struct usb_request *request; 822 - struct cdns3_trb *trb; 823 - 824 - while (!list_empty(&priv_ep->pending_req_list)) { 825 - request = cdns3_next_request(&priv_ep->pending_req_list); 826 - priv_req = to_cdns3_request(request); 827 - 828 - /* Re-select endpoint. It could be changed by other CPU during 829 - * handling usb_gadget_giveback_request. 830 - */ 831 - cdns3_select_ep(priv_dev, priv_ep->endpoint.address); 832 - 833 - if (!cdns3_request_handled(priv_ep, priv_req)) 834 - goto prepare_next_td; 835 - 836 - trb = priv_ep->trb_pool + priv_ep->dequeue; 837 - trace_cdns3_complete_trb(priv_ep, trb); 838 - 839 - if (trb != priv_req->trb) 840 - dev_warn(priv_dev->dev, 841 - "request_trb=0x%p, queue_trb=0x%p\n", 842 - priv_req->trb, trb); 843 - 844 - request->actual = TRB_LEN(le32_to_cpu(trb->length)); 845 - cdns3_move_deq_to_next_trb(priv_req); 846 - cdns3_gadget_giveback(priv_ep, priv_req, 0); 847 - 848 - if (priv_ep->type != USB_ENDPOINT_XFER_ISOC && 849 - TRBS_PER_SEGMENT == 2) 850 - break; 851 - } 852 - priv_ep->flags &= ~EP_PENDING_REQUEST; 853 - 854 - prepare_next_td: 855 - cdns3_start_all_request(priv_dev, priv_ep); 856 - } 857 - 858 - void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm) 859 - { 860 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 861 - 862 - cdns3_wa1_restore_cycle_bit(priv_ep); 863 - 864 - if (rearm) { 865 - trace_cdns3_ring(priv_ep); 866 - 867 - /* Cycle Bit must be updated before arming DMA. */ 868 - wmb(); 869 - writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd); 870 - 871 - __cdns3_gadget_wakeup(priv_dev); 872 - 873 - trace_cdns3_doorbell_epx(priv_ep->name, 874 - readl(&priv_dev->regs->ep_traddr)); 875 - } 876 - } 877 - 878 - /** 879 - * cdns3_check_ep_interrupt_proceed - Processes interrupt related to endpoint 880 - * @priv_ep: endpoint object 881 - * 882 - * Returns 0 883 - */ 884 - static int cdns3_check_ep_interrupt_proceed(struct cdns3_endpoint *priv_ep) 885 - { 886 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 887 - u32 ep_sts_reg; 888 - 889 - cdns3_select_ep(priv_dev, priv_ep->endpoint.address); 890 - 891 - trace_cdns3_epx_irq(priv_dev, priv_ep); 892 - 893 - ep_sts_reg = readl(&priv_dev->regs->ep_sts); 894 - writel(ep_sts_reg, &priv_dev->regs->ep_sts); 895 - 896 - if (ep_sts_reg & EP_STS_TRBERR) { 897 - /* 898 - * For isochronous transfer driver completes request on 899 - * IOC or on TRBERR. IOC appears only when device receive 900 - * OUT data packet. If host disable stream or lost some packet 901 - * then the only way to finish all queued transfer is to do it 902 - * on TRBERR event. 903 - */ 904 - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && 905 - !priv_ep->wa1_set) { 906 - if (!priv_ep->dir) { 907 - u32 ep_cfg = readl(&priv_dev->regs->ep_cfg); 908 - 909 - ep_cfg &= ~EP_CFG_ENABLE; 910 - writel(ep_cfg, &priv_dev->regs->ep_cfg); 911 - priv_ep->flags &= ~EP_QUIRK_ISO_OUT_EN; 912 - } 913 - cdns3_transfer_completed(priv_dev, priv_ep); 914 - } else { 915 - if (priv_ep->flags & EP_DEFERRED_DRDY) { 916 - priv_ep->flags &= ~EP_DEFERRED_DRDY; 917 - cdns3_start_all_request(priv_dev, priv_ep); 918 - } else { 919 - cdns3_rearm_transfer(priv_ep, priv_ep->wa1_set); 920 - } 921 - } 922 - } 923 - 924 - if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) 925 - cdns3_transfer_completed(priv_dev, priv_ep); 926 - 927 - return 0; 928 - } 929 - 930 - /** 931 - * cdns3_check_usb_interrupt_proceed - Processes interrupt related to device 932 - * @priv_dev: extended gadget object 933 - * @usb_ists: bitmap representation of device's reported interrupts 934 - * (usb_ists register value) 935 - */ 936 - static void cdns3_check_usb_interrupt_proceed(struct cdns3_device *priv_dev, 937 - u32 usb_ists) 938 - { 939 - int speed = 0; 940 - 941 - trace_cdns3_usb_irq(priv_dev, usb_ists); 942 - if (usb_ists & USB_ISTS_L1ENTI) { 943 - /* 944 - * WORKAROUND: CDNS3 controller has issue with hardware resuming 945 - * from L1. To fix it, if any DMA transfer is pending driver 946 - * must starts driving resume signal immediately. 947 - */ 948 - if (readl(&priv_dev->regs->drbl)) 949 - __cdns3_gadget_wakeup(priv_dev); 950 - } 951 - 952 - /* Connection detected */ 953 - if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) { 954 - speed = cdns3_get_speed(priv_dev); 955 - priv_dev->gadget.speed = speed; 956 - usb_gadget_set_state(&priv_dev->gadget, USB_STATE_POWERED); 957 - cdns3_ep0_config(priv_dev); 958 - } 959 - 960 - /* Disconnection detected */ 961 - if (usb_ists & (USB_ISTS_DIS2I | USB_ISTS_DISI)) { 962 - if (priv_dev->gadget_driver && 963 - priv_dev->gadget_driver->disconnect) { 964 - spin_unlock(&priv_dev->lock); 965 - priv_dev->gadget_driver->disconnect(&priv_dev->gadget); 966 - spin_lock(&priv_dev->lock); 967 - } 968 - 969 - priv_dev->gadget.speed = USB_SPEED_UNKNOWN; 970 - usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED); 971 - cdns3_hw_reset_eps_config(priv_dev); 972 - } 973 - 974 - if (usb_ists & (USB_ISTS_L2ENTI | USB_ISTS_U3ENTI)) { 975 - if (priv_dev->gadget_driver && 976 - priv_dev->gadget_driver->suspend) { 977 - spin_unlock(&priv_dev->lock); 978 - priv_dev->gadget_driver->suspend(&priv_dev->gadget); 979 - spin_lock(&priv_dev->lock); 980 - } 981 - } 982 - 983 - if (usb_ists & (USB_ISTS_L2EXTI | USB_ISTS_U3EXTI)) { 984 - if (priv_dev->gadget_driver && 985 - priv_dev->gadget_driver->resume) { 986 - spin_unlock(&priv_dev->lock); 987 - priv_dev->gadget_driver->resume(&priv_dev->gadget); 988 - spin_lock(&priv_dev->lock); 989 - } 990 - } 991 - 992 - /* reset*/ 993 - if (usb_ists & (USB_ISTS_UWRESI | USB_ISTS_UHRESI | USB_ISTS_U2RESI)) { 994 - if (priv_dev->gadget_driver) { 995 - spin_unlock(&priv_dev->lock); 996 - usb_gadget_udc_reset(&priv_dev->gadget, 997 - priv_dev->gadget_driver); 998 - spin_lock(&priv_dev->lock); 999 - 1000 - /*read again to check the actual speed*/ 1001 - speed = cdns3_get_speed(priv_dev); 1002 - priv_dev->gadget.speed = speed; 1003 - cdns3_hw_reset_eps_config(priv_dev); 1004 - cdns3_ep0_config(priv_dev); 1005 - } 1006 - } 1007 - } 1008 - 1009 - /** 1010 - * cdns3_device_irq_handler- interrupt handler for device part of controller 1011 - * 1012 - * @irq: irq number for cdns3 core device 1013 - * @data: structure of cdns3 1014 - * 1015 - * Returns IRQ_HANDLED or IRQ_NONE 1016 - */ 1017 - static irqreturn_t cdns3_device_irq_handler(int irq, void *data) 1018 - { 1019 - struct cdns3_device *priv_dev; 1020 - struct cdns3 *cdns = data; 1021 - irqreturn_t ret = IRQ_NONE; 1022 - unsigned long flags; 1023 - u32 reg; 1024 - 1025 - priv_dev = cdns->gadget_dev; 1026 - spin_lock_irqsave(&priv_dev->lock, flags); 1027 - 1028 - /* check USB device interrupt */ 1029 - reg = readl(&priv_dev->regs->usb_ists); 1030 - 1031 - if (reg) { 1032 - writel(reg, &priv_dev->regs->usb_ists); 1033 - cdns3_check_usb_interrupt_proceed(priv_dev, reg); 1034 - ret = IRQ_HANDLED; 1035 - } 1036 - 1037 - /* check endpoint interrupt */ 1038 - reg = readl(&priv_dev->regs->ep_ists); 1039 - 1040 - if (reg) { 1041 - priv_dev->shadow_ep_en |= reg; 1042 - reg = ~reg & readl(&priv_dev->regs->ep_ien); 1043 - /* mask deferred interrupt. */ 1044 - writel(reg, &priv_dev->regs->ep_ien); 1045 - ret = IRQ_WAKE_THREAD; 1046 - } 1047 - 1048 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1049 - return ret; 1050 - } 1051 - 1052 - /** 1053 - * cdns3_device_thread_irq_handler- interrupt handler for device part 1054 - * of controller 1055 - * 1056 - * @irq: irq number for cdns3 core device 1057 - * @data: structure of cdns3 1058 - * 1059 - * Returns IRQ_HANDLED or IRQ_NONE 1060 - */ 1061 - static irqreturn_t cdns3_device_thread_irq_handler(int irq, void *data) 1062 - { 1063 - struct cdns3_device *priv_dev; 1064 - struct cdns3 *cdns = data; 1065 - irqreturn_t ret = IRQ_NONE; 1066 - unsigned long flags; 1067 - u32 ep_ien; 1068 - int bit; 1069 - u32 reg; 1070 - 1071 - priv_dev = cdns->gadget_dev; 1072 - spin_lock_irqsave(&priv_dev->lock, flags); 1073 - 1074 - reg = readl(&priv_dev->regs->ep_ists); 1075 - 1076 - /* handle default endpoint OUT */ 1077 - if (reg & EP_ISTS_EP_OUT0) { 1078 - cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_OUT); 1079 - ret = IRQ_HANDLED; 1080 - } 1081 - 1082 - /* handle default endpoint IN */ 1083 - if (reg & EP_ISTS_EP_IN0) { 1084 - cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_IN); 1085 - ret = IRQ_HANDLED; 1086 - } 1087 - 1088 - /* check if interrupt from non default endpoint, if no exit */ 1089 - reg &= ~(EP_ISTS_EP_OUT0 | EP_ISTS_EP_IN0); 1090 - if (!reg) 1091 - goto irqend; 1092 - 1093 - for_each_set_bit(bit, (unsigned long *)&reg, 1094 - sizeof(u32) * BITS_PER_BYTE) { 1095 - priv_dev->shadow_ep_en |= BIT(bit); 1096 - cdns3_check_ep_interrupt_proceed(priv_dev->eps[bit]); 1097 - ret = IRQ_HANDLED; 1098 - } 1099 - 1100 - if (priv_dev->run_garbage_colector) { 1101 - struct cdns3_aligned_buf *buf, *tmp; 1102 - 1103 - list_for_each_entry_safe(buf, tmp, &priv_dev->aligned_buf_list, 1104 - list) { 1105 - if (!buf->in_use) { 1106 - list_del(&buf->list); 1107 - 1108 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1109 - dma_free_coherent(priv_dev->sysdev, buf->size, 1110 - buf->buf, 1111 - buf->dma); 1112 - spin_lock_irqsave(&priv_dev->lock, flags); 1113 - 1114 - kfree(buf); 1115 - } 1116 - } 1117 - 1118 - priv_dev->run_garbage_colector = 0; 1119 - } 1120 - 1121 - irqend: 1122 - ep_ien = readl(&priv_dev->regs->ep_ien) | priv_dev->shadow_ep_en; 1123 - priv_dev->shadow_ep_en = 0; 1124 - /* Unmask all handled EP interrupts */ 1125 - writel(ep_ien, &priv_dev->regs->ep_ien); 1126 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1127 - return ret; 1128 - } 1129 - 1130 - /** 1131 - * cdns3_ep_onchip_buffer_reserve - Try to reserve onchip buf for EP 1132 - * 1133 - * The real reservation will occur during write to EP_CFG register, 1134 - * this function is used to check if the 'size' reservation is allowed. 1135 - * 1136 - * @priv_dev: extended gadget object 1137 - * @size: the size (KB) for EP would like to allocate 1138 - * @is_in: endpoint direction 1139 - * 1140 - * Return 0 if the required size can met or negative value on failure 1141 - */ 1142 - static int cdns3_ep_onchip_buffer_reserve(struct cdns3_device *priv_dev, 1143 - int size, int is_in) 1144 - { 1145 - int remained; 1146 - 1147 - /* 2KB are reserved for EP0*/ 1148 - remained = priv_dev->onchip_buffers - priv_dev->onchip_used_size - 2; 1149 - 1150 - if (is_in) { 1151 - if (remained < size) 1152 - return -EPERM; 1153 - 1154 - priv_dev->onchip_used_size += size; 1155 - } else { 1156 - int required; 1157 - 1158 - /** 1159 - * ALL OUT EPs are shared the same chunk onchip memory, so 1160 - * driver checks if it already has assigned enough buffers 1161 - */ 1162 - if (priv_dev->out_mem_is_allocated >= size) 1163 - return 0; 1164 - 1165 - required = size - priv_dev->out_mem_is_allocated; 1166 - 1167 - if (required > remained) 1168 - return -EPERM; 1169 - 1170 - priv_dev->out_mem_is_allocated += required; 1171 - priv_dev->onchip_used_size += required; 1172 - } 1173 - 1174 - return 0; 1175 - } 1176 - 1177 - void cdns3_configure_dmult(struct cdns3_device *priv_dev, 1178 - struct cdns3_endpoint *priv_ep) 1179 - { 1180 - struct cdns3_usb_regs __iomem *regs = priv_dev->regs; 1181 - 1182 - /* For dev_ver > DEV_VER_V2 DMULT is configured per endpoint */ 1183 - if (priv_dev->dev_ver <= DEV_VER_V2) 1184 - writel(USB_CONF_DMULT, &regs->usb_conf); 1185 - 1186 - if (priv_dev->dev_ver == DEV_VER_V2) 1187 - writel(USB_CONF2_EN_TDL_TRB, &regs->usb_conf2); 1188 - 1189 - if (priv_dev->dev_ver >= DEV_VER_V3 && priv_ep) { 1190 - u32 mask; 1191 - 1192 - if (priv_ep->dir) 1193 - mask = BIT(priv_ep->num + 16); 1194 - else 1195 - mask = BIT(priv_ep->num); 1196 - 1197 - if (priv_ep->type != USB_ENDPOINT_XFER_ISOC) { 1198 - cdns3_set_register_bit(&regs->tdl_from_trb, mask); 1199 - cdns3_set_register_bit(&regs->tdl_beh, mask); 1200 - cdns3_set_register_bit(&regs->tdl_beh2, mask); 1201 - cdns3_set_register_bit(&regs->dma_adv_td, mask); 1202 - } 1203 - 1204 - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) 1205 - cdns3_set_register_bit(&regs->tdl_from_trb, mask); 1206 - 1207 - cdns3_set_register_bit(&regs->dtrans, mask); 1208 - } 1209 - } 1210 - 1211 - /** 1212 - * cdns3_ep_config Configure hardware endpoint 1213 - * @priv_ep: extended endpoint object 1214 - */ 1215 - void cdns3_ep_config(struct cdns3_endpoint *priv_ep) 1216 - { 1217 - bool is_iso_ep = (priv_ep->type == USB_ENDPOINT_XFER_ISOC); 1218 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 1219 - u32 bEndpointAddress = priv_ep->num | priv_ep->dir; 1220 - u32 max_packet_size = 0; 1221 - u8 maxburst = 0; 1222 - u32 ep_cfg = 0; 1223 - u8 buffering; 1224 - u8 mult = 0; 1225 - int ret; 1226 - 1227 - buffering = CDNS3_EP_BUF_SIZE - 1; 1228 - 1229 - cdns3_configure_dmult(priv_dev, priv_ep); 1230 - 1231 - switch (priv_ep->type) { 1232 - case USB_ENDPOINT_XFER_INT: 1233 - ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_INT); 1234 - 1235 - if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) || 1236 - priv_dev->dev_ver > DEV_VER_V2) 1237 - ep_cfg |= EP_CFG_TDL_CHK; 1238 - break; 1239 - case USB_ENDPOINT_XFER_BULK: 1240 - ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_BULK); 1241 - 1242 - if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) || 1243 - priv_dev->dev_ver > DEV_VER_V2) 1244 - ep_cfg |= EP_CFG_TDL_CHK; 1245 - break; 1246 - default: 1247 - ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_ISOC); 1248 - mult = CDNS3_EP_ISO_HS_MULT - 1; 1249 - buffering = mult + 1; 1250 - } 1251 - 1252 - switch (priv_dev->gadget.speed) { 1253 - case USB_SPEED_FULL: 1254 - max_packet_size = is_iso_ep ? 1023 : 64; 1255 - break; 1256 - case USB_SPEED_HIGH: 1257 - max_packet_size = is_iso_ep ? 1024 : 512; 1258 - break; 1259 - case USB_SPEED_SUPER: 1260 - /* It's limitation that driver assumes in driver. */ 1261 - mult = 0; 1262 - max_packet_size = 1024; 1263 - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) { 1264 - maxburst = CDNS3_EP_ISO_SS_BURST - 1; 1265 - buffering = (mult + 1) * 1266 - (maxburst + 1); 1267 - 1268 - if (priv_ep->interval > 1) 1269 - buffering++; 1270 - } else { 1271 - maxburst = CDNS3_EP_BUF_SIZE - 1; 1272 - } 1273 - break; 1274 - default: 1275 - /* all other speed are not supported */ 1276 - return; 1277 - } 1278 - 1279 - if (max_packet_size == 1024) 1280 - priv_ep->trb_burst_size = 128; 1281 - else if (max_packet_size >= 512) 1282 - priv_ep->trb_burst_size = 64; 1283 - else 1284 - priv_ep->trb_burst_size = 16; 1285 - 1286 - ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1, 1287 - !!priv_ep->dir); 1288 - if (ret) { 1289 - dev_err(priv_dev->dev, "onchip mem is full, ep is invalid\n"); 1290 - return; 1291 - } 1292 - 1293 - ep_cfg |= EP_CFG_MAXPKTSIZE(max_packet_size) | 1294 - EP_CFG_MULT(mult) | 1295 - EP_CFG_BUFFERING(buffering) | 1296 - EP_CFG_MAXBURST(maxburst); 1297 - 1298 - cdns3_select_ep(priv_dev, bEndpointAddress); 1299 - writel(ep_cfg, &priv_dev->regs->ep_cfg); 1300 - 1301 - dev_dbg(priv_dev->dev, "Configure %s: with val %08x\n", 1302 - priv_ep->name, ep_cfg); 1303 - } 1304 - 1305 - /* Find correct direction for HW endpoint according to description */ 1306 - static int cdns3_ep_dir_is_correct(struct usb_endpoint_descriptor *desc, 1307 - struct cdns3_endpoint *priv_ep) 1308 - { 1309 - return (priv_ep->endpoint.caps.dir_in && usb_endpoint_dir_in(desc)) || 1310 - (priv_ep->endpoint.caps.dir_out && usb_endpoint_dir_out(desc)); 1311 - } 1312 - 1313 - static struct 1314 - cdns3_endpoint *cdns3_find_available_ep(struct cdns3_device *priv_dev, 1315 - struct usb_endpoint_descriptor *desc) 1316 - { 1317 - struct usb_ep *ep; 1318 - struct cdns3_endpoint *priv_ep; 1319 - 1320 - list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) { 1321 - unsigned long num; 1322 - int ret; 1323 - /* ep name pattern likes epXin or epXout */ 1324 - char c[2] = {ep->name[2], '\0'}; 1325 - 1326 - ret = kstrtoul(c, 10, &num); 1327 - if (ret) 1328 - return ERR_PTR(ret); 1329 - 1330 - priv_ep = ep_to_cdns3_ep(ep); 1331 - if (cdns3_ep_dir_is_correct(desc, priv_ep)) { 1332 - if (!(priv_ep->flags & EP_CLAIMED)) { 1333 - priv_ep->num = num; 1334 - return priv_ep; 1335 - } 1336 - } 1337 - } 1338 - 1339 - return ERR_PTR(-ENOENT); 1340 - } 1341 - 1342 - /* 1343 - * Cadence IP has one limitation that all endpoints must be configured 1344 - * (Type & MaxPacketSize) before setting configuration through hardware 1345 - * register, it means we can't change endpoints configuration after 1346 - * set_configuration. 1347 - * 1348 - * This function set EP_CLAIMED flag which is added when the gadget driver 1349 - * uses usb_ep_autoconfig to configure specific endpoint; 1350 - * When the udc driver receives set_configurion request, 1351 - * it goes through all claimed endpoints, and configure all endpoints 1352 - * accordingly. 1353 - * 1354 - * At usb_ep_ops.enable/disable, we only enable and disable endpoint through 1355 - * ep_cfg register which can be changed after set_configuration, and do 1356 - * some software operation accordingly. 1357 - */ 1358 - static struct 1359 - usb_ep *cdns3_gadget_match_ep(struct usb_gadget *gadget, 1360 - struct usb_endpoint_descriptor *desc, 1361 - struct usb_ss_ep_comp_descriptor *comp_desc) 1362 - { 1363 - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); 1364 - struct cdns3_endpoint *priv_ep; 1365 - unsigned long flags; 1366 - 1367 - priv_ep = cdns3_find_available_ep(priv_dev, desc); 1368 - if (IS_ERR(priv_ep)) { 1369 - dev_err(priv_dev->dev, "no available ep\n"); 1370 - return NULL; 1371 - } 1372 - 1373 - dev_dbg(priv_dev->dev, "match endpoint: %s\n", priv_ep->name); 1374 - 1375 - spin_lock_irqsave(&priv_dev->lock, flags); 1376 - priv_ep->endpoint.desc = desc; 1377 - priv_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT; 1378 - priv_ep->type = usb_endpoint_type(desc); 1379 - priv_ep->flags |= EP_CLAIMED; 1380 - priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0; 1381 - 1382 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1383 - return &priv_ep->endpoint; 1384 - } 1385 - 1386 - /** 1387 - * cdns3_gadget_ep_alloc_request Allocates request 1388 - * @ep: endpoint object associated with request 1389 - * @gfp_flags: gfp flags 1390 - * 1391 - * Returns allocated request address, NULL on allocation error 1392 - */ 1393 - struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep, 1394 - gfp_t gfp_flags) 1395 - { 1396 - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); 1397 - struct cdns3_request *priv_req; 1398 - 1399 - priv_req = kzalloc(sizeof(*priv_req), gfp_flags); 1400 - if (!priv_req) 1401 - return NULL; 1402 - 1403 - priv_req->priv_ep = priv_ep; 1404 - 1405 - trace_cdns3_alloc_request(priv_req); 1406 - return &priv_req->request; 1407 - } 1408 - 1409 - /** 1410 - * cdns3_gadget_ep_free_request Free memory occupied by request 1411 - * @ep: endpoint object associated with request 1412 - * @request: request to free memory 1413 - */ 1414 - void cdns3_gadget_ep_free_request(struct usb_ep *ep, 1415 - struct usb_request *request) 1416 - { 1417 - struct cdns3_request *priv_req = to_cdns3_request(request); 1418 - 1419 - if (priv_req->aligned_buf) 1420 - priv_req->aligned_buf->in_use = 0; 1421 - 1422 - trace_cdns3_free_request(priv_req); 1423 - kfree(priv_req); 1424 - } 1425 - 1426 - /** 1427 - * cdns3_gadget_ep_enable Enable endpoint 1428 - * @ep: endpoint object 1429 - * @desc: endpoint descriptor 1430 - * 1431 - * Returns 0 on success, error code elsewhere 1432 - */ 1433 - static int cdns3_gadget_ep_enable(struct usb_ep *ep, 1434 - const struct usb_endpoint_descriptor *desc) 1435 - { 1436 - struct cdns3_endpoint *priv_ep; 1437 - struct cdns3_device *priv_dev; 1438 - u32 reg = EP_STS_EN_TRBERREN; 1439 - u32 bEndpointAddress; 1440 - unsigned long flags; 1441 - int enable = 1; 1442 - int ret; 1443 - 1444 - priv_ep = ep_to_cdns3_ep(ep); 1445 - priv_dev = priv_ep->cdns3_dev; 1446 - 1447 - if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 1448 - dev_dbg(priv_dev->dev, "usbss: invalid parameters\n"); 1449 - return -EINVAL; 1450 - } 1451 - 1452 - if (!desc->wMaxPacketSize) { 1453 - dev_err(priv_dev->dev, "usbss: missing wMaxPacketSize\n"); 1454 - return -EINVAL; 1455 - } 1456 - 1457 - if (dev_WARN_ONCE(priv_dev->dev, priv_ep->flags & EP_ENABLED, 1458 - "%s is already enabled\n", priv_ep->name)) 1459 - return 0; 1460 - 1461 - spin_lock_irqsave(&priv_dev->lock, flags); 1462 - 1463 - priv_ep->endpoint.desc = desc; 1464 - priv_ep->type = usb_endpoint_type(desc); 1465 - priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0; 1466 - 1467 - if (priv_ep->interval > ISO_MAX_INTERVAL && 1468 - priv_ep->type == USB_ENDPOINT_XFER_ISOC) { 1469 - dev_err(priv_dev->dev, "Driver is limited to %d period\n", 1470 - ISO_MAX_INTERVAL); 1471 - 1472 - ret = -EINVAL; 1473 - goto exit; 1474 - } 1475 - 1476 - ret = cdns3_allocate_trb_pool(priv_ep); 1477 - 1478 - if (ret) 1479 - goto exit; 1480 - 1481 - bEndpointAddress = priv_ep->num | priv_ep->dir; 1482 - cdns3_select_ep(priv_dev, bEndpointAddress); 1483 - 1484 - trace_cdns3_gadget_ep_enable(priv_ep); 1485 - 1486 - writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd); 1487 - 1488 - ret = cdns3_handshake(&priv_dev->regs->ep_cmd, 1489 - EP_CMD_CSTALL | EP_CMD_EPRST, 0, 1000); 1490 - 1491 - if (unlikely(ret)) { 1492 - cdns3_free_trb_pool(priv_ep); 1493 - ret = -EINVAL; 1494 - goto exit; 1495 - } 1496 - 1497 - /* enable interrupt for selected endpoint */ 1498 - cdns3_set_register_bit(&priv_dev->regs->ep_ien, 1499 - BIT(cdns3_ep_addr_to_index(bEndpointAddress))); 1500 - 1501 - writel(reg, &priv_dev->regs->ep_sts_en); 1502 - 1503 - /* 1504 - * For some versions of controller at some point during ISO OUT traffic 1505 - * DMA reads Transfer Ring for the EP which has never got doorbell. 1506 - * This issue was detected only on simulation, but to avoid this issue 1507 - * driver add protection against it. To fix it driver enable ISO OUT 1508 - * endpoint before setting DRBL. This special treatment of ISO OUT 1509 - * endpoints are recommended by controller specification. 1510 - */ 1511 - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) 1512 - enable = 0; 1513 - 1514 - if (enable) 1515 - cdns3_set_register_bit(&priv_dev->regs->ep_cfg, EP_CFG_ENABLE); 1516 - 1517 - ep->desc = desc; 1518 - priv_ep->flags &= ~(EP_PENDING_REQUEST | EP_STALL | 1519 - EP_QUIRK_ISO_OUT_EN); 1520 - priv_ep->flags |= EP_ENABLED | EP_UPDATE_EP_TRBADDR; 1521 - priv_ep->wa1_set = 0; 1522 - priv_ep->enqueue = 0; 1523 - priv_ep->dequeue = 0; 1524 - reg = readl(&priv_dev->regs->ep_sts); 1525 - priv_ep->pcs = !!EP_STS_CCS(reg); 1526 - priv_ep->ccs = !!EP_STS_CCS(reg); 1527 - /* one TRB is reserved for link TRB used in DMULT mode*/ 1528 - priv_ep->free_trbs = priv_ep->num_trbs - 1; 1529 - exit: 1530 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1531 - 1532 - return ret; 1533 - } 1534 - 1535 - /** 1536 - * cdns3_gadget_ep_disable Disable endpoint 1537 - * @ep: endpoint object 1538 - * 1539 - * Returns 0 on success, error code elsewhere 1540 - */ 1541 - static int cdns3_gadget_ep_disable(struct usb_ep *ep) 1542 - { 1543 - struct cdns3_endpoint *priv_ep; 1544 - struct cdns3_device *priv_dev; 1545 - struct usb_request *request; 1546 - unsigned long flags; 1547 - int ret = 0; 1548 - u32 ep_cfg; 1549 - 1550 - if (!ep) { 1551 - pr_err("usbss: invalid parameters\n"); 1552 - return -EINVAL; 1553 - } 1554 - 1555 - priv_ep = ep_to_cdns3_ep(ep); 1556 - priv_dev = priv_ep->cdns3_dev; 1557 - 1558 - if (dev_WARN_ONCE(priv_dev->dev, !(priv_ep->flags & EP_ENABLED), 1559 - "%s is already disabled\n", priv_ep->name)) 1560 - return 0; 1561 - 1562 - spin_lock_irqsave(&priv_dev->lock, flags); 1563 - 1564 - trace_cdns3_gadget_ep_disable(priv_ep); 1565 - 1566 - cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress); 1567 - 1568 - ep_cfg = readl(&priv_dev->regs->ep_cfg); 1569 - ep_cfg &= ~EP_CFG_ENABLE; 1570 - writel(ep_cfg, &priv_dev->regs->ep_cfg); 1571 - 1572 - /** 1573 - * Driver needs some time before resetting endpoint. 1574 - * It need waits for clearing DBUSY bit or for timeout expired. 1575 - * 10us is enough time for controller to stop transfer. 1576 - */ 1577 - cdns3_handshake(&priv_dev->regs->ep_sts, 1578 - EP_STS_DBUSY, 0, 10); 1579 - 1580 - writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd); 1581 - 1582 - ret = cdns3_handshake(&priv_dev->regs->ep_cmd, 1583 - EP_CMD_CSTALL | EP_CMD_EPRST, 0, 1000); 1584 - 1585 - if (unlikely(ret)) 1586 - dev_err(priv_dev->dev, "Timeout: %s resetting failed.\n", 1587 - priv_ep->name); 1588 - 1589 - while (!list_empty(&priv_ep->pending_req_list)) { 1590 - request = cdns3_next_request(&priv_ep->pending_req_list); 1591 - 1592 - cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), 1593 - -ESHUTDOWN); 1594 - } 1595 - 1596 - while (!list_empty(&priv_ep->deferred_req_list)) { 1597 - request = cdns3_next_request(&priv_ep->deferred_req_list); 1598 - 1599 - cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), 1600 - -ESHUTDOWN); 1601 - } 1602 - 1603 - ep->desc = NULL; 1604 - priv_ep->flags &= ~EP_ENABLED; 1605 - 1606 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1607 - 1608 - return ret; 1609 - } 1610 - 1611 - /** 1612 - * cdns3_gadget_ep_queue Transfer data on endpoint 1613 - * @ep: endpoint object 1614 - * @request: request object 1615 - * @gfp_flags: gfp flags 1616 - * 1617 - * Returns 0 on success, error code elsewhere 1618 - */ 1619 - static int __cdns3_gadget_ep_queue(struct usb_ep *ep, 1620 - struct usb_request *request, 1621 - gfp_t gfp_flags) 1622 - { 1623 - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); 1624 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 1625 - struct cdns3_request *priv_req; 1626 - int ret = 0; 1627 - 1628 - request->actual = 0; 1629 - request->status = -EINPROGRESS; 1630 - priv_req = to_cdns3_request(request); 1631 - trace_cdns3_ep_queue(priv_req); 1632 - 1633 - ret = cdns3_prepare_aligned_request_buf(priv_req); 1634 - if (ret < 0) 1635 - return ret; 1636 - 1637 - ret = usb_gadget_map_request_by_dev(priv_dev->sysdev, request, 1638 - usb_endpoint_dir_in(ep->desc)); 1639 - if (ret) 1640 - return ret; 1641 - 1642 - list_add_tail(&request->list, &priv_ep->deferred_req_list); 1643 - 1644 - /* 1645 - * If hardware endpoint configuration has not been set yet then 1646 - * just queue request in deferred list. Transfer will be started in 1647 - * cdns3_set_hw_configuration. 1648 - */ 1649 - if (priv_dev->hw_configured_flag) 1650 - cdns3_start_all_request(priv_dev, priv_ep); 1651 - 1652 - return 0; 1653 - } 1654 - 1655 - static int cdns3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1656 - gfp_t gfp_flags) 1657 - { 1658 - struct usb_request *zlp_request; 1659 - struct cdns3_endpoint *priv_ep; 1660 - struct cdns3_device *priv_dev; 1661 - unsigned long flags; 1662 - int ret; 1663 - 1664 - if (!request || !ep) 1665 - return -EINVAL; 1666 - 1667 - priv_ep = ep_to_cdns3_ep(ep); 1668 - priv_dev = priv_ep->cdns3_dev; 1669 - 1670 - spin_lock_irqsave(&priv_dev->lock, flags); 1671 - 1672 - ret = __cdns3_gadget_ep_queue(ep, request, gfp_flags); 1673 - 1674 - if (ret == 0 && request->zero && request->length && 1675 - (request->length % ep->maxpacket == 0)) { 1676 - struct cdns3_request *priv_req; 1677 - 1678 - zlp_request = cdns3_gadget_ep_alloc_request(ep, GFP_ATOMIC); 1679 - zlp_request->buf = priv_dev->zlp_buf; 1680 - zlp_request->length = 0; 1681 - 1682 - priv_req = to_cdns3_request(zlp_request); 1683 - priv_req->flags |= REQUEST_ZLP; 1684 - 1685 - dev_dbg(priv_dev->dev, "Queuing ZLP for endpoint: %s\n", 1686 - priv_ep->name); 1687 - ret = __cdns3_gadget_ep_queue(ep, zlp_request, gfp_flags); 1688 - } 1689 - 1690 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1691 - return ret; 1692 - } 1693 - 1694 - /** 1695 - * cdns3_gadget_ep_dequeue Remove request from transfer queue 1696 - * @ep: endpoint object associated with request 1697 - * @request: request object 1698 - * 1699 - * Returns 0 on success, error code elsewhere 1700 - */ 1701 - int cdns3_gadget_ep_dequeue(struct usb_ep *ep, 1702 - struct usb_request *request) 1703 - { 1704 - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); 1705 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 1706 - struct usb_request *req, *req_temp; 1707 - struct cdns3_request *priv_req; 1708 - struct cdns3_trb *link_trb; 1709 - unsigned long flags; 1710 - int ret = 0; 1711 - 1712 - if (!ep || !request || !ep->desc) 1713 - return -EINVAL; 1714 - 1715 - spin_lock_irqsave(&priv_dev->lock, flags); 1716 - 1717 - priv_req = to_cdns3_request(request); 1718 - 1719 - trace_cdns3_ep_dequeue(priv_req); 1720 - 1721 - cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress); 1722 - 1723 - list_for_each_entry_safe(req, req_temp, &priv_ep->pending_req_list, 1724 - list) { 1725 - if (request == req) 1726 - goto found; 1727 - } 1728 - 1729 - list_for_each_entry_safe(req, req_temp, &priv_ep->deferred_req_list, 1730 - list) { 1731 - if (request == req) 1732 - goto found; 1733 - } 1734 - 1735 - goto not_found; 1736 - 1737 - found: 1738 - 1739 - if (priv_ep->wa1_trb == priv_req->trb) 1740 - cdns3_wa1_restore_cycle_bit(priv_ep); 1741 - 1742 - link_trb = priv_req->trb; 1743 - cdns3_move_deq_to_next_trb(priv_req); 1744 - cdns3_gadget_giveback(priv_ep, priv_req, -ECONNRESET); 1745 - 1746 - /* Update ring */ 1747 - request = cdns3_next_request(&priv_ep->deferred_req_list); 1748 - if (request) { 1749 - priv_req = to_cdns3_request(request); 1750 - 1751 - link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma + 1752 - (priv_req->start_trb * TRB_SIZE)); 1753 - link_trb->control = (link_trb->control & TRB_CYCLE) | 1754 - TRB_TYPE(TRB_LINK) | TRB_CHAIN | TRB_TOGGLE; 1755 - } else { 1756 - priv_ep->flags |= EP_UPDATE_EP_TRBADDR; 1757 - } 1758 - 1759 - not_found: 1760 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1761 - return ret; 1762 - } 1763 - 1764 - /** 1765 - * cdns3_gadget_ep_set_halt Sets/clears stall on selected endpoint 1766 - * @ep: endpoint object to set/clear stall on 1767 - * @value: 1 for set stall, 0 for clear stall 1768 - * 1769 - * Returns 0 on success, error code elsewhere 1770 - */ 1771 - int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1772 - { 1773 - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); 1774 - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; 1775 - unsigned long flags; 1776 - int ret = 0; 1777 - 1778 - if (!(priv_ep->flags & EP_ENABLED)) 1779 - return -EPERM; 1780 - 1781 - spin_lock_irqsave(&priv_dev->lock, flags); 1782 - 1783 - cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress); 1784 - if (value) { 1785 - cdns3_ep_stall_flush(priv_ep); 1786 - } else { 1787 - priv_ep->flags &= ~EP_WEDGE; 1788 - 1789 - cdns3_dbg(priv_ep->cdns3_dev, "Clear stalled endpoint %s\n", 1790 - priv_ep->name); 1791 - 1792 - writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd); 1793 - 1794 - /* wait for EPRST cleared */ 1795 - ret = cdns3_handshake(&priv_dev->regs->ep_cmd, 1796 - EP_CMD_EPRST, 0, 100); 1797 - if (unlikely(ret)) { 1798 - dev_err(priv_dev->dev, 1799 - "Clearing halt condition failed for %s\n", 1800 - priv_ep->name); 1801 - goto finish; 1802 - 1803 - } else { 1804 - priv_ep->flags &= ~EP_STALL; 1805 - } 1806 - } 1807 - 1808 - priv_ep->flags &= ~EP_PENDING_REQUEST; 1809 - finish: 1810 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1811 - 1812 - return ret; 1813 - } 1814 - 1815 - extern const struct usb_ep_ops cdns3_gadget_ep0_ops; 1816 - 1817 - static const struct usb_ep_ops cdns3_gadget_ep_ops = { 1818 - .enable = cdns3_gadget_ep_enable, 1819 - .disable = cdns3_gadget_ep_disable, 1820 - .alloc_request = cdns3_gadget_ep_alloc_request, 1821 - .free_request = cdns3_gadget_ep_free_request, 1822 - .queue = cdns3_gadget_ep_queue, 1823 - .dequeue = cdns3_gadget_ep_dequeue, 1824 - .set_halt = cdns3_gadget_ep_set_halt, 1825 - .set_wedge = cdns3_gadget_ep_set_wedge, 1826 - }; 1827 - 1828 - /** 1829 - * cdns3_gadget_get_frame Returns number of actual ITP frame 1830 - * @gadget: gadget object 1831 - * 1832 - * Returns number of actual ITP frame 1833 - */ 1834 - static int cdns3_gadget_get_frame(struct usb_gadget *gadget) 1835 - { 1836 - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); 1837 - 1838 - return readl(&priv_dev->regs->usb_itpn); 1839 - } 1840 - 1841 - int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev) 1842 - { 1843 - enum usb_device_speed speed; 1844 - 1845 - speed = cdns3_get_speed(priv_dev); 1846 - 1847 - if (speed >= USB_SPEED_SUPER) 1848 - return 0; 1849 - 1850 - /* Start driving resume signaling to indicate remote wakeup. */ 1851 - writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf); 1852 - 1853 - return 0; 1854 - } 1855 - 1856 - static int cdns3_gadget_wakeup(struct usb_gadget *gadget) 1857 - { 1858 - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); 1859 - unsigned long flags; 1860 - int ret = 0; 1861 - 1862 - spin_lock_irqsave(&priv_dev->lock, flags); 1863 - ret = __cdns3_gadget_wakeup(priv_dev); 1864 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1865 - return ret; 1866 - } 1867 - 1868 - static int cdns3_gadget_set_selfpowered(struct usb_gadget *gadget, 1869 - int is_selfpowered) 1870 - { 1871 - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); 1872 - unsigned long flags; 1873 - 1874 - spin_lock_irqsave(&priv_dev->lock, flags); 1875 - priv_dev->is_selfpowered = !!is_selfpowered; 1876 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1877 - return 0; 1878 - } 1879 - 1880 - static int cdns3_gadget_pullup(struct usb_gadget *gadget, int is_on) 1881 - { 1882 - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); 1883 - 1884 - if (is_on) 1885 - writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf); 1886 - else 1887 - writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); 1888 - 1889 - return 0; 1890 - } 1891 - 1892 - static void cdns3_gadget_config(struct cdns3_device *priv_dev) 1893 - { 1894 - struct cdns3_usb_regs __iomem *regs = priv_dev->regs; 1895 - u32 reg; 1896 - 1897 - cdns3_ep0_config(priv_dev); 1898 - 1899 - /* enable interrupts for endpoint 0 (in and out) */ 1900 - writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, &regs->ep_ien); 1901 - 1902 - /* 1903 - *Driver need modify LFPS minimal U1 Exit time for 0x00024505 revision 1904 - * of controller 1905 - */ 1906 - if (priv_dev->dev_ver == DEV_VER_TI_V1) { 1907 - reg = readl(&regs->dbg_link1); 1908 - 1909 - reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK; 1910 - reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) | 1911 - DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET; 1912 - writel(reg, &regs->dbg_link1); 1913 - } 1914 - 1915 - /* 1916 - * By default some platforms has set protected access to memory. 1917 - * This cause problem with cache, so driver restore non-secure 1918 - * access to memory. 1919 - */ 1920 - reg = readl(&regs->dma_axi_ctrl); 1921 - reg = DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) | 1922 - DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE); 1923 - writel(reg, &regs->dma_axi_ctrl); 1924 - 1925 - /* enable generic interrupt*/ 1926 - writel(USB_IEN_INIT, &regs->usb_ien); 1927 - writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, &regs->usb_conf); 1928 - 1929 - cdns3_configure_dmult(priv_dev, NULL); 1930 - 1931 - cdns3_gadget_pullup(&priv_dev->gadget, 1); 1932 - } 1933 - 1934 - /** 1935 - * cdns3_gadget_udc_start Gadget start 1936 - * @gadget: gadget object 1937 - * @driver: driver which operates on this gadget 1938 - * 1939 - * Returns 0 on success, error code elsewhere 1940 - */ 1941 - static int cdns3_gadget_udc_start(struct usb_gadget *gadget, 1942 - struct usb_gadget_driver *driver) 1943 - { 1944 - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); 1945 - unsigned long flags; 1946 - 1947 - spin_lock_irqsave(&priv_dev->lock, flags); 1948 - priv_dev->gadget_driver = driver; 1949 - cdns3_gadget_config(priv_dev); 1950 - spin_unlock_irqrestore(&priv_dev->lock, flags); 1951 - return 0; 1952 - } 1953 - 1954 - /** 1955 - * cdns3_gadget_udc_stop Stops gadget 1956 - * @gadget: gadget object 1957 - * 1958 - * Returns 0 1959 - */ 1960 - static int cdns3_gadget_udc_stop(struct usb_gadget *gadget) 1961 - { 1962 - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); 1963 - struct cdns3_endpoint *priv_ep; 1964 - u32 bEndpointAddress; 1965 - struct usb_ep *ep; 1966 - int ret = 0; 1967 - 1968 - priv_dev->gadget_driver = NULL; 1969 - 1970 - priv_dev->onchip_used_size = 0; 1971 - priv_dev->out_mem_is_allocated = 0; 1972 - priv_dev->gadget.speed = USB_SPEED_UNKNOWN; 1973 - 1974 - list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) { 1975 - priv_ep = ep_to_cdns3_ep(ep); 1976 - bEndpointAddress = priv_ep->num | priv_ep->dir; 1977 - cdns3_select_ep(priv_dev, bEndpointAddress); 1978 - writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd); 1979 - ret = cdns3_handshake(&priv_dev->regs->ep_cmd, 1980 - EP_CMD_EPRST, 0, 100); 1981 - cdns3_free_trb_pool(priv_ep); 1982 - } 1983 - 1984 - /* disable interrupt for device */ 1985 - writel(0, &priv_dev->regs->usb_ien); 1986 - writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); 1987 - 1988 - return ret; 1989 - } 1990 - 1991 - static const struct usb_gadget_ops cdns3_gadget_ops = { 1992 - .get_frame = cdns3_gadget_get_frame, 1993 - .wakeup = cdns3_gadget_wakeup, 1994 - .set_selfpowered = cdns3_gadget_set_selfpowered, 1995 - .pullup = cdns3_gadget_pullup, 1996 - .udc_start = cdns3_gadget_udc_start, 1997 - .udc_stop = cdns3_gadget_udc_stop, 1998 - .match_ep = cdns3_gadget_match_ep, 1999 - }; 2000 - 2001 - static void cdns3_free_all_eps(struct cdns3_device *priv_dev) 2002 - { 2003 - int i; 2004 - 2005 - /*ep0 OUT point to ep0 IN*/ 2006 - priv_dev->eps[16] = NULL; 2007 - 2008 - cdns3_free_trb_pool(priv_dev->eps[0]); 2009 - 2010 - for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) 2011 - if (priv_dev->eps[i]) 2012 - devm_kfree(priv_dev->dev, priv_dev->eps[i]); 2013 - } 2014 - 2015 - /** 2016 - * cdns3_init_eps Initializes software endpoints of gadget 2017 - * @cdns3: extended gadget object 2018 - * 2019 - * Returns 0 on success, error code elsewhere 2020 - */ 2021 - static int cdns3_init_eps(struct cdns3_device *priv_dev) 2022 - { 2023 - u32 ep_enabled_reg, iso_ep_reg; 2024 - struct cdns3_endpoint *priv_ep; 2025 - int ep_dir, ep_number; 2026 - u32 ep_mask; 2027 - int ret = 0; 2028 - int i; 2029 - 2030 - /* Read it from USB_CAP3 to USB_CAP5 */ 2031 - ep_enabled_reg = readl(&priv_dev->regs->usb_cap3); 2032 - iso_ep_reg = readl(&priv_dev->regs->usb_cap4); 2033 - 2034 - dev_dbg(priv_dev->dev, "Initializing non-zero endpoints\n"); 2035 - 2036 - for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) { 2037 - ep_dir = i >> 4; /* i div 16 */ 2038 - ep_number = i & 0xF; /* i % 16 */ 2039 - ep_mask = BIT(i); 2040 - 2041 - if (!(ep_enabled_reg & ep_mask)) 2042 - continue; 2043 - 2044 - if (ep_dir && !ep_number) { 2045 - priv_dev->eps[i] = priv_dev->eps[0]; 2046 - continue; 2047 - } 2048 - 2049 - priv_ep = devm_kzalloc(priv_dev->dev, sizeof(*priv_ep), 2050 - GFP_KERNEL); 2051 - if (!priv_ep) { 2052 - ret = -ENOMEM; 2053 - goto err; 2054 - } 2055 - 2056 - /* set parent of endpoint object */ 2057 - priv_ep->cdns3_dev = priv_dev; 2058 - priv_dev->eps[i] = priv_ep; 2059 - priv_ep->num = ep_number; 2060 - priv_ep->dir = ep_dir ? USB_DIR_IN : USB_DIR_OUT; 2061 - 2062 - if (!ep_number) { 2063 - ret = cdns3_init_ep0(priv_dev, priv_ep); 2064 - if (ret) { 2065 - dev_err(priv_dev->dev, "Failed to init ep0\n"); 2066 - goto err; 2067 - } 2068 - } else { 2069 - snprintf(priv_ep->name, sizeof(priv_ep->name), "ep%d%s", 2070 - ep_number, !!ep_dir ? "in" : "out"); 2071 - priv_ep->endpoint.name = priv_ep->name; 2072 - 2073 - usb_ep_set_maxpacket_limit(&priv_ep->endpoint, 2074 - CDNS3_EP_MAX_PACKET_LIMIT); 2075 - priv_ep->endpoint.max_streams = CDNS3_EP_MAX_STREAMS; 2076 - priv_ep->endpoint.ops = &cdns3_gadget_ep_ops; 2077 - if (ep_dir) 2078 - priv_ep->endpoint.caps.dir_in = 1; 2079 - else 2080 - priv_ep->endpoint.caps.dir_out = 1; 2081 - 2082 - if (iso_ep_reg & ep_mask) 2083 - priv_ep->endpoint.caps.type_iso = 1; 2084 - 2085 - priv_ep->endpoint.caps.type_bulk = 1; 2086 - priv_ep->endpoint.caps.type_int = 1; 2087 - 2088 - list_add_tail(&priv_ep->endpoint.ep_list, 2089 - &priv_dev->gadget.ep_list); 2090 - } 2091 - 2092 - priv_ep->flags = 0; 2093 - 2094 - dev_info(priv_dev->dev, "Initialized %s support: %s %s\n", 2095 - priv_ep->name, 2096 - priv_ep->endpoint.caps.type_bulk ? "BULK, INT" : "", 2097 - priv_ep->endpoint.caps.type_iso ? "ISO" : ""); 2098 - 2099 - INIT_LIST_HEAD(&priv_ep->pending_req_list); 2100 - INIT_LIST_HEAD(&priv_ep->deferred_req_list); 2101 - } 2102 - 2103 - return 0; 2104 - err: 2105 - cdns3_free_all_eps(priv_dev); 2106 - return -ENOMEM; 2107 - } 2108 - 2109 - void cdns3_gadget_exit(struct cdns3 *cdns) 2110 - { 2111 - struct cdns3_device *priv_dev; 2112 - 2113 - priv_dev = cdns->gadget_dev; 2114 - 2115 - devm_free_irq(cdns->dev, cdns->dev_irq, cdns); 2116 - 2117 - pm_runtime_mark_last_busy(cdns->dev); 2118 - pm_runtime_put_autosuspend(cdns->dev); 2119 - 2120 - usb_del_gadget_udc(&priv_dev->gadget); 2121 - 2122 - cdns3_free_all_eps(priv_dev); 2123 - 2124 - while (!list_empty(&priv_dev->aligned_buf_list)) { 2125 - struct cdns3_aligned_buf *buf; 2126 - 2127 - buf = cdns3_next_align_buf(&priv_dev->aligned_buf_list); 2128 - dma_free_coherent(priv_dev->sysdev, buf->size, 2129 - buf->buf, 2130 - buf->dma); 2131 - 2132 - list_del(&buf->list); 2133 - kfree(buf); 2134 - } 2135 - 2136 - dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf, 2137 - priv_dev->setup_dma); 2138 - 2139 - kfree(priv_dev->zlp_buf); 2140 - kfree(priv_dev); 2141 - cdns->gadget_dev = NULL; 2142 - cdns3_drd_switch_gadget(cdns, 0); 2143 - } 2144 - 2145 - static int cdns3_gadget_start(struct cdns3 *cdns) 2146 - { 2147 - struct cdns3_device *priv_dev; 2148 - u32 max_speed; 2149 - int ret; 2150 - 2151 - priv_dev = kzalloc(sizeof(*priv_dev), GFP_KERNEL); 2152 - if (!priv_dev) 2153 - return -ENOMEM; 2154 - 2155 - cdns->gadget_dev = priv_dev; 2156 - priv_dev->sysdev = cdns->dev; 2157 - priv_dev->dev = cdns->dev; 2158 - priv_dev->regs = cdns->dev_regs; 2159 - 2160 - device_property_read_u16(priv_dev->dev, "cdns,on-chip-buff-size", 2161 - &priv_dev->onchip_buffers); 2162 - 2163 - if (priv_dev->onchip_buffers <= 0) { 2164 - u32 reg = readl(&priv_dev->regs->usb_cap2); 2165 - 2166 - priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg); 2167 - } 2168 - 2169 - if (!priv_dev->onchip_buffers) 2170 - priv_dev->onchip_buffers = 256; 2171 - 2172 - max_speed = usb_get_maximum_speed(cdns->dev); 2173 - 2174 - /* Check the maximum_speed parameter */ 2175 - switch (max_speed) { 2176 - case USB_SPEED_FULL: 2177 - case USB_SPEED_HIGH: 2178 - case USB_SPEED_SUPER: 2179 - break; 2180 - default: 2181 - dev_err(cdns->dev, "invalid maximum_speed parameter %d\n", 2182 - max_speed); 2183 - /* fall through */ 2184 - case USB_SPEED_UNKNOWN: 2185 - /* default to superspeed */ 2186 - max_speed = USB_SPEED_SUPER; 2187 - break; 2188 - } 2189 - 2190 - /* fill gadget fields */ 2191 - priv_dev->gadget.max_speed = max_speed; 2192 - priv_dev->gadget.speed = USB_SPEED_UNKNOWN; 2193 - priv_dev->gadget.ops = &cdns3_gadget_ops; 2194 - priv_dev->gadget.name = "usb-ss-gadget"; 2195 - priv_dev->gadget.sg_supported = 1; 2196 - 2197 - spin_lock_init(&priv_dev->lock); 2198 - INIT_WORK(&priv_dev->pending_status_wq, 2199 - cdns3_pending_setup_status_handler); 2200 - 2201 - /* initialize endpoint container */ 2202 - INIT_LIST_HEAD(&priv_dev->gadget.ep_list); 2203 - INIT_LIST_HEAD(&priv_dev->aligned_buf_list); 2204 - 2205 - ret = cdns3_init_eps(priv_dev); 2206 - if (ret) { 2207 - dev_err(priv_dev->dev, "Failed to create endpoints\n"); 2208 - goto err1; 2209 - } 2210 - 2211 - /* allocate memory for setup packet buffer */ 2212 - priv_dev->setup_buf = dma_alloc_coherent(priv_dev->sysdev, 8, 2213 - &priv_dev->setup_dma, GFP_DMA); 2214 - if (!priv_dev->setup_buf) { 2215 - ret = -ENOMEM; 2216 - goto err2; 2217 - } 2218 - 2219 - priv_dev->dev_ver = readl(&priv_dev->regs->usb_cap6); 2220 - 2221 - dev_dbg(priv_dev->dev, "Device Controller version: %08x\n", 2222 - readl(&priv_dev->regs->usb_cap6)); 2223 - dev_dbg(priv_dev->dev, "USB Capabilities:: %08x\n", 2224 - readl(&priv_dev->regs->usb_cap1)); 2225 - dev_dbg(priv_dev->dev, "On-Chip memory cnfiguration: %08x\n", 2226 - readl(&priv_dev->regs->usb_cap2)); 2227 - 2228 - priv_dev->dev_ver = GET_DEV_BASE_VERSION(priv_dev->dev_ver); 2229 - 2230 - priv_dev->zlp_buf = kzalloc(CDNS3_EP_ZLP_BUF_SIZE, GFP_KERNEL); 2231 - if (!priv_dev->zlp_buf) { 2232 - ret = -ENOMEM; 2233 - goto err3; 2234 - } 2235 - 2236 - /* add USB gadget device */ 2237 - ret = usb_add_gadget_udc(priv_dev->dev, &priv_dev->gadget); 2238 - if (ret < 0) { 2239 - dev_err(priv_dev->dev, 2240 - "Failed to register USB device controller\n"); 2241 - goto err4; 2242 - } 2243 - 2244 - return 0; 2245 - err4: 2246 - kfree(priv_dev->zlp_buf); 2247 - err3: 2248 - dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf, 2249 - priv_dev->setup_dma); 2250 - err2: 2251 - cdns3_free_all_eps(priv_dev); 2252 - err1: 2253 - cdns->gadget_dev = NULL; 2254 - return ret; 2255 - } 2256 - 2257 - static int __cdns3_gadget_init(struct cdns3 *cdns) 2258 - { 2259 - struct cdns3_device *priv_dev; 2260 - int ret = 0; 2261 - 2262 - cdns3_drd_switch_gadget(cdns, 1); 2263 - pm_runtime_get_sync(cdns->dev); 2264 - 2265 - ret = cdns3_gadget_start(cdns); 2266 - if (ret) 2267 - return ret; 2268 - 2269 - priv_dev = cdns->gadget_dev; 2270 - ret = devm_request_threaded_irq(cdns->dev, cdns->dev_irq, 2271 - cdns3_device_irq_handler, 2272 - cdns3_device_thread_irq_handler, 2273 - IRQF_SHARED, dev_name(cdns->dev), cdns); 2274 - 2275 - if (ret) 2276 - goto err0; 2277 - 2278 - return 0; 2279 - err0: 2280 - cdns3_gadget_exit(cdns); 2281 - return ret; 2282 - } 2283 - 2284 - static int cdns3_gadget_suspend(struct cdns3 *cdns, bool do_wakeup) 2285 - { 2286 - cdns3_gadget_exit(cdns); 2287 - return 0; 2288 - } 2289 - 2290 - static int cdns3_gadget_resume(struct cdns3 *cdns, bool hibernated) 2291 - { 2292 - return cdns3_gadget_start(cdns); 2293 - } 2294 - 2295 - /** 2296 - * cdns3_gadget_init - initialize device structure 2297 - * 2298 - * cdns: cdns3 instance 2299 - * 2300 - * This function initializes the gadget. 2301 - */ 2302 - int cdns3_gadget_init(struct cdns3 *cdns) 2303 - { 2304 - struct cdns3_role_driver *rdrv; 2305 - 2306 - rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL); 2307 - if (!rdrv) 2308 - return -ENOMEM; 2309 - 2310 - rdrv->start = __cdns3_gadget_init; 2311 - rdrv->stop = cdns3_gadget_exit; 2312 - rdrv->suspend = cdns3_gadget_suspend; 2313 - rdrv->resume = cdns3_gadget_resume; 2314 - rdrv->state = CDNS3_ROLE_STATE_INACTIVE; 2315 - rdrv->name = "gadget"; 2316 - cdns->roles[CDNS3_ROLE_GADGET] = rdrv; 2317 - 2318 - return 0; 2319 - }
-1321
drivers/usb/cdns3/gadget.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * USBSS device controller driver header file 4 - * 5 - * Copyright (C) 2018-2019 Cadence. 6 - * Copyright (C) 2017-2018 NXP 7 - * 8 - * Author: Pawel Laszczak <pawell@cadence.com> 9 - * Pawel Jez <pjez@cadence.com> 10 - * Peter Chen <peter.chen@nxp.com> 11 - */ 12 - #ifndef __LINUX_CDNS3_GADGET 13 - #define __LINUX_CDNS3_GADGET 14 - #include <linux/usb/gadget.h> 15 - 16 - /* 17 - * USBSS-DEV register interface. 18 - * This corresponds to the USBSS Device Controller Interface 19 - */ 20 - 21 - /** 22 - * struct cdns3_usb_regs - device controller registers. 23 - * @usb_conf: Global Configuration Register. 24 - * @usb_sts: Global Status Register. 25 - * @usb_cmd: Global Command Register. 26 - * @usb_itpn: ITP/SOF number Register. 27 - * @usb_lpm: Global Command Register. 28 - * @usb_ien: USB Interrupt Enable Register. 29 - * @usb_ists: USB Interrupt Status Register. 30 - * @ep_sel: Endpoint Select Register. 31 - * @ep_traddr: Endpoint Transfer Ring Address Register. 32 - * @ep_cfg: Endpoint Configuration Register. 33 - * @ep_cmd: Endpoint Command Register. 34 - * @ep_sts: Endpoint Status Register. 35 - * @ep_sts_sid: Endpoint Status Register. 36 - * @ep_sts_en: Endpoint Status Register Enable. 37 - * @drbl: Doorbell Register. 38 - * @ep_ien: EP Interrupt Enable Register. 39 - * @ep_ists: EP Interrupt Status Register. 40 - * @usb_pwr: Global Power Configuration Register. 41 - * @usb_conf2: Global Configuration Register 2. 42 - * @usb_cap1: Capability Register 1. 43 - * @usb_cap2: Capability Register 2. 44 - * @usb_cap3: Capability Register 3. 45 - * @usb_cap4: Capability Register 4. 46 - * @usb_cap5: Capability Register 5. 47 - * @usb_cap6: Capability Register 6. 48 - * @usb_cpkt1: Custom Packet Register 1. 49 - * @usb_cpkt2: Custom Packet Register 2. 50 - * @usb_cpkt3: Custom Packet Register 3. 51 - * @ep_dma_ext_addr: Upper address for DMA operations Register. 52 - * @buf_addr: Address for On-chip Buffer operations Register. 53 - * @buf_data: Data for On-chip Buffer operations Register. 54 - * @buf_ctrl: On-chip Buffer Access Control Registe. 55 - * @dtrans: DMA Transfer Mode Register. 56 - * @tdl_from_trb: Source of TD Configuration Register. 57 - * @tdl_beh: TDL Behavior Configuration Register. 58 - * @ep_tdl: Endpoint TDL Register. 59 - * @tdl_beh2: TDL Behavior 2 Configuration Register. 60 - * @dma_adv_td: DMA Advance TD Configuration Register. 61 - * @reserved1: Reserved. 62 - * @cfg_regs: Configuration registers. 63 - * @reserved2: Reserved. 64 - * @dma_axi_ctrl: AXI Control register. 65 - * @dma_axi_id: AXI ID register. 66 - * @dma_axi_cap: AXI Capability register. 67 - * @dma_axi_ctrl0: AXI Control 0 register. 68 - * @dma_axi_ctrl1: AXI Control 1 register. 69 - */ 70 - struct cdns3_usb_regs { 71 - __le32 usb_conf; 72 - __le32 usb_sts; 73 - __le32 usb_cmd; 74 - __le32 usb_itpn; 75 - __le32 usb_lpm; 76 - __le32 usb_ien; 77 - __le32 usb_ists; 78 - __le32 ep_sel; 79 - __le32 ep_traddr; 80 - __le32 ep_cfg; 81 - __le32 ep_cmd; 82 - __le32 ep_sts; 83 - __le32 ep_sts_sid; 84 - __le32 ep_sts_en; 85 - __le32 drbl; 86 - __le32 ep_ien; 87 - __le32 ep_ists; 88 - __le32 usb_pwr; 89 - __le32 usb_conf2; 90 - __le32 usb_cap1; 91 - __le32 usb_cap2; 92 - __le32 usb_cap3; 93 - __le32 usb_cap4; 94 - __le32 usb_cap5; 95 - __le32 usb_cap6; 96 - __le32 usb_cpkt1; 97 - __le32 usb_cpkt2; 98 - __le32 usb_cpkt3; 99 - __le32 ep_dma_ext_addr; 100 - __le32 buf_addr; 101 - __le32 buf_data; 102 - __le32 buf_ctrl; 103 - __le32 dtrans; 104 - __le32 tdl_from_trb; 105 - __le32 tdl_beh; 106 - __le32 ep_tdl; 107 - __le32 tdl_beh2; 108 - __le32 dma_adv_td; 109 - __le32 reserved1[26]; 110 - __le32 cfg_reg1; 111 - __le32 dbg_link1; 112 - __le32 dbg_link2; 113 - __le32 cfg_regs[74]; 114 - __le32 reserved2[34]; 115 - __le32 dma_axi_ctrl; 116 - __le32 dma_axi_id; 117 - __le32 dma_axi_cap; 118 - __le32 dma_axi_ctrl0; 119 - __le32 dma_axi_ctrl1; 120 - }; 121 - 122 - /* USB_CONF - bitmasks */ 123 - /* Reset USB device configuration. */ 124 - #define USB_CONF_CFGRST BIT(0) 125 - /* Set Configuration. */ 126 - #define USB_CONF_CFGSET BIT(1) 127 - /* Disconnect USB device in SuperSpeed. */ 128 - #define USB_CONF_USB3DIS BIT(3) 129 - /* Disconnect USB device in HS/FS */ 130 - #define USB_CONF_USB2DIS BIT(4) 131 - /* Little Endian access - default */ 132 - #define USB_CONF_LENDIAN BIT(5) 133 - /* 134 - * Big Endian access. Driver assume that byte order for 135 - * SFRs access always is as Little Endian so this bit 136 - * is not used. 137 - */ 138 - #define USB_CONF_BENDIAN BIT(6) 139 - /* Device software reset. */ 140 - #define USB_CONF_SWRST BIT(7) 141 - /* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/ 142 - #define USB_CONF_DSING BIT(8) 143 - /* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */ 144 - #define USB_CONF_DMULT BIT(9) 145 - /* DMA clock turn-off enable. */ 146 - #define USB_CONF_DMAOFFEN BIT(10) 147 - /* DMA clock turn-off disable. */ 148 - #define USB_CONF_DMAOFFDS BIT(11) 149 - /* Clear Force Full Speed. */ 150 - #define USB_CONF_CFORCE_FS BIT(12) 151 - /* Set Force Full Speed. */ 152 - #define USB_CONF_SFORCE_FS BIT(13) 153 - /* Device enable. */ 154 - #define USB_CONF_DEVEN BIT(14) 155 - /* Device disable. */ 156 - #define USB_CONF_DEVDS BIT(15) 157 - /* L1 LPM state entry enable (used in HS/FS mode). */ 158 - #define USB_CONF_L1EN BIT(16) 159 - /* L1 LPM state entry disable (used in HS/FS mode). */ 160 - #define USB_CONF_L1DS BIT(17) 161 - /* USB 2.0 clock gate disable. */ 162 - #define USB_CONF_CLK2OFFEN BIT(18) 163 - /* USB 2.0 clock gate enable. */ 164 - #define USB_CONF_CLK2OFFDS BIT(19) 165 - /* L0 LPM state entry request (used in HS/FS mode). */ 166 - #define USB_CONF_LGO_L0 BIT(20) 167 - /* USB 3.0 clock gate disable. */ 168 - #define USB_CONF_CLK3OFFEN BIT(21) 169 - /* USB 3.0 clock gate enable. */ 170 - #define USB_CONF_CLK3OFFDS BIT(22) 171 - /* Bit 23 is reserved*/ 172 - /* U1 state entry enable (used in SS mode). */ 173 - #define USB_CONF_U1EN BIT(24) 174 - /* U1 state entry disable (used in SS mode). */ 175 - #define USB_CONF_U1DS BIT(25) 176 - /* U2 state entry enable (used in SS mode). */ 177 - #define USB_CONF_U2EN BIT(26) 178 - /* U2 state entry disable (used in SS mode). */ 179 - #define USB_CONF_U2DS BIT(27) 180 - /* U0 state entry request (used in SS mode). */ 181 - #define USB_CONF_LGO_U0 BIT(28) 182 - /* U1 state entry request (used in SS mode). */ 183 - #define USB_CONF_LGO_U1 BIT(29) 184 - /* U2 state entry request (used in SS mode). */ 185 - #define USB_CONF_LGO_U2 BIT(30) 186 - /* SS.Inactive state entry request (used in SS mode) */ 187 - #define USB_CONF_LGO_SSINACT BIT(31) 188 - 189 - /* USB_STS - bitmasks */ 190 - /* 191 - * Configuration status. 192 - * 1 - device is in the configured state. 193 - * 0 - device is not configured. 194 - */ 195 - #define USB_STS_CFGSTS_MASK BIT(0) 196 - #define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK) 197 - /* 198 - * On-chip memory overflow. 199 - * 0 - On-chip memory status OK. 200 - * 1 - On-chip memory overflow. 201 - */ 202 - #define USB_STS_OV_MASK BIT(1) 203 - #define USB_STS_OV(p) ((p) & USB_STS_OV_MASK) 204 - /* 205 - * SuperSpeed connection status. 206 - * 0 - USB in SuperSpeed mode disconnected. 207 - * 1 - USB in SuperSpeed mode connected. 208 - */ 209 - #define USB_STS_USB3CONS_MASK BIT(2) 210 - #define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK) 211 - /* 212 - * DMA transfer configuration status. 213 - * 0 - single request. 214 - * 1 - multiple TRB chain 215 - * Supported only for controller version < DEV_VER_V3 216 - */ 217 - #define USB_STS_DTRANS_MASK BIT(3) 218 - #define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK) 219 - /* 220 - * Device speed. 221 - * 0 - Undefined (value after reset). 222 - * 1 - Low speed 223 - * 2 - Full speed 224 - * 3 - High speed 225 - * 4 - Super speed 226 - */ 227 - #define USB_STS_USBSPEED_MASK GENMASK(6, 4) 228 - #define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4) 229 - #define USB_STS_LS (0x1 << 4) 230 - #define USB_STS_FS (0x2 << 4) 231 - #define USB_STS_HS (0x3 << 4) 232 - #define USB_STS_SS (0x4 << 4) 233 - #define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4)) 234 - #define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS) 235 - #define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS) 236 - #define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS) 237 - #define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS) 238 - /* 239 - * Endianness for SFR access. 240 - * 0 - Little Endian order (default after hardware reset). 241 - * 1 - Big Endian order 242 - */ 243 - #define USB_STS_ENDIAN_MASK BIT(7) 244 - #define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK) 245 - /* 246 - * HS/FS clock turn-off status. 247 - * 0 - hsfs clock is always on. 248 - * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled 249 - * (default after hardware reset). 250 - */ 251 - #define USB_STS_CLK2OFF_MASK BIT(8) 252 - #define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK) 253 - /* 254 - * PCLK clock turn-off status. 255 - * 0 - pclk clock is always on. 256 - * 1 - pclk clock turn-off in U3 (SS mode) is enabled 257 - * (default after hardware reset). 258 - */ 259 - #define USB_STS_CLK3OFF_MASK BIT(9) 260 - #define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK) 261 - /* 262 - * Controller in reset state. 263 - * 0 - Internal reset is active. 264 - * 1 - Internal reset is not active and controller is fully operational. 265 - */ 266 - #define USB_STS_IN_RST_MASK BIT(10) 267 - #define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK) 268 - /* 269 - * Status of the "TDL calculation basing on TRB" feature. 270 - * 0 - disabled 271 - * 1 - enabled 272 - * Supported only for DEV_VER_V2 controller version. 273 - */ 274 - #define USB_STS_TDL_TRB_ENABLED BIT(11) 275 - /* 276 - * Device enable Status. 277 - * 0 - USB device is disabled (VBUS input is disconnected from internal logic). 278 - * 1 - USB device is enabled (VBUS input is connected to the internal logic). 279 - */ 280 - #define USB_STS_DEVS_MASK BIT(14) 281 - #define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK) 282 - /* 283 - * Address status. 284 - * 0 - USB device is default state. 285 - * 1 - USB device is at least in address state. 286 - */ 287 - #define USB_STS_ADDRESSED_MASK BIT(15) 288 - #define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK) 289 - /* 290 - * L1 LPM state enable status (used in HS/FS mode). 291 - * 0 - Entering to L1 LPM state disabled. 292 - * 1 - Entering to L1 LPM state enabled. 293 - */ 294 - #define USB_STS_L1ENS_MASK BIT(16) 295 - #define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK) 296 - /* 297 - * Internal VBUS connection status (used both in HS/FS and SS mode). 298 - * 0 - internal VBUS is not detected. 299 - * 1 - internal VBUS is detected. 300 - */ 301 - #define USB_STS_VBUSS_MASK BIT(17) 302 - #define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK) 303 - /* 304 - * HS/FS LPM state (used in FS/HS mode). 305 - * 0 - L0 State 306 - * 1 - L1 State 307 - * 2 - L2 State 308 - * 3 - L3 State 309 - */ 310 - #define USB_STS_LPMST_MASK GENMASK(19, 18) 311 - #define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18)) 312 - #define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18)) 313 - #define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18)) 314 - #define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18)) 315 - /* 316 - * Disable HS status (used in FS/HS mode). 317 - * 0 - the disconnect bit for HS/FS mode is set . 318 - * 1 - the disconnect bit for HS/FS mode is not set. 319 - */ 320 - #define USB_STS_USB2CONS_MASK BIT(20) 321 - #define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK) 322 - /* 323 - * HS/FS mode connection status (used in FS/HS mode). 324 - * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled. 325 - * 1 - High Speed operations in USB2.0 (FS/HS). 326 - */ 327 - #define USB_STS_DISABLE_HS_MASK BIT(21) 328 - #define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK) 329 - /* 330 - * U1 state enable status (used in SS mode). 331 - * 0 - Entering to U1 state disabled. 332 - * 1 - Entering to U1 state enabled. 333 - */ 334 - #define USB_STS_U1ENS_MASK BIT(24) 335 - #define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK) 336 - /* 337 - * U2 state enable status (used in SS mode). 338 - * 0 - Entering to U2 state disabled. 339 - * 1 - Entering to U2 state enabled. 340 - */ 341 - #define USB_STS_U2ENS_MASK BIT(25) 342 - #define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK) 343 - /* 344 - * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current 345 - * SuperSpeed link state 346 - */ 347 - #define USB_STS_LST_MASK GENMASK(29, 26) 348 - #define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26)) 349 - #define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26)) 350 - #define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26)) 351 - #define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26)) 352 - #define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26)) 353 - #define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26)) 354 - #define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26)) 355 - #define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26)) 356 - #define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26)) 357 - #define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26)) 358 - #define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26)) 359 - #define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26)) 360 - /* 361 - * DMA clock turn-off status. 362 - * 0 - DMA clock is always on (default after hardware reset). 363 - * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled. 364 - */ 365 - #define USB_STS_DMAOFF_MASK BIT(30) 366 - #define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK) 367 - /* 368 - * SFR Endian status. 369 - * 0 - Little Endian order (default after hardware reset). 370 - * 1 - Big Endian order. 371 - */ 372 - #define USB_STS_ENDIAN2_MASK BIT(31) 373 - #define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK) 374 - 375 - /* USB_CMD - bitmasks */ 376 - /* Set Function Address */ 377 - #define USB_CMD_SET_ADDR BIT(0) 378 - /* 379 - * Function Address This field is saved to the device only when the field 380 - * SET_ADDR is set '1 ' during write to USB_CMD register. 381 - * Software is responsible for entering the address of the device during 382 - * SET_ADDRESS request service. This field should be set immediately after 383 - * the SETUP packet is decoded, and prior to confirmation of the status phase 384 - */ 385 - #define USB_CMD_FADDR_MASK GENMASK(7, 1) 386 - #define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK) 387 - /* Send Function Wake Device Notification TP (used only in SS mode). */ 388 - #define USB_CMD_SDNFW BIT(8) 389 - /* Set Test Mode (used only in HS/FS mode). */ 390 - #define USB_CMD_STMODE BIT(9) 391 - /* Test mode selector (used only in HS/FS mode) */ 392 - #define USB_STS_TMODE_SEL_MASK GENMASK(11, 10) 393 - #define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK) 394 - /* 395 - * Send Latency Tolerance Message Device Notification TP (used only 396 - * in SS mode). 397 - */ 398 - #define USB_CMD_SDNLTM BIT(12) 399 - /* Send Custom Transaction Packet (used only in SS mode) */ 400 - #define USB_CMD_SPKT BIT(13) 401 - /*Device Notification 'Function Wake' - Interface value (only in SS mode. */ 402 - #define USB_CMD_DNFW_INT_MASK GENMASK(23, 16) 403 - #define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK) 404 - /* 405 - * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0] 406 - * (used only in SS mode). 407 - */ 408 - #define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16) 409 - #define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK) 410 - 411 - /* USB_ITPN - bitmasks */ 412 - /* 413 - * ITP(SS) / SOF (HS/FS) number 414 - * In SS mode this field represent number of last ITP received from host. 415 - * In HS/FS mode this field represent number of last SOF received from host. 416 - */ 417 - #define USB_ITPN_MASK GENMASK(13, 0) 418 - #define USB_ITPN(p) ((p) & USB_ITPN_MASK) 419 - 420 - /* USB_LPM - bitmasks */ 421 - /* Host Initiated Resume Duration. */ 422 - #define USB_LPM_HIRD_MASK GENMASK(3, 0) 423 - #define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK) 424 - /* Remote Wakeup Enable (bRemoteWake). */ 425 - #define USB_LPM_BRW BIT(4) 426 - 427 - /* USB_IEN - bitmasks */ 428 - /* SS connection interrupt enable */ 429 - #define USB_IEN_CONIEN BIT(0) 430 - /* SS disconnection interrupt enable. */ 431 - #define USB_IEN_DISIEN BIT(1) 432 - /* USB SS warm reset interrupt enable. */ 433 - #define USB_IEN_UWRESIEN BIT(2) 434 - /* USB SS hot reset interrupt enable */ 435 - #define USB_IEN_UHRESIEN BIT(3) 436 - /* SS link U3 state enter interrupt enable (suspend).*/ 437 - #define USB_IEN_U3ENTIEN BIT(4) 438 - /* SS link U3 state exit interrupt enable (wakeup). */ 439 - #define USB_IEN_U3EXTIEN BIT(5) 440 - /* SS link U2 state enter interrupt enable.*/ 441 - #define USB_IEN_U2ENTIEN BIT(6) 442 - /* SS link U2 state exit interrupt enable.*/ 443 - #define USB_IEN_U2EXTIEN BIT(7) 444 - /* SS link U1 state enter interrupt enable.*/ 445 - #define USB_IEN_U1ENTIEN BIT(8) 446 - /* SS link U1 state exit interrupt enable.*/ 447 - #define USB_IEN_U1EXTIEN BIT(9) 448 - /* ITP/SOF packet detected interrupt enable.*/ 449 - #define USB_IEN_ITPIEN BIT(10) 450 - /* Wakeup interrupt enable.*/ 451 - #define USB_IEN_WAKEIEN BIT(11) 452 - /* Send Custom Packet interrupt enable.*/ 453 - #define USB_IEN_SPKTIEN BIT(12) 454 - /* HS/FS mode connection interrupt enable.*/ 455 - #define USB_IEN_CON2IEN BIT(16) 456 - /* HS/FS mode disconnection interrupt enable.*/ 457 - #define USB_IEN_DIS2IEN BIT(17) 458 - /* USB reset (HS/FS mode) interrupt enable.*/ 459 - #define USB_IEN_U2RESIEN BIT(18) 460 - /* LPM L2 state enter interrupt enable.*/ 461 - #define USB_IEN_L2ENTIEN BIT(20) 462 - /* LPM L2 state exit interrupt enable.*/ 463 - #define USB_IEN_L2EXTIEN BIT(21) 464 - /* LPM L1 state enter interrupt enable.*/ 465 - #define USB_IEN_L1ENTIEN BIT(24) 466 - /* LPM L1 state exit interrupt enable.*/ 467 - #define USB_IEN_L1EXTIEN BIT(25) 468 - /* Configuration reset interrupt enable.*/ 469 - #define USB_IEN_CFGRESIEN BIT(26) 470 - /* Start of the USB SS warm reset interrupt enable.*/ 471 - #define USB_IEN_UWRESSIEN BIT(28) 472 - /* End of the USB SS warm reset interrupt enable.*/ 473 - #define USB_IEN_UWRESEIEN BIT(29) 474 - 475 - #define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \ 476 - | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \ 477 - | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \ 478 - | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN) 479 - 480 - /* USB_ISTS - bitmasks */ 481 - /* SS Connection detected. */ 482 - #define USB_ISTS_CONI BIT(0) 483 - /* SS Disconnection detected. */ 484 - #define USB_ISTS_DISI BIT(1) 485 - /* UUSB warm reset detectede. */ 486 - #define USB_ISTS_UWRESI BIT(2) 487 - /* USB hot reset detected. */ 488 - #define USB_ISTS_UHRESI BIT(3) 489 - /* U3 link state enter detected (suspend).*/ 490 - #define USB_ISTS_U3ENTI BIT(4) 491 - /* U3 link state exit detected (wakeup). */ 492 - #define USB_ISTS_U3EXTI BIT(5) 493 - /* U2 link state enter detected.*/ 494 - #define USB_ISTS_U2ENTI BIT(6) 495 - /* U2 link state exit detected.*/ 496 - #define USB_ISTS_U2EXTI BIT(7) 497 - /* U1 link state enter detected.*/ 498 - #define USB_ISTS_U1ENTI BIT(8) 499 - /* U1 link state exit detected.*/ 500 - #define USB_ISTS_U1EXTI BIT(9) 501 - /* ITP/SOF packet detected.*/ 502 - #define USB_ISTS_ITPI BIT(10) 503 - /* Wakeup detected.*/ 504 - #define USB_ISTS_WAKEI BIT(11) 505 - /* Send Custom Packet detected.*/ 506 - #define USB_ISTS_SPKTI BIT(12) 507 - /* HS/FS mode connection detected.*/ 508 - #define USB_ISTS_CON2I BIT(16) 509 - /* HS/FS mode disconnection detected.*/ 510 - #define USB_ISTS_DIS2I BIT(17) 511 - /* USB reset (HS/FS mode) detected.*/ 512 - #define USB_ISTS_U2RESI BIT(18) 513 - /* LPM L2 state enter detected.*/ 514 - #define USB_ISTS_L2ENTI BIT(20) 515 - /* LPM L2 state exit detected.*/ 516 - #define USB_ISTS_L2EXTI BIT(21) 517 - /* LPM L1 state enter detected.*/ 518 - #define USB_ISTS_L1ENTI BIT(24) 519 - /* LPM L1 state exit detected.*/ 520 - #define USB_ISTS_L1EXTI BIT(25) 521 - /* USB configuration reset detected.*/ 522 - #define USB_ISTS_CFGRESI BIT(26) 523 - /* Start of the USB warm reset detected.*/ 524 - #define USB_ISTS_UWRESSI BIT(28) 525 - /* End of the USB warm reset detected.*/ 526 - #define USB_ISTS_UWRESEI BIT(29) 527 - 528 - /* USB_SEL - bitmasks */ 529 - #define EP_SEL_EPNO_MASK GENMASK(3, 0) 530 - /* Endpoint number. */ 531 - #define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK) 532 - /* Endpoint direction bit - 0 - OUT, 1 - IN. */ 533 - #define EP_SEL_DIR BIT(7) 534 - 535 - #define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR) 536 - #define select_ep_out (EP_SEL_EPNO(p)) 537 - 538 - /* EP_TRADDR - bitmasks */ 539 - /* Transfer Ring address. */ 540 - #define EP_TRADDR_TRADDR(p) ((p)) 541 - 542 - /* EP_CFG - bitmasks */ 543 - /* Endpoint enable */ 544 - #define EP_CFG_ENABLE BIT(0) 545 - /* 546 - * Endpoint type. 547 - * 1 - isochronous 548 - * 2 - bulk 549 - * 3 - interrupt 550 - */ 551 - #define EP_CFG_EPTYPE_MASK GENMASK(2, 1) 552 - #define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK) 553 - /* Stream support enable (only in SS mode). */ 554 - #define EP_CFG_STREAM_EN BIT(3) 555 - /* TDL check (only in SS mode for BULK EP). */ 556 - #define EP_CFG_TDL_CHK BIT(4) 557 - /* SID check (only in SS mode for BULK OUT EP). */ 558 - #define EP_CFG_SID_CHK BIT(5) 559 - /* DMA transfer endianness. */ 560 - #define EP_CFG_EPENDIAN BIT(7) 561 - /* Max burst size (used only in SS mode). */ 562 - #define EP_CFG_MAXBURST_MASK GENMASK(11, 8) 563 - #define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK) 564 - /* ISO max burst. */ 565 - #define EP_CFG_MULT_MASK GENMASK(15, 14) 566 - #define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK) 567 - /* ISO max burst. */ 568 - #define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16) 569 - #define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK) 570 - /* Max number of buffered packets. */ 571 - #define EP_CFG_BUFFERING_MASK GENMASK(31, 27) 572 - #define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK) 573 - 574 - /* EP_CMD - bitmasks */ 575 - /* Endpoint reset. */ 576 - #define EP_CMD_EPRST BIT(0) 577 - /* Endpoint STALL set. */ 578 - #define EP_CMD_SSTALL BIT(1) 579 - /* Endpoint STALL clear. */ 580 - #define EP_CMD_CSTALL BIT(2) 581 - /* Send ERDY TP. */ 582 - #define EP_CMD_ERDY BIT(3) 583 - /* Request complete. */ 584 - #define EP_CMD_REQ_CMPL BIT(5) 585 - /* Transfer descriptor ready. */ 586 - #define EP_CMD_DRDY BIT(6) 587 - /* Data flush. */ 588 - #define EP_CMD_DFLUSH BIT(7) 589 - /* 590 - * Transfer Descriptor Length write (used only for Bulk Stream capable 591 - * endpoints in SS mode). 592 - * Bit Removed from DEV_VER_V3 controller version. 593 - */ 594 - #define EP_CMD_STDL BIT(8) 595 - /* 596 - * Transfer Descriptor Length (used only in SS mode for bulk endpoints). 597 - * Bits Removed from DEV_VER_V3 controller version. 598 - */ 599 - #define EP_CMD_TDL_MASK GENMASK(15, 9) 600 - #define EP_CMD_TDL(p) (((p) << 9) & EP_CMD_TDL_MASK) 601 - /* ERDY Stream ID value (used in SS mode). */ 602 - #define EP_CMD_ERDY_SID_MASK GENMASK(31, 16) 603 - #define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_SID_MASK) 604 - 605 - /* EP_STS - bitmasks */ 606 - /* Setup transfer complete. */ 607 - #define EP_STS_SETUP BIT(0) 608 - /* Endpoint STALL status. */ 609 - #define EP_STS_STALL(p) ((p) & BIT(1)) 610 - /* Interrupt On Complete. */ 611 - #define EP_STS_IOC BIT(2) 612 - /* Interrupt on Short Packet. */ 613 - #define EP_STS_ISP BIT(3) 614 - /* Transfer descriptor missing. */ 615 - #define EP_STS_DESCMIS BIT(4) 616 - /* Stream Rejected (used only in SS mode) */ 617 - #define EP_STS_STREAMR BIT(5) 618 - /* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */ 619 - #define EP_STS_MD_EXIT BIT(6) 620 - /* TRB error. */ 621 - #define EP_STS_TRBERR BIT(7) 622 - /* Not ready (used only in SS mode). */ 623 - #define EP_STS_NRDY BIT(8) 624 - /* DMA busy bit. */ 625 - #define EP_STS_DBUSY BIT(9) 626 - /* Endpoint Buffer Empty */ 627 - #define EP_STS_BUFFEMPTY(p) ((p) & BIT(10)) 628 - /* Current Cycle Status */ 629 - #define EP_STS_CCS(p) ((p) & BIT(11)) 630 - /* Prime (used only in SS mode. */ 631 - #define EP_STS_PRIME BIT(12) 632 - /* Stream error (used only in SS mode). */ 633 - #define EP_STS_SIDERR BIT(13) 634 - /* OUT size mismatch. */ 635 - #define EP_STS_OUTSMM BIT(14) 636 - /* ISO transmission error. */ 637 - #define EP_STS_ISOERR BIT(15) 638 - /* Host Packet Pending (only for SS mode). */ 639 - #define EP_STS_HOSTPP(p) ((p) & BIT(16)) 640 - /* Stream Protocol State Machine State (only for Bulk stream endpoints). */ 641 - #define EP_STS_SPSMST_MASK GENMASK(18, 17) 642 - #define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17) 643 - #define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17) 644 - #define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17) 645 - #define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17) 646 - /* Interrupt On Transfer complete. */ 647 - #define EP_STS_IOT BIT(19) 648 - /* OUT queue endpoint number. */ 649 - #define EP_STS_OUTQ_NO_MASK GENMASK(27, 24) 650 - #define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24) 651 - /* OUT queue valid flag. */ 652 - #define EP_STS_OUTQ_VAL_MASK BIT(28) 653 - #define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK) 654 - /* SETUP WAIT. */ 655 - #define EP_STS_STPWAIT BIT(31) 656 - 657 - /* EP_STS_SID - bitmasks */ 658 - /* Stream ID (used only in SS mode). */ 659 - #define EP_STS_SID_MASK GENMASK(15, 0) 660 - #define EP_STS_SID(p) ((p) & EP_STS_SID_MASK) 661 - 662 - /* EP_STS_EN - bitmasks */ 663 - /* SETUP interrupt enable. */ 664 - #define EP_STS_EN_SETUPEN BIT(0) 665 - /* OUT transfer missing descriptor enable. */ 666 - #define EP_STS_EN_DESCMISEN BIT(4) 667 - /* Stream Rejected enable. */ 668 - #define EP_STS_EN_STREAMREN BIT(5) 669 - /* Move Data Exit enable.*/ 670 - #define EP_STS_EN_MD_EXITEN BIT(6) 671 - /* TRB enable. */ 672 - #define EP_STS_EN_TRBERREN BIT(7) 673 - /* NRDY enable. */ 674 - #define EP_STS_EN_NRDYEN BIT(8) 675 - /* Prime enable. */ 676 - #define EP_STS_EN_PRIMEEEN BIT(12) 677 - /* Stream error enable. */ 678 - #define EP_STS_EN_SIDERREN BIT(13) 679 - /* OUT size mismatch enable. */ 680 - #define EP_STS_EN_OUTSMMEN BIT(14) 681 - /* ISO transmission error enable. */ 682 - #define EP_STS_EN_ISOERREN BIT(15) 683 - /* Interrupt on Transmission complete enable. */ 684 - #define EP_STS_EN_IOTEN BIT(19) 685 - /* Setup Wait interrupt enable. */ 686 - #define EP_STS_EN_STPWAITEN BIT(31) 687 - 688 - /* DRBL- bitmasks */ 689 - #define DB_VALUE_BY_INDEX(index) (1 << (index)) 690 - #define DB_VALUE_EP0_OUT BIT(0) 691 - #define DB_VALUE_EP0_IN BIT(16) 692 - 693 - /* EP_IEN - bitmasks */ 694 - #define EP_IEN(index) (1 << (index)) 695 - #define EP_IEN_EP_OUT0 BIT(0) 696 - #define EP_IEN_EP_IN0 BIT(16) 697 - 698 - /* EP_ISTS - bitmasks */ 699 - #define EP_ISTS(index) (1 << (index)) 700 - #define EP_ISTS_EP_OUT0 BIT(0) 701 - #define EP_ISTS_EP_IN0 BIT(16) 702 - 703 - /* USB_PWR- bitmasks */ 704 - /*Power Shut Off capability enable*/ 705 - #define PUSB_PWR_PSO_EN BIT(0) 706 - /*Power Shut Off capability disable*/ 707 - #define PUSB_PWR_PSO_DS BIT(1) 708 - /* 709 - * Enables turning-off Reference Clock. 710 - * This bit is optional and implemented only when support for OTG is 711 - * implemented (indicated by OTG_READY bit set to '1'). 712 - */ 713 - #define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8) 714 - /* 715 - * Status bit indicating that operation required by STB_CLK_SWITCH_EN write 716 - * is completed 717 - */ 718 - #define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9) 719 - /* This bit informs if Fast Registers Access is enabled. */ 720 - #define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30) 721 - /* Fast Registers Access Enable. */ 722 - #define PUSB_PWR_FST_REG_ACCESS BIT(31) 723 - 724 - /* USB_CONF2- bitmasks */ 725 - /* 726 - * Writing 1 disables TDL calculation basing on TRB feature in controller 727 - * for DMULT mode. 728 - * Bit supported only for DEV_VER_V2 version. 729 - */ 730 - #define USB_CONF2_DIS_TDL_TRB BIT(1) 731 - /* 732 - * Writing 1 enables TDL calculation basing on TRB feature in controller 733 - * for DMULT mode. 734 - * Bit supported only for DEV_VER_V2 version. 735 - */ 736 - #define USB_CONF2_EN_TDL_TRB BIT(2) 737 - 738 - /* USB_CAP1- bitmasks */ 739 - /* 740 - * SFR Interface type 741 - * These field reflects type of SFR interface implemented: 742 - * 0x0 - OCP 743 - * 0x1 - AHB, 744 - * 0x2 - PLB 745 - * 0x3 - AXI 746 - * 0x4-0xF - reserved 747 - */ 748 - #define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0) 749 - #define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0) 750 - #define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1) 751 - #define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2) 752 - #define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3) 753 - /* 754 - * SFR Interface width 755 - * These field reflects width of SFR interface implemented: 756 - * 0x0 - 8 bit interface, 757 - * 0x1 - 16 bit interface, 758 - * 0x2 - 32 bit interface 759 - * 0x3 - 64 bit interface 760 - * 0x4-0xF - reserved 761 - */ 762 - #define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4) 763 - #define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4)) 764 - #define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4)) 765 - #define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4)) 766 - #define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4)) 767 - /* 768 - * DMA Interface type 769 - * These field reflects type of DMA interface implemented: 770 - * 0x0 - OCP 771 - * 0x1 - AHB, 772 - * 0x2 - PLB 773 - * 0x3 - AXI 774 - * 0x4-0xF - reserved 775 - */ 776 - #define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8) 777 - #define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8)) 778 - #define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8)) 779 - #define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8)) 780 - #define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8)) 781 - /* 782 - * DMA Interface width 783 - * These field reflects width of DMA interface implemented: 784 - * 0x0 - reserved, 785 - * 0x1 - reserved, 786 - * 0x2 - 32 bit interface 787 - * 0x3 - 64 bit interface 788 - * 0x4-0xF - reserved 789 - */ 790 - #define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12) 791 - #define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12)) 792 - #define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12)) 793 - /* 794 - * USB3 PHY Interface type 795 - * These field reflects type of USB3 PHY interface implemented: 796 - * 0x0 - USB PIPE, 797 - * 0x1 - RMMI, 798 - * 0x2-0xF - reserved 799 - */ 800 - #define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16) 801 - #define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16)) 802 - #define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16)) 803 - /* 804 - * USB3 PHY Interface width 805 - * These field reflects width of USB3 PHY interface implemented: 806 - * 0x0 - 8 bit PIPE interface, 807 - * 0x1 - 16 bit PIPE interface, 808 - * 0x2 - 32 bit PIPE interface, 809 - * 0x3 - 64 bit PIPE interface 810 - * 0x4-0xF - reserved 811 - * Note: When SSIC interface is implemented this field shows the width of 812 - * internal PIPE interface. The RMMI interface is always 20bit wide. 813 - */ 814 - #define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20) 815 - #define DEV_U3PHY_WIDTH_8(p) \ 816 - (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20)) 817 - #define DEV_U3PHY_WIDTH_16(p) \ 818 - (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16)) 819 - #define DEV_U3PHY_WIDTH_32(p) \ 820 - (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20)) 821 - #define DEV_U3PHY_WIDTH_64(p) \ 822 - (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16)) 823 - 824 - /* 825 - * USB2 PHY Interface enable 826 - * These field informs if USB2 PHY interface is implemented: 827 - * 0x0 - interface NOT implemented, 828 - * 0x1 - interface implemented 829 - */ 830 - #define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24)) 831 - /* 832 - * USB2 PHY Interface type 833 - * These field reflects type of USB2 PHY interface implemented: 834 - * 0x0 - UTMI, 835 - * 0x1 - ULPI 836 - */ 837 - #define DEV_U2PHY_ULPI(p) ((p) & BIT(25)) 838 - /* 839 - * USB2 PHY Interface width 840 - * These field reflects width of USB2 PHY interface implemented: 841 - * 0x0 - 8 bit interface, 842 - * 0x1 - 16 bit interface, 843 - * Note: The ULPI interface is always 8bit wide. 844 - */ 845 - #define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26)) 846 - /* 847 - * OTG Ready 848 - * 0x0 - pure device mode 849 - * 0x1 - some features and ports for CDNS USB OTG controller are implemented. 850 - */ 851 - #define USB_CAP1_OTG_READY(p) ((p) & BIT(27)) 852 - 853 - /* 854 - * When set, indicates that controller supports automatic internal TDL 855 - * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode 856 - * Supported only for DEV_VER_V2 controller version. 857 - */ 858 - #define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28)) 859 - 860 - /* USB_CAP2- bitmasks */ 861 - /* 862 - * The actual size of the connected On-chip RAM memory in kB: 863 - * - 0 means 256 kB (max supported mem size) 864 - * - value other than 0 reflects the mem size in kB 865 - */ 866 - #define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0)) 867 - /* 868 - * Max supported mem size 869 - * These field reflects width of on-chip RAM address bus width, 870 - * which determines max supported mem size: 871 - * 0x0-0x7 - reserved, 872 - * 0x8 - support for 4kB mem, 873 - * 0x9 - support for 8kB mem, 874 - * 0xA - support for 16kB mem, 875 - * 0xB - support for 32kB mem, 876 - * 0xC - support for 64kB mem, 877 - * 0xD - support for 128kB mem, 878 - * 0xE - support for 256kB mem, 879 - * 0xF - reserved 880 - */ 881 - #define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8)) 882 - 883 - /* USB_CAP3- bitmasks */ 884 - #define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index))) 885 - 886 - /* USB_CAP4- bitmasks */ 887 - #define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index))) 888 - 889 - /* USB_CAP5- bitmasks */ 890 - #define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index))) 891 - 892 - /* USB_CAP6- bitmasks */ 893 - /* The USBSS-DEV Controller Internal build number. */ 894 - #define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0)) 895 - /* The USBSS-DEV Controller version number. */ 896 - #define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24)) 897 - 898 - #define DEV_VER_NXP_V1 0x00024502 899 - #define DEV_VER_TI_V1 0x00024509 900 - #define DEV_VER_V2 0x0002450C 901 - #define DEV_VER_V3 0x0002450d 902 - 903 - /* DBG_LINK1- bitmasks */ 904 - /* 905 - * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum 906 - * time required for decoding the received LFPS as an LFPS.U1_Exit. 907 - */ 908 - #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0)) 909 - /* 910 - * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for 911 - * phytxelecidle deassertion when LFPS.U1_Exit 912 - */ 913 - #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8) 914 - #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8)) 915 - /* 916 - * RXDET_BREAK_DIS value This parameter configures terminating the Far-end 917 - * Receiver termination detection sequence: 918 - * 0: it is possible that USBSS_DEV will terminate Farend receiver 919 - * termination detection sequence 920 - * 1: USBSS_DEV will not terminate Far-end receiver termination 921 - * detection sequence 922 - */ 923 - #define DBG_LINK1_RXDET_BREAK_DIS BIT(16) 924 - /* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */ 925 - #define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17)) 926 - /* 927 - * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the 928 - * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically 929 - * cleared. Writing '0' has no effect 930 - */ 931 - #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24) 932 - /* 933 - * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the 934 - * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically 935 - * cleared. Writing '0' has no effect 936 - */ 937 - #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25) 938 - /* 939 - * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes 940 - * the RXDET_BREAK_DIS field value to the device. This bit is automatically 941 - * cleared. Writing '0' has no effect 942 - */ 943 - #define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26) 944 - /* 945 - * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes 946 - * the LFPS_GEN_PING field value to the device. This bit is automatically 947 - * cleared. Writing '0' has no effect." 948 - */ 949 - #define DBG_LINK1_LFPS_GEN_PING_SET BIT(27) 950 - 951 - /* DMA_AXI_CTRL- bitmasks */ 952 - /* The mawprot pin configuration. */ 953 - #define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0)) 954 - /* The marprot pin configuration. */ 955 - #define DMA_AXI_CTRL_MAWPROT(p) (((p) < 16) & GENMASK(18, 16)) 956 - #define DMA_AXI_CTRL_NON_SECURE 0x02 957 - 958 - #define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget)) 959 - 960 - #define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint)) 961 - 962 - /*-------------------------------------------------------------------------*/ 963 - /* 964 - * USBSS-DEV DMA interface. 965 - */ 966 - #define TRBS_PER_SEGMENT 40 967 - 968 - #define ISO_MAX_INTERVAL 10 969 - 970 - #if TRBS_PER_SEGMENT < 2 971 - #error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2." 972 - #endif 973 - 974 - /* 975 - *Only for ISOC endpoints - maximum number of TRBs is calculated as 976 - * pow(2, bInterval-1) * number of usb requests. It is limitation made by 977 - * driver to save memory. Controller must prepare TRB for each ITP even 978 - * if bInterval > 1. It's the reason why driver needs so many TRBs for 979 - * isochronous endpoints. 980 - */ 981 - #define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8) 982 - 983 - #define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \ 984 - TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT) 985 - /** 986 - * struct cdns3_trb - represent Transfer Descriptor block. 987 - * @buffer: pointer to buffer data 988 - * @length: length of data 989 - * @control: control flags. 990 - * 991 - * This structure describes transfer block serviced by DMA module. 992 - */ 993 - struct cdns3_trb { 994 - __le32 buffer; 995 - __le32 length; 996 - __le32 control; 997 - }; 998 - 999 - #define TRB_SIZE (sizeof(struct cdns3_trb)) 1000 - #define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT) 1001 - #define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT) 1002 - #define TRB_CTRL_RING_SIZE (TRB_SIZE * 2) 1003 - 1004 - /* TRB bit mask */ 1005 - #define TRB_TYPE_BITMASK GENMASK(15, 10) 1006 - #define TRB_TYPE(p) ((p) << 10) 1007 - #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1008 - 1009 - /* TRB type IDs */ 1010 - /* bulk, interrupt, isoc , and control data stage */ 1011 - #define TRB_NORMAL 1 1012 - /* TRB for linking ring segments */ 1013 - #define TRB_LINK 6 1014 - 1015 - /* Cycle bit - indicates TRB ownership by driver or hw*/ 1016 - #define TRB_CYCLE BIT(0) 1017 - /* 1018 - * When set to '1', the device will toggle its interpretation of the Cycle bit 1019 - */ 1020 - #define TRB_TOGGLE BIT(1) 1021 - 1022 - /* 1023 - * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was 1024 - * processed while USB short packet was received. No more buffers defined by 1025 - * the TD will be used. DMA will automatically advance to next TD. 1026 - * - Shall be set to 0 by Software when putting TRB on the Transfer Ring 1027 - * - Shall be set to 1 by Controller when Short Packet condition for this TRB 1028 - * is detected independent if ISP is set or not. 1029 - */ 1030 - #define TRB_SP BIT(1) 1031 - 1032 - /* Interrupt on short packet*/ 1033 - #define TRB_ISP BIT(2) 1034 - /*Setting this bit enables FIFO DMA operation mode*/ 1035 - #define TRB_FIFO_MODE BIT(3) 1036 - /* Set PCIe no snoop attribute */ 1037 - #define TRB_CHAIN BIT(4) 1038 - /* Interrupt on completion */ 1039 - #define TRB_IOC BIT(5) 1040 - 1041 - /* stream ID bitmasks. */ 1042 - #define TRB_STREAM_ID(p) ((p) & GENMASK(31, 16)) 1043 - 1044 - /* Size of TD expressed in USB packets for HS/FS mode. */ 1045 - #define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16)) 1046 - #define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16) 1047 - 1048 - /* transfer_len bitmasks. */ 1049 - #define TRB_LEN(p) ((p) & GENMASK(16, 0)) 1050 - 1051 - /* Size of TD expressed in USB packets for SS mode. */ 1052 - #define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17)) 1053 - #define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17) 1054 - 1055 - /* transfer_len bitmasks - bits 31:24 */ 1056 - #define TRB_BURST_LEN(p) (((p) << 24) & GENMASK(31, 24)) 1057 - #define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24) 1058 - 1059 - /* Data buffer pointer bitmasks*/ 1060 - #define TRB_BUFFER(p) ((p) & GENMASK(31, 0)) 1061 - 1062 - /*-------------------------------------------------------------------------*/ 1063 - /* Driver numeric constants */ 1064 - 1065 - /* Such declaration should be added to ch9.h */ 1066 - #define USB_DEVICE_MAX_ADDRESS 127 1067 - 1068 - /* Endpoint init values */ 1069 - #define CDNS3_EP_MAX_PACKET_LIMIT 1024 1070 - #define CDNS3_EP_MAX_STREAMS 15 1071 - #define CDNS3_EP0_MAX_PACKET_LIMIT 512 1072 - 1073 - /* All endpoints including EP0 */ 1074 - #define CDNS3_ENDPOINTS_MAX_COUNT 32 1075 - #define CDNS3_EP_ZLP_BUF_SIZE 1024 1076 - 1077 - #define CDNS3_EP_BUF_SIZE 2 /* KB */ 1078 - #define CDNS3_EP_ISO_HS_MULT 3 1079 - #define CDNS3_EP_ISO_SS_BURST 3 1080 - #define CDNS3_MAX_NUM_DESCMISS_BUF 32 1081 - #define CDNS3_DESCMIS_BUF_SIZE 2048 /* Bytes */ 1082 - /*-------------------------------------------------------------------------*/ 1083 - /* Used structs */ 1084 - 1085 - struct cdns3_device; 1086 - 1087 - /** 1088 - * struct cdns3_endpoint - extended device side representation of USB endpoint. 1089 - * @endpoint: usb endpoint 1090 - * @pending_req_list: list of requests queuing on transfer ring. 1091 - * @deferred_req_list: list of requests waiting for queuing on transfer ring. 1092 - * @trb_pool: transfer ring - array of transaction buffers 1093 - * @trb_pool_dma: dma address of transfer ring 1094 - * @cdns3_dev: device associated with this endpoint 1095 - * @name: a human readable name e.g. ep1out 1096 - * @flags: specify the current state of endpoint 1097 - * @dir: endpoint direction 1098 - * @num: endpoint number (1 - 15) 1099 - * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 1100 - * @interval: interval between packets used for ISOC endpoint. 1101 - * @free_trbs: number of free TRBs in transfer ring 1102 - * @num_trbs: number of all TRBs in transfer ring 1103 - * @pcs: producer cycle state 1104 - * @ccs: consumer cycle state 1105 - * @enqueue: enqueue index in transfer ring 1106 - * @dequeue: dequeue index in transfer ring 1107 - * @trb_burst_size: number of burst used in trb. 1108 - */ 1109 - struct cdns3_endpoint { 1110 - struct usb_ep endpoint; 1111 - struct list_head pending_req_list; 1112 - struct list_head deferred_req_list; 1113 - 1114 - struct cdns3_trb *trb_pool; 1115 - dma_addr_t trb_pool_dma; 1116 - 1117 - struct cdns3_device *cdns3_dev; 1118 - char name[20]; 1119 - 1120 - #define EP_ENABLED BIT(0) 1121 - #define EP_STALL BIT(1) 1122 - #define EP_WEDGE BIT(2) 1123 - #define EP_TRANSFER_STARTED BIT(3) 1124 - #define EP_UPDATE_EP_TRBADDR BIT(4) 1125 - #define EP_PENDING_REQUEST BIT(5) 1126 - #define EP_RING_FULL BIT(6) 1127 - #define EP_CLAIMED BIT(7) 1128 - #define EP_DEFERRED_DRDY BIT(8) 1129 - #define EP_QUIRK_ISO_OUT_EN BIT(9) 1130 - u32 flags; 1131 - 1132 - u8 dir; 1133 - u8 num; 1134 - u8 type; 1135 - int interval; 1136 - 1137 - int free_trbs; 1138 - int num_trbs; 1139 - u8 pcs; 1140 - u8 ccs; 1141 - int enqueue; 1142 - int dequeue; 1143 - u8 trb_burst_size; 1144 - 1145 - unsigned int wa1_set:1; 1146 - struct cdns3_trb *wa1_trb; 1147 - unsigned int wa1_trb_index; 1148 - unsigned int wa1_cycle_bit:1; 1149 - }; 1150 - 1151 - /** 1152 - * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer 1153 - * @buf: aligned to 8 bytes data buffer. Buffer address used in 1154 - * TRB shall be aligned to 8. 1155 - * @dma: dma address 1156 - * @size: size of buffer 1157 - * @in_use: inform if this buffer is associated with usb_request 1158 - * @list: used to adding instance of this object to list 1159 - */ 1160 - struct cdns3_aligned_buf { 1161 - void *buf; 1162 - dma_addr_t dma; 1163 - u32 size; 1164 - int in_use:1; 1165 - struct list_head list; 1166 - }; 1167 - 1168 - /** 1169 - * struct cdns3_request - extended device side representation of usb_request 1170 - * object . 1171 - * @request: generic usb_request object describing single I/O request. 1172 - * @priv_ep: extended representation of usb_ep object 1173 - * @trb: the first TRB association with this request 1174 - * @start_trb: number of the first TRB in transfer ring 1175 - * @end_trb: number of the last TRB in transfer ring 1176 - * @aligned_buf: object holds information about aligned buffer associated whit 1177 - * this endpoint 1178 - * @flags: flag specifying special usage of request 1179 - */ 1180 - struct cdns3_request { 1181 - struct usb_request request; 1182 - struct cdns3_endpoint *priv_ep; 1183 - struct cdns3_trb *trb; 1184 - int start_trb; 1185 - int end_trb; 1186 - struct cdns3_aligned_buf *aligned_buf; 1187 - #define REQUEST_PENDING BIT(0) 1188 - #define REQUEST_INTERNAL BIT(1) 1189 - #define REQUEST_INTERNAL_CH BIT(2) 1190 - #define REQUEST_ZLP BIT(3) 1191 - #define REQUEST_UNALIGNED BIT(4) 1192 - u32 flags; 1193 - struct list_head list; 1194 - }; 1195 - 1196 - #define to_cdns3_request(r) (container_of(r, struct cdns3_request, request)) 1197 - 1198 - /*Stages used during enumeration process.*/ 1199 - #define CDNS3_SETUP_STAGE 0x0 1200 - #define CDNS3_DATA_STAGE 0x1 1201 - #define CDNS3_STATUS_STAGE 0x2 1202 - 1203 - /** 1204 - * struct cdns3_device - represent USB device. 1205 - * @dev: pointer to device structure associated whit this controller 1206 - * @sysdev: pointer to the DMA capable device 1207 - * @gadget: device side representation of the peripheral controller 1208 - * @gadget_driver: pointer to the gadget driver 1209 - * @dev_ver: device controller version. 1210 - * @lock: for synchronizing 1211 - * @regs: base address for device side registers 1212 - * @setup_buf: used while processing usb control requests 1213 - * @setup_dma: dma address for setup_buf 1214 - * @zlp_buf - zlp buffer 1215 - * @ep0_stage: ep0 stage during enumeration process. 1216 - * @ep0_data_dir: direction for control transfer 1217 - * @eps: array of pointers to all endpoints with exclusion ep0 1218 - * @aligned_buf_list: list of aligned buffers internally allocated by driver 1219 - * @run_garbage_colector: infroms that at least one element of aligned_buf_list 1220 - * can be freed 1221 - * @selected_ep: actually selected endpoint. It's used only to improve 1222 - * performance. 1223 - * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP. 1224 - * @u1_allowed: allow device transition to u1 state 1225 - * @u2_allowed: allow device transition to u2 state 1226 - * @is_selfpowered: device is self powered 1227 - * @setup_pending: setup packet is processing by gadget driver 1228 - * @hw_configured_flag: hardware endpoint configuration was set. 1229 - * @wake_up_flag: allow device to remote up the host 1230 - * @status_completion_no_call: indicate that driver is waiting for status s 1231 - * stage completion. It's used in deferred SET_CONFIGURATION request. 1232 - * @onchip_buffers: number of available on-chip buffers. 1233 - * @onchip_used_size: actual size of on-chip memory assigned to endpoints. 1234 - * @pending_status_wq: workqueue handling status stage for deferred requests. 1235 - * @shadow_ep_en: hold information about endpoints that will be enabled 1236 - * in soft irq. 1237 - * @pending_status_request: request for which status stage was deferred 1238 - */ 1239 - struct cdns3_device { 1240 - struct device *dev; 1241 - struct device *sysdev; 1242 - 1243 - struct usb_gadget gadget; 1244 - struct usb_gadget_driver *gadget_driver; 1245 - 1246 - #define CDNS_REVISION_V0 0x00024501 1247 - #define CDNS_REVISION_V1 0x00024509 1248 - u32 dev_ver; 1249 - 1250 - /* generic spin-lock for drivers */ 1251 - spinlock_t lock; 1252 - 1253 - struct cdns3_usb_regs __iomem *regs; 1254 - 1255 - struct usb_ctrlrequest *setup_buf; 1256 - dma_addr_t setup_dma; 1257 - void *zlp_buf; 1258 - 1259 - u8 ep0_stage; 1260 - int ep0_data_dir; 1261 - 1262 - struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT]; 1263 - 1264 - struct list_head aligned_buf_list; 1265 - unsigned run_garbage_colector:1; 1266 - 1267 - u32 selected_ep; 1268 - u16 isoch_delay; 1269 - 1270 - unsigned wait_for_setup:1; 1271 - unsigned u1_allowed:1; 1272 - unsigned u2_allowed:1; 1273 - unsigned is_selfpowered:1; 1274 - unsigned setup_pending:1; 1275 - int hw_configured_flag:1; 1276 - int wake_up_flag:1; 1277 - unsigned status_completion_no_call:1; 1278 - int out_mem_is_allocated; 1279 - 1280 - struct work_struct pending_status_wq; 1281 - struct usb_request *pending_status_request; 1282 - u32 shadow_ep_en; 1283 - /*in KB */ 1284 - u16 onchip_buffers; 1285 - u16 onchip_used_size; 1286 - }; 1287 - 1288 - void cdns3_set_register_bit(void __iomem *ptr, u32 mask); 1289 - dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep, 1290 - struct cdns3_trb *trb); 1291 - enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev); 1292 - void cdns3_pending_setup_status_handler(struct work_struct *work); 1293 - void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev); 1294 - void cdns3_set_hw_configuration(struct cdns3_device *priv_dev); 1295 - void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep); 1296 - void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable); 1297 - struct usb_request *cdns3_next_request(struct list_head *list); 1298 - int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep, 1299 - struct usb_request *request); 1300 - void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm); 1301 - int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep); 1302 - u8 cdns3_ep_addr_to_index(u8 ep_addr); 1303 - int cdns3_gadget_ep_set_wedge(struct usb_ep *ep); 1304 - int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value); 1305 - struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep, 1306 - gfp_t gfp_flags); 1307 - void cdns3_gadget_ep_free_request(struct usb_ep *ep, 1308 - struct usb_request *request); 1309 - int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request); 1310 - void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep, 1311 - struct cdns3_request *priv_req, 1312 - int status); 1313 - 1314 - int cdns3_init_ep0(struct cdns3_device *priv_dev, 1315 - struct cdns3_endpoint *priv_ep); 1316 - void cdns3_ep0_config(struct cdns3_device *priv_dev); 1317 - void cdns3_ep_config(struct cdns3_endpoint *priv_ep); 1318 - void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir); 1319 - int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev); 1320 - 1321 - #endif /* __LINUX_CDNS3_GADGET */
-28
drivers/usb/cdns3/host-export.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * Cadence USBSS DRD Driver - Host Export APIs 4 - * 5 - * Copyright (C) 2017-2018 NXP 6 - * 7 - * Authors: Peter Chen <peter.chen@nxp.com> 8 - */ 9 - #ifndef __LINUX_CDNS3_HOST_EXPORT 10 - #define __LINUX_CDNS3_HOST_EXPORT 11 - 12 - #ifdef CONFIG_USB_CDNS3_HOST 13 - 14 - int cdns3_host_init(struct cdns3 *cdns); 15 - void cdns3_host_exit(struct cdns3 *cdns); 16 - 17 - #else 18 - 19 - static inline int cdns3_host_init(struct cdns3 *cdns) 20 - { 21 - return -ENXIO; 22 - } 23 - 24 - static inline void cdns3_host_exit(struct cdns3 *cdns) { } 25 - 26 - #endif /* CONFIG_USB_CDNS3_HOST */ 27 - 28 - #endif /* __LINUX_CDNS3_HOST_EXPORT */
-76
drivers/usb/cdns3/host.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Cadence USBSS DRD Driver - host side 4 - * 5 - * Copyright (C) 2018 Cadence Design Systems. 6 - * Copyright (C) 2017-2018 NXP 7 - * 8 - * Authors: Peter Chen <peter.chen@nxp.com> 9 - * Pawel Laszczak <pawell@cadence.com> 10 - */ 11 - 12 - #include <linux/platform_device.h> 13 - #include "core.h" 14 - #include "drd.h" 15 - 16 - static int __cdns3_host_init(struct cdns3 *cdns) 17 - { 18 - struct platform_device *xhci; 19 - int ret; 20 - 21 - cdns3_drd_switch_host(cdns, 1); 22 - 23 - xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO); 24 - if (!xhci) { 25 - dev_err(cdns->dev, "couldn't allocate xHCI device\n"); 26 - return -ENOMEM; 27 - } 28 - 29 - xhci->dev.parent = cdns->dev; 30 - cdns->host_dev = xhci; 31 - 32 - ret = platform_device_add_resources(xhci, cdns->xhci_res, 33 - CDNS3_XHCI_RESOURCES_NUM); 34 - if (ret) { 35 - dev_err(cdns->dev, "couldn't add resources to xHCI device\n"); 36 - goto err1; 37 - } 38 - 39 - ret = platform_device_add(xhci); 40 - if (ret) { 41 - dev_err(cdns->dev, "failed to register xHCI device\n"); 42 - goto err1; 43 - } 44 - 45 - return 0; 46 - err1: 47 - platform_device_put(xhci); 48 - return ret; 49 - } 50 - 51 - static void cdns3_host_exit(struct cdns3 *cdns) 52 - { 53 - platform_device_unregister(cdns->host_dev); 54 - cdns->host_dev = NULL; 55 - cdns3_drd_switch_host(cdns, 0); 56 - } 57 - 58 - int cdns3_host_init(struct cdns3 *cdns) 59 - { 60 - struct cdns3_role_driver *rdrv; 61 - 62 - rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL); 63 - if (!rdrv) 64 - return -ENOMEM; 65 - 66 - rdrv->start = __cdns3_host_init; 67 - rdrv->stop = cdns3_host_exit; 68 - rdrv->state = CDNS3_ROLE_STATE_INACTIVE; 69 - rdrv->suspend = NULL; 70 - rdrv->resume = NULL; 71 - rdrv->name = "host"; 72 - 73 - cdns->roles[CDNS3_ROLE_HOST] = rdrv; 74 - 75 - return 0; 76 - }
-23
drivers/usb/cdns3/trace.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * USBSS device controller driver Trace Support 4 - * 5 - * Copyright (C) 2018 Cadence. 6 - * 7 - * Author: Pawel Laszczak <pawell@cadence.com> 8 - */ 9 - 10 - #define CREATE_TRACE_POINTS 11 - #include "trace.h" 12 - 13 - void cdns3_dbg(struct cdns3_device *priv_dev, const char *fmt, ...) 14 - { 15 - struct va_format vaf; 16 - va_list args; 17 - 18 - va_start(args, fmt); 19 - vaf.fmt = fmt; 20 - vaf.va = &args; 21 - trace_cdns3_log(priv_dev, &vaf); 22 - va_end(args); 23 - }
-447
drivers/usb/cdns3/trace.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * USBSS device controller driver. 4 - * Trace support header file. 5 - * 6 - * Copyright (C) 2018 Cadence. 7 - * 8 - * Author: Pawel Laszczak <pawell@cadence.com> 9 - */ 10 - 11 - #undef TRACE_SYSTEM 12 - #define TRACE_SYSTEM cdns3 13 - 14 - #if !defined(__LINUX_CDNS3_TRACE) || defined(TRACE_HEADER_MULTI_READ) 15 - #define __LINUX_CDNS3_TRACE 16 - 17 - #include <linux/types.h> 18 - #include <linux/tracepoint.h> 19 - #include <asm/byteorder.h> 20 - #include <linux/usb/ch9.h> 21 - #include "core.h" 22 - #include "gadget.h" 23 - #include "debug.h" 24 - 25 - #define CDNS3_MSG_MAX 500 26 - 27 - TRACE_EVENT(cdns3_log, 28 - TP_PROTO(struct cdns3_device *priv_dev, struct va_format *vaf), 29 - TP_ARGS(priv_dev, vaf), 30 - TP_STRUCT__entry( 31 - __string(name, dev_name(priv_dev->dev)) 32 - __dynamic_array(char, msg, CDNS3_MSG_MAX) 33 - ), 34 - TP_fast_assign( 35 - __assign_str(name, dev_name(priv_dev->dev)); 36 - vsnprintf(__get_str(msg), CDNS3_MSG_MAX, vaf->fmt, *vaf->va); 37 - ), 38 - TP_printk("%s: %s", __get_str(name), __get_str(msg)) 39 - ); 40 - 41 - DECLARE_EVENT_CLASS(cdns3_log_doorbell, 42 - TP_PROTO(const char *ep_name, u32 ep_trbaddr), 43 - TP_ARGS(ep_name, ep_trbaddr), 44 - TP_STRUCT__entry( 45 - __string(name, ep_name) 46 - __field(u32, ep_trbaddr) 47 - ), 48 - TP_fast_assign( 49 - __assign_str(name, ep_name); 50 - __entry->ep_trbaddr = ep_trbaddr; 51 - ), 52 - TP_printk("//Ding Dong %s, ep_trbaddr %08x", __get_str(name), 53 - __entry->ep_trbaddr) 54 - ); 55 - 56 - DEFINE_EVENT(cdns3_log_doorbell, cdns3_doorbell_ep0, 57 - TP_PROTO(const char *ep_name, u32 ep_trbaddr), 58 - TP_ARGS(ep_name, ep_trbaddr) 59 - ); 60 - 61 - DEFINE_EVENT(cdns3_log_doorbell, cdns3_doorbell_epx, 62 - TP_PROTO(const char *ep_name, u32 ep_trbaddr), 63 - TP_ARGS(ep_name, ep_trbaddr) 64 - ); 65 - 66 - DECLARE_EVENT_CLASS(cdns3_log_usb_irq, 67 - TP_PROTO(struct cdns3_device *priv_dev, u32 usb_ists), 68 - TP_ARGS(priv_dev, usb_ists), 69 - TP_STRUCT__entry( 70 - __field(enum usb_device_speed, speed) 71 - __field(u32, usb_ists) 72 - __dynamic_array(char, str, CDNS3_MSG_MAX) 73 - ), 74 - TP_fast_assign( 75 - __entry->speed = cdns3_get_speed(priv_dev); 76 - __entry->usb_ists = usb_ists; 77 - ), 78 - TP_printk("%s", cdns3_decode_usb_irq(__get_str(str), __entry->speed, 79 - __entry->usb_ists)) 80 - ); 81 - 82 - DEFINE_EVENT(cdns3_log_usb_irq, cdns3_usb_irq, 83 - TP_PROTO(struct cdns3_device *priv_dev, u32 usb_ists), 84 - TP_ARGS(priv_dev, usb_ists) 85 - ); 86 - 87 - DECLARE_EVENT_CLASS(cdns3_log_epx_irq, 88 - TP_PROTO(struct cdns3_device *priv_dev, struct cdns3_endpoint *priv_ep), 89 - TP_ARGS(priv_dev, priv_ep), 90 - TP_STRUCT__entry( 91 - __string(ep_name, priv_ep->name) 92 - __field(u32, ep_sts) 93 - __field(u32, ep_traddr) 94 - __dynamic_array(char, str, CDNS3_MSG_MAX) 95 - ), 96 - TP_fast_assign( 97 - __assign_str(ep_name, priv_ep->name); 98 - __entry->ep_sts = readl(&priv_dev->regs->ep_sts); 99 - __entry->ep_traddr = readl(&priv_dev->regs->ep_traddr); 100 - ), 101 - TP_printk("%s, ep_traddr: %08x", 102 - cdns3_decode_epx_irq(__get_str(str), 103 - __get_str(ep_name), 104 - __entry->ep_sts), 105 - __entry->ep_traddr) 106 - ); 107 - 108 - DEFINE_EVENT(cdns3_log_epx_irq, cdns3_epx_irq, 109 - TP_PROTO(struct cdns3_device *priv_dev, struct cdns3_endpoint *priv_ep), 110 - TP_ARGS(priv_dev, priv_ep) 111 - ); 112 - 113 - DECLARE_EVENT_CLASS(cdns3_log_ep0_irq, 114 - TP_PROTO(struct cdns3_device *priv_dev, u32 ep_sts), 115 - TP_ARGS(priv_dev, ep_sts), 116 - TP_STRUCT__entry( 117 - __field(int, ep_dir) 118 - __field(u32, ep_sts) 119 - __dynamic_array(char, str, CDNS3_MSG_MAX) 120 - ), 121 - TP_fast_assign( 122 - __entry->ep_dir = priv_dev->ep0_data_dir; 123 - __entry->ep_sts = ep_sts; 124 - ), 125 - TP_printk("%s", cdns3_decode_ep0_irq(__get_str(str), 126 - __entry->ep_dir, 127 - __entry->ep_sts)) 128 - ); 129 - 130 - DEFINE_EVENT(cdns3_log_ep0_irq, cdns3_ep0_irq, 131 - TP_PROTO(struct cdns3_device *priv_dev, u32 ep_sts), 132 - TP_ARGS(priv_dev, ep_sts) 133 - ); 134 - 135 - DECLARE_EVENT_CLASS(cdns3_log_ctrl, 136 - TP_PROTO(struct usb_ctrlrequest *ctrl), 137 - TP_ARGS(ctrl), 138 - TP_STRUCT__entry( 139 - __field(u8, bRequestType) 140 - __field(u8, bRequest) 141 - __field(u16, wValue) 142 - __field(u16, wIndex) 143 - __field(u16, wLength) 144 - __dynamic_array(char, str, CDNS3_MSG_MAX) 145 - ), 146 - TP_fast_assign( 147 - __entry->bRequestType = ctrl->bRequestType; 148 - __entry->bRequest = ctrl->bRequest; 149 - __entry->wValue = le16_to_cpu(ctrl->wValue); 150 - __entry->wIndex = le16_to_cpu(ctrl->wIndex); 151 - __entry->wLength = le16_to_cpu(ctrl->wLength); 152 - ), 153 - TP_printk("%s", usb_decode_ctrl(__get_str(str), CDNS3_MSG_MAX, 154 - __entry->bRequestType, 155 - __entry->bRequest, __entry->wValue, 156 - __entry->wIndex, __entry->wLength) 157 - ) 158 - ); 159 - 160 - DEFINE_EVENT(cdns3_log_ctrl, cdns3_ctrl_req, 161 - TP_PROTO(struct usb_ctrlrequest *ctrl), 162 - TP_ARGS(ctrl) 163 - ); 164 - 165 - DECLARE_EVENT_CLASS(cdns3_log_request, 166 - TP_PROTO(struct cdns3_request *req), 167 - TP_ARGS(req), 168 - TP_STRUCT__entry( 169 - __string(name, req->priv_ep->name) 170 - __field(struct cdns3_request *, req) 171 - __field(void *, buf) 172 - __field(unsigned int, actual) 173 - __field(unsigned int, length) 174 - __field(int, status) 175 - __field(int, zero) 176 - __field(int, short_not_ok) 177 - __field(int, no_interrupt) 178 - __field(int, start_trb) 179 - __field(int, end_trb) 180 - __field(struct cdns3_trb *, start_trb_addr) 181 - __field(int, flags) 182 - ), 183 - TP_fast_assign( 184 - __assign_str(name, req->priv_ep->name); 185 - __entry->req = req; 186 - __entry->buf = req->request.buf; 187 - __entry->actual = req->request.actual; 188 - __entry->length = req->request.length; 189 - __entry->status = req->request.status; 190 - __entry->zero = req->request.zero; 191 - __entry->short_not_ok = req->request.short_not_ok; 192 - __entry->no_interrupt = req->request.no_interrupt; 193 - __entry->start_trb = req->start_trb; 194 - __entry->end_trb = req->end_trb; 195 - __entry->start_trb_addr = req->trb; 196 - __entry->flags = req->flags; 197 - ), 198 - TP_printk("%s: req: %p, req buff %p, length: %u/%u %s%s%s, status: %d," 199 - " trb: [start:%d, end:%d: virt addr %pa], flags:%x ", 200 - __get_str(name), __entry->req, __entry->buf, __entry->actual, 201 - __entry->length, 202 - __entry->zero ? "zero | " : "", 203 - __entry->short_not_ok ? "short | " : "", 204 - __entry->no_interrupt ? "no int" : "", 205 - __entry->status, 206 - __entry->start_trb, 207 - __entry->end_trb, 208 - __entry->start_trb_addr, 209 - __entry->flags 210 - ) 211 - ); 212 - 213 - DEFINE_EVENT(cdns3_log_request, cdns3_alloc_request, 214 - TP_PROTO(struct cdns3_request *req), 215 - TP_ARGS(req) 216 - ); 217 - 218 - DEFINE_EVENT(cdns3_log_request, cdns3_free_request, 219 - TP_PROTO(struct cdns3_request *req), 220 - TP_ARGS(req) 221 - ); 222 - 223 - DEFINE_EVENT(cdns3_log_request, cdns3_ep_queue, 224 - TP_PROTO(struct cdns3_request *req), 225 - TP_ARGS(req) 226 - ); 227 - 228 - DEFINE_EVENT(cdns3_log_request, cdns3_ep_dequeue, 229 - TP_PROTO(struct cdns3_request *req), 230 - TP_ARGS(req) 231 - ); 232 - 233 - DEFINE_EVENT(cdns3_log_request, cdns3_gadget_giveback, 234 - TP_PROTO(struct cdns3_request *req), 235 - TP_ARGS(req) 236 - ); 237 - 238 - DECLARE_EVENT_CLASS(cdns3_log_aligned_request, 239 - TP_PROTO(struct cdns3_request *priv_req), 240 - TP_ARGS(priv_req), 241 - TP_STRUCT__entry( 242 - __string(name, priv_req->priv_ep->name) 243 - __field(struct usb_request *, req) 244 - __field(void *, buf) 245 - __field(dma_addr_t, dma) 246 - __field(void *, aligned_buf) 247 - __field(dma_addr_t, aligned_dma) 248 - __field(u32, aligned_buf_size) 249 - ), 250 - TP_fast_assign( 251 - __assign_str(name, priv_req->priv_ep->name); 252 - __entry->req = &priv_req->request; 253 - __entry->buf = priv_req->request.buf; 254 - __entry->dma = priv_req->request.dma; 255 - __entry->aligned_buf = priv_req->aligned_buf->buf; 256 - __entry->aligned_dma = priv_req->aligned_buf->dma; 257 - __entry->aligned_buf_size = priv_req->aligned_buf->size; 258 - ), 259 - TP_printk("%s: req: %p, req buf %p, dma %pad a_buf %p a_dma %pad, size %d", 260 - __get_str(name), __entry->req, __entry->buf, &__entry->dma, 261 - __entry->aligned_buf, &__entry->aligned_dma, 262 - __entry->aligned_buf_size 263 - ) 264 - ); 265 - 266 - DEFINE_EVENT(cdns3_log_aligned_request, cdns3_free_aligned_request, 267 - TP_PROTO(struct cdns3_request *req), 268 - TP_ARGS(req) 269 - ); 270 - 271 - DEFINE_EVENT(cdns3_log_aligned_request, cdns3_prepare_aligned_request, 272 - TP_PROTO(struct cdns3_request *req), 273 - TP_ARGS(req) 274 - ); 275 - 276 - DECLARE_EVENT_CLASS(cdns3_log_trb, 277 - TP_PROTO(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb), 278 - TP_ARGS(priv_ep, trb), 279 - TP_STRUCT__entry( 280 - __string(name, priv_ep->name) 281 - __field(struct cdns3_trb *, trb) 282 - __field(u32, buffer) 283 - __field(u32, length) 284 - __field(u32, control) 285 - __field(u32, type) 286 - ), 287 - TP_fast_assign( 288 - __assign_str(name, priv_ep->name); 289 - __entry->trb = trb; 290 - __entry->buffer = trb->buffer; 291 - __entry->length = trb->length; 292 - __entry->control = trb->control; 293 - __entry->type = usb_endpoint_type(priv_ep->endpoint.desc); 294 - ), 295 - TP_printk("%s: trb %p, dma buf: 0x%08x, size: %ld, burst: %d ctrl: 0x%08x (%s%s%s%s%s%s%s)", 296 - __get_str(name), __entry->trb, __entry->buffer, 297 - TRB_LEN(__entry->length), 298 - (u8)TRB_BURST_LEN_GET(__entry->length), 299 - __entry->control, 300 - __entry->control & TRB_CYCLE ? "C=1, " : "C=0, ", 301 - __entry->control & TRB_TOGGLE ? "T=1, " : "T=0, ", 302 - __entry->control & TRB_ISP ? "ISP, " : "", 303 - __entry->control & TRB_FIFO_MODE ? "FIFO, " : "", 304 - __entry->control & TRB_CHAIN ? "CHAIN, " : "", 305 - __entry->control & TRB_IOC ? "IOC, " : "", 306 - TRB_FIELD_TO_TYPE(__entry->control) == TRB_NORMAL ? "Normal" : "LINK" 307 - ) 308 - ); 309 - 310 - DEFINE_EVENT(cdns3_log_trb, cdns3_prepare_trb, 311 - TP_PROTO(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb), 312 - TP_ARGS(priv_ep, trb) 313 - ); 314 - 315 - DEFINE_EVENT(cdns3_log_trb, cdns3_complete_trb, 316 - TP_PROTO(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb), 317 - TP_ARGS(priv_ep, trb) 318 - ); 319 - 320 - DECLARE_EVENT_CLASS(cdns3_log_ring, 321 - TP_PROTO(struct cdns3_endpoint *priv_ep), 322 - TP_ARGS(priv_ep), 323 - TP_STRUCT__entry( 324 - __dynamic_array(u8, ring, TRB_RING_SIZE) 325 - __dynamic_array(u8, priv_ep, sizeof(struct cdns3_endpoint)) 326 - __dynamic_array(char, buffer, 327 - (TRBS_PER_SEGMENT * 65) + CDNS3_MSG_MAX) 328 - ), 329 - TP_fast_assign( 330 - memcpy(__get_dynamic_array(priv_ep), priv_ep, 331 - sizeof(struct cdns3_endpoint)); 332 - memcpy(__get_dynamic_array(ring), priv_ep->trb_pool, 333 - TRB_RING_SIZE); 334 - ), 335 - 336 - TP_printk("%s", 337 - cdns3_dbg_ring((struct cdns3_endpoint *)__get_str(priv_ep), 338 - (struct cdns3_trb *)__get_str(ring), 339 - __get_str(buffer))) 340 - ); 341 - 342 - DEFINE_EVENT(cdns3_log_ring, cdns3_ring, 343 - TP_PROTO(struct cdns3_endpoint *priv_ep), 344 - TP_ARGS(priv_ep) 345 - ); 346 - 347 - DECLARE_EVENT_CLASS(cdns3_log_ep, 348 - TP_PROTO(struct cdns3_endpoint *priv_ep), 349 - TP_ARGS(priv_ep), 350 - TP_STRUCT__entry( 351 - __string(name, priv_ep->name) 352 - __field(unsigned int, maxpacket) 353 - __field(unsigned int, maxpacket_limit) 354 - __field(unsigned int, max_streams) 355 - __field(unsigned int, maxburst) 356 - __field(unsigned int, flags) 357 - __field(unsigned int, dir) 358 - __field(u8, enqueue) 359 - __field(u8, dequeue) 360 - ), 361 - TP_fast_assign( 362 - __assign_str(name, priv_ep->name); 363 - __entry->maxpacket = priv_ep->endpoint.maxpacket; 364 - __entry->maxpacket_limit = priv_ep->endpoint.maxpacket_limit; 365 - __entry->max_streams = priv_ep->endpoint.max_streams; 366 - __entry->maxburst = priv_ep->endpoint.maxburst; 367 - __entry->flags = priv_ep->flags; 368 - __entry->dir = priv_ep->dir; 369 - __entry->enqueue = priv_ep->enqueue; 370 - __entry->dequeue = priv_ep->dequeue; 371 - ), 372 - TP_printk("%s: mps: %d/%d. streams: %d, burst: %d, enq idx: %d, " 373 - "deq idx: %d, flags %s%s%s%s%s%s%s%s, dir: %s", 374 - __get_str(name), __entry->maxpacket, 375 - __entry->maxpacket_limit, __entry->max_streams, 376 - __entry->maxburst, __entry->enqueue, 377 - __entry->dequeue, 378 - __entry->flags & EP_ENABLED ? "EN | " : "", 379 - __entry->flags & EP_STALL ? "STALL | " : "", 380 - __entry->flags & EP_WEDGE ? "WEDGE | " : "", 381 - __entry->flags & EP_TRANSFER_STARTED ? "STARTED | " : "", 382 - __entry->flags & EP_UPDATE_EP_TRBADDR ? "UPD TRB | " : "", 383 - __entry->flags & EP_PENDING_REQUEST ? "REQ PEN | " : "", 384 - __entry->flags & EP_RING_FULL ? "RING FULL |" : "", 385 - __entry->flags & EP_CLAIMED ? "CLAIMED " : "", 386 - __entry->dir ? "IN" : "OUT" 387 - ) 388 - ); 389 - 390 - DEFINE_EVENT(cdns3_log_ep, cdns3_gadget_ep_enable, 391 - TP_PROTO(struct cdns3_endpoint *priv_ep), 392 - TP_ARGS(priv_ep) 393 - ); 394 - 395 - DEFINE_EVENT(cdns3_log_ep, cdns3_gadget_ep_disable, 396 - TP_PROTO(struct cdns3_endpoint *priv_ep), 397 - TP_ARGS(priv_ep) 398 - ); 399 - 400 - DECLARE_EVENT_CLASS(cdns3_log_request_handled, 401 - TP_PROTO(struct cdns3_request *priv_req, int current_index, 402 - int handled), 403 - TP_ARGS(priv_req, current_index, handled), 404 - TP_STRUCT__entry( 405 - __field(struct cdns3_request *, priv_req) 406 - __field(unsigned int, dma_position) 407 - __field(unsigned int, handled) 408 - __field(unsigned int, dequeue_idx) 409 - __field(unsigned int, enqueue_idx) 410 - __field(unsigned int, start_trb) 411 - __field(unsigned int, end_trb) 412 - ), 413 - TP_fast_assign( 414 - __entry->priv_req = priv_req; 415 - __entry->dma_position = current_index; 416 - __entry->handled = handled; 417 - __entry->dequeue_idx = priv_req->priv_ep->dequeue; 418 - __entry->enqueue_idx = priv_req->priv_ep->enqueue; 419 - __entry->start_trb = priv_req->start_trb; 420 - __entry->end_trb = priv_req->end_trb; 421 - ), 422 - TP_printk("Req: %p %s, DMA pos: %d, ep deq: %d, ep enq: %d," 423 - " start trb: %d, end trb: %d", 424 - __entry->priv_req, 425 - __entry->handled ? "handled" : "not handled", 426 - __entry->dma_position, __entry->dequeue_idx, 427 - __entry->enqueue_idx, __entry->start_trb, 428 - __entry->end_trb 429 - ) 430 - ); 431 - 432 - DEFINE_EVENT(cdns3_log_request_handled, cdns3_request_handled, 433 - TP_PROTO(struct cdns3_request *priv_req, int current_index, 434 - int handled), 435 - TP_ARGS(priv_req, current_index, handled) 436 - ); 437 - #endif /* __LINUX_CDNS3_TRACE */ 438 - 439 - /* this part must be outside header guard */ 440 - 441 - #undef TRACE_INCLUDE_PATH 442 - #define TRACE_INCLUDE_PATH . 443 - 444 - #undef TRACE_INCLUDE_FILE 445 - #define TRACE_INCLUDE_FILE trace 446 - 447 - #include <trace/define_trace.h>