···146 __clr_IFR(0x0000);147148 for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)149- set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);150151- set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);152153 /* the FPGA drives the first four external IRQ inputs on the CPU PIC */154 setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
···146 __clr_IFR(0x0000);147148 for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)149+ irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);150151+ irq_set_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);152153 /* the FPGA drives the first four external IRQ inputs on the CPU PIC */154 setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
+1-1
arch/frv/kernel/irq-mb93093.c
···124 __clr_IFR(0x0000);125126 for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)127- set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);128129 /* the FPGA drives external IRQ input #2 on the CPU PIC */130 setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
···124 __clr_IFR(0x0000);125126 for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)127+ irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);128129 /* the FPGA drives external IRQ input #2 on the CPU PIC */130 setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
+2-1
arch/frv/kernel/irq-mb93493.c
···139 int irq;140141 for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)142- set_irq_chip_and_handler(irq, &frv_mb93493_pic, handle_edge_irq);0143144 /* the MB93493 drives external IRQ inputs on the CPU PIC */145 setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
···139 int irq;140141 for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)142+ irq_set_chip_and_handler(irq, &frv_mb93493_pic,143+ handle_edge_irq);144145 /* the MB93493 drives external IRQ inputs on the CPU PIC */146 setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
+2-2
arch/frv/kernel/irq.c
···155 int level;156157 for (level = 1; level <= 14; level++)158- set_irq_chip_and_handler(level, &frv_cpu_pic,159 handle_level_irq);160161- set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq);162163 /* set the trigger levels for internal interrupt sources164 * - timers all falling-edge
···155 int level;156157 for (level = 1; level <= 14; level++)158+ irq_set_chip_and_handler(level, &frv_cpu_pic,159 handle_level_irq);160161+ irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq);162163 /* set the trigger levels for internal interrupt sources164 * - timers all falling-edge