tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'icc-mtk' into icc-next
MediaTek DVFSRC Bus Bandwidth and Regulator knobs
This series adds support for the MediaTek Dynamic Voltage and Frequency
Scaling Resource Controller (DVFSRC), found on many MediaTek SoCs.
This hardware collects requests from both software and the various remote
processors embededd into the SoC, and decides about a minimum operating
voltage and a minimum DRAM frequency to fulfill those requests, in an
effort to provide the best achievable performance per watt.
Such hardware IP is capable of transparently performing direct register
R/W on all of the DVFSRC-controlled regulators and SoC bandwidth knobs.
Summarizing how the DVFSRC works for Interconnect:
ICC provider ICC Nodes
---- ----
_________ |CPU | |--- |VPU |
_____ | |----- ---- | ----
| |->| DRAM | ---- | ----
|DRAM |->|scheduler|----- |GPU | |--- |DISP|
| |->| (EMI) | ---- | ----
|_____|->|_________|---. ----- | ----
/|\ `-|MMSYS|--|--- |VDEC|
| ----- | ----
| | ----
| change DRAM freq |--- |VENC|
-------- | ----
SMC --> | DVFSRC | | ----
-------- |--- |IMG |
| ----
| ----
|--- |CAM |
----
* icc-mtk
dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings
interconnect: mediatek: Add MediaTek MT8183/8195 EMI Interconnect driver
interconnect: mediatek: remove unneeded semicolon
Link: https://lore.kernel.org/r/20240610085735.147134-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
+829
+51
Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
+51
Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/mediatek,mt8183-emi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek External Memory Interface (EMI) Interconnect
8
+
9
+
maintainers:
10
+
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11
+
12
+
description: |
13
+
EMI interconnect providers support system bandwidth requirements through
14
+
Dynamic Voltage Frequency Scaling Resource Collector (DVFSRC) hardware.
15
+
The provider is able to communicate with the DVFSRC through Secure Monitor
16
+
Call (SMC).
17
+
18
+
ICC provider ICC Nodes
19
+
---- ----
20
+
_________ |CPU | |--- |VPU |
21
+
_____ | |----- ---- | ----
22
+
| |->| DRAM | ---- | ----
23
+
|DRAM |->|scheduler|----- |GPU | |--- |DISP|
24
+
| |->| (EMI) | ---- | ----
25
+
|_____|->|_________|---. ----- | ----
26
+
/|\ `-|MMSYS|--|--- |VDEC|
27
+
| ----- | ----
28
+
| | ----
29
+
| change DRAM freq |--- |VENC|
30
+
-------- | ----
31
+
SMC --> | DVFSRC | | ----
32
+
-------- |--- |IMG |
33
+
| ----
34
+
| ----
35
+
|--- |CAM |
36
+
----
37
+
38
+
properties:
39
+
compatible:
40
+
enum:
41
+
- mediatek,mt8183-emi
42
+
- mediatek,mt8195-emi
43
+
44
+
'#interconnect-cells':
45
+
const: 1
46
+
47
+
required:
48
+
- compatible
49
+
- '#interconnect-cells'
50
+
51
+
unevaluatedProperties: false
+1
drivers/interconnect/Kconfig
+1
drivers/interconnect/Kconfig
+1
drivers/interconnect/Makefile
+1
drivers/interconnect/Makefile
+29
drivers/interconnect/mediatek/Kconfig
+29
drivers/interconnect/mediatek/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
config INTERCONNECT_MTK
4
+
bool "MediaTek interconnect drivers"
5
+
depends on ARCH_MEDIATEK || COMPILE_TEST
6
+
help
7
+
Support for MediaTek's bus interconnect hardware.
8
+
9
+
config INTERCONNECT_MTK_DVFSRC_EMI
10
+
tristate "MediaTek DVFSRC EMI interconnect driver"
11
+
depends on INTERCONNECT_MTK && MTK_DVFSRC
12
+
help
13
+
This is a driver for the MediaTek External Memory Interface
14
+
interconnect on SoCs equipped with the integrated Dynamic
15
+
Voltage Frequency Scaling Resource Collector (DVFSRC) MCU
16
+
17
+
config INTERCONNECT_MTK_MT8183
18
+
tristate "MediaTek MT8183 interconnect driver"
19
+
depends on INTERCONNECT_MTK_DVFSRC_EMI
20
+
help
21
+
This is a driver for the MediaTek bus interconnect on MT8183-based
22
+
platforms.
23
+
24
+
config INTERCONNECT_MTK_MT8195
25
+
tristate "MediaTek MT8195 interconnect driver"
26
+
depends on INTERCONNECT_MTK_DVFSRC_EMI
27
+
help
28
+
This is a driver for the MediaTek bus interconnect on MT8195-based
29
+
platforms.
+5
drivers/interconnect/mediatek/Makefile
+5
drivers/interconnect/mediatek/Makefile
+153
drivers/interconnect/mediatek/icc-emi.c
+153
drivers/interconnect/mediatek/icc-emi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek External Memory Interface (EMI) Interconnect driver
4
+
*
5
+
* Copyright (c) 2021 MediaTek Inc.
6
+
* Copyright (c) 2024 Collabora Ltd.
7
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
8
+
*/
9
+
10
+
#include <linux/interconnect.h>
11
+
#include <linux/interconnect-provider.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of.h>
14
+
#include <linux/of_platform.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/soc/mediatek/dvfsrc.h>
17
+
18
+
#include "icc-emi.h"
19
+
20
+
static int mtk_emi_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
21
+
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
22
+
{
23
+
struct mtk_icc_node *in = node->data;
24
+
25
+
*agg_avg += avg_bw;
26
+
*agg_peak = max_t(u32, *agg_peak, peak_bw);
27
+
28
+
in->sum_avg = *agg_avg;
29
+
in->max_peak = *agg_peak;
30
+
31
+
return 0;
32
+
}
33
+
34
+
static int mtk_emi_icc_set(struct icc_node *src, struct icc_node *dst)
35
+
{
36
+
struct mtk_icc_node *node = dst->data;
37
+
struct device *dev;
38
+
int ret;
39
+
40
+
if (unlikely(!src->provider))
41
+
return -EINVAL;
42
+
43
+
dev = src->provider->dev;
44
+
45
+
switch (node->ep) {
46
+
case 0:
47
+
break;
48
+
case 1:
49
+
ret = mtk_dvfsrc_send_request(dev, MTK_DVFSRC_CMD_PEAK_BW, node->max_peak);
50
+
if (ret) {
51
+
dev_err(dev, "Cannot send peak bw request: %d\n", ret);
52
+
return ret;
53
+
}
54
+
55
+
ret = mtk_dvfsrc_send_request(dev, MTK_DVFSRC_CMD_BW, node->sum_avg);
56
+
if (ret) {
57
+
dev_err(dev, "Cannot send bw request: %d\n", ret);
58
+
return ret;
59
+
}
60
+
break;
61
+
case 2:
62
+
ret = mtk_dvfsrc_send_request(dev, MTK_DVFSRC_CMD_HRT_BW, node->sum_avg);
63
+
if (ret) {
64
+
dev_err(dev, "Cannot send HRT bw request: %d\n", ret);
65
+
return ret;
66
+
}
67
+
break;
68
+
default:
69
+
dev_err(src->provider->dev, "Unknown endpoint %u\n", node->ep);
70
+
return -EINVAL;
71
+
}
72
+
73
+
return 0;
74
+
}
75
+
76
+
int mtk_emi_icc_probe(struct platform_device *pdev)
77
+
{
78
+
const struct mtk_icc_desc *desc;
79
+
struct device *dev = &pdev->dev;
80
+
struct icc_node *node;
81
+
struct icc_onecell_data *data;
82
+
struct icc_provider *provider;
83
+
struct mtk_icc_node **mnodes;
84
+
int i, j, ret;
85
+
86
+
desc = of_device_get_match_data(dev);
87
+
if (!desc)
88
+
return -EINVAL;
89
+
90
+
mnodes = desc->nodes;
91
+
92
+
provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
93
+
if (!provider)
94
+
return -ENOMEM;
95
+
96
+
data = devm_kzalloc(dev, struct_size(data, nodes, desc->num_nodes), GFP_KERNEL);
97
+
if (!data)
98
+
return -ENOMEM;
99
+
100
+
provider->dev = pdev->dev.parent;
101
+
provider->set = mtk_emi_icc_set;
102
+
provider->aggregate = mtk_emi_icc_aggregate;
103
+
provider->xlate = of_icc_xlate_onecell;
104
+
INIT_LIST_HEAD(&provider->nodes);
105
+
provider->data = data;
106
+
107
+
for (i = 0; i < desc->num_nodes; i++) {
108
+
if (!mnodes[i])
109
+
continue;
110
+
111
+
node = icc_node_create(mnodes[i]->id);
112
+
if (IS_ERR(node)) {
113
+
ret = PTR_ERR(node);
114
+
goto err;
115
+
}
116
+
117
+
node->name = mnodes[i]->name;
118
+
node->data = mnodes[i];
119
+
icc_node_add(node, provider);
120
+
121
+
for (j = 0; j < mnodes[i]->num_links; j++)
122
+
icc_link_create(node, mnodes[i]->links[j]);
123
+
124
+
data->nodes[i] = node;
125
+
}
126
+
data->num_nodes = desc->num_nodes;
127
+
128
+
ret = icc_provider_register(provider);
129
+
if (ret)
130
+
goto err;
131
+
132
+
platform_set_drvdata(pdev, provider);
133
+
134
+
return 0;
135
+
err:
136
+
icc_nodes_remove(provider);
137
+
return ret;
138
+
}
139
+
EXPORT_SYMBOL_GPL(mtk_emi_icc_probe);
140
+
141
+
void mtk_emi_icc_remove(struct platform_device *pdev)
142
+
{
143
+
struct icc_provider *provider = platform_get_drvdata(pdev);
144
+
145
+
icc_provider_deregister(provider);
146
+
icc_nodes_remove(provider);
147
+
}
148
+
EXPORT_SYMBOL_GPL(mtk_emi_icc_remove);
149
+
150
+
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
151
+
MODULE_AUTHOR("Henry Chen <henryc.chen@mediatek.com>");
152
+
MODULE_DESCRIPTION("MediaTek External Memory Interface interconnect driver");
153
+
MODULE_LICENSE("GPL");
+40
drivers/interconnect/mediatek/icc-emi.h
+40
drivers/interconnect/mediatek/icc-emi.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#ifndef __DRIVERS_INTERCONNECT_MEDIATEK_ICC_EMI_H
9
+
#define __DRIVERS_INTERCONNECT_MEDIATEK_ICC_EMI_H
10
+
11
+
/**
12
+
* struct mtk_icc_node - Mediatek EMI Interconnect Node
13
+
* @name: The interconnect node name which is shown in debugfs
14
+
* @ep: Type of this endpoint
15
+
* @id: Unique node identifier
16
+
* @sum_avg: Current sum aggregate value of all average bw requests in kBps
17
+
* @max_peak: Current max aggregate value of all peak bw requests in kBps
18
+
* @num_links: The total number of @links
19
+
* @links: Array of @id linked to this node
20
+
*/
21
+
struct mtk_icc_node {
22
+
unsigned char *name;
23
+
int ep;
24
+
u16 id;
25
+
u64 sum_avg;
26
+
u64 max_peak;
27
+
28
+
u16 num_links;
29
+
u16 links[] __counted_by(num_links);
30
+
};
31
+
32
+
struct mtk_icc_desc {
33
+
struct mtk_icc_node **nodes;
34
+
size_t num_nodes;
35
+
};
36
+
37
+
int mtk_emi_icc_probe(struct platform_device *pdev);
38
+
void mtk_emi_icc_remove(struct platform_device *pdev);
39
+
40
+
#endif /* __DRIVERS_INTERCONNECT_MEDIATEK_ICC_EMI_H */
+143
drivers/interconnect/mediatek/mt8183.c
+143
drivers/interconnect/mediatek/mt8183.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#include <linux/device.h>
9
+
#include <linux/interconnect.h>
10
+
#include <linux/interconnect-provider.h>
11
+
#include <linux/mod_devicetable.h>
12
+
#include <linux/module.h>
13
+
#include <linux/platform_device.h>
14
+
#include <dt-bindings/interconnect/mediatek,mt8183.h>
15
+
16
+
#include "icc-emi.h"
17
+
18
+
static struct mtk_icc_node ddr_emi = {
19
+
.name = "ddr-emi",
20
+
.id = SLAVE_DDR_EMI,
21
+
.ep = 1,
22
+
};
23
+
24
+
static struct mtk_icc_node mcusys = {
25
+
.name = "mcusys",
26
+
.id = MASTER_MCUSYS,
27
+
.ep = 0,
28
+
.num_links = 1,
29
+
.links = { SLAVE_DDR_EMI }
30
+
};
31
+
32
+
static struct mtk_icc_node gpu = {
33
+
.name = "gpu",
34
+
.id = MASTER_MFG,
35
+
.ep = 0,
36
+
.num_links = 1,
37
+
.links = { SLAVE_DDR_EMI }
38
+
};
39
+
40
+
static struct mtk_icc_node mmsys = {
41
+
.name = "mmsys",
42
+
.id = MASTER_MMSYS,
43
+
.ep = 0,
44
+
.num_links = 1,
45
+
.links = { SLAVE_DDR_EMI }
46
+
};
47
+
48
+
static struct mtk_icc_node mm_vpu = {
49
+
.name = "mm-vpu",
50
+
.id = MASTER_MM_VPU,
51
+
.ep = 0,
52
+
.num_links = 1,
53
+
.links = { MASTER_MMSYS }
54
+
};
55
+
56
+
static struct mtk_icc_node mm_disp = {
57
+
.name = "mm-disp",
58
+
.id = MASTER_MM_DISP,
59
+
.ep = 0,
60
+
.num_links = 1,
61
+
.links = { MASTER_MMSYS }
62
+
};
63
+
64
+
static struct mtk_icc_node mm_vdec = {
65
+
.name = "mm-vdec",
66
+
.id = MASTER_MM_VDEC,
67
+
.ep = 0,
68
+
.num_links = 1,
69
+
.links = { MASTER_MMSYS }
70
+
};
71
+
72
+
static struct mtk_icc_node mm_venc = {
73
+
.name = "mm-venc",
74
+
.id = MASTER_MM_VENC,
75
+
.ep = 0,
76
+
.num_links = 1,
77
+
.links = { MASTER_MMSYS }
78
+
};
79
+
80
+
static struct mtk_icc_node mm_cam = {
81
+
.name = "mm-cam",
82
+
.id = MASTER_MM_CAM,
83
+
.ep = 0,
84
+
.num_links = 1,
85
+
.links = { MASTER_MMSYS }
86
+
};
87
+
88
+
static struct mtk_icc_node mm_img = {
89
+
.name = "mm-img",
90
+
.id = MASTER_MM_IMG,
91
+
.ep = 0,
92
+
.num_links = 1,
93
+
.links = { MASTER_MMSYS }
94
+
};
95
+
96
+
static struct mtk_icc_node mm_mdp = {
97
+
.name = "mm-mdp",
98
+
.id = MASTER_MM_MDP,
99
+
.ep = 0,
100
+
.num_links = 1,
101
+
.links = { MASTER_MMSYS }
102
+
};
103
+
104
+
static struct mtk_icc_node *mt8183_emi_icc_nodes[] = {
105
+
[SLAVE_DDR_EMI] = &ddr_emi,
106
+
[MASTER_MCUSYS] = &mcusys,
107
+
[MASTER_MFG] = &gpu,
108
+
[MASTER_MMSYS] = &mmsys,
109
+
[MASTER_MM_VPU] = &mm_vpu,
110
+
[MASTER_MM_DISP] = &mm_disp,
111
+
[MASTER_MM_VDEC] = &mm_vdec,
112
+
[MASTER_MM_VENC] = &mm_venc,
113
+
[MASTER_MM_CAM] = &mm_cam,
114
+
[MASTER_MM_IMG] = &mm_img,
115
+
[MASTER_MM_MDP] = &mm_mdp
116
+
};
117
+
118
+
static const struct mtk_icc_desc mt8183_emi_icc = {
119
+
.nodes = mt8183_emi_icc_nodes,
120
+
.num_nodes = ARRAY_SIZE(mt8183_emi_icc_nodes),
121
+
};
122
+
123
+
static const struct of_device_id mtk_mt8183_emi_icc_of_match[] = {
124
+
{ .compatible = "mediatek,mt8183-emi", .data = &mt8183_emi_icc },
125
+
{ /* sentinel */ },
126
+
};
127
+
MODULE_DEVICE_TABLE(of, mtk_mt8183_emi_icc_of_match);
128
+
129
+
static struct platform_driver mtk_emi_icc_mt8183_driver = {
130
+
.driver = {
131
+
.name = "emi-icc-mt8183",
132
+
.of_match_table = mtk_mt8183_emi_icc_of_match,
133
+
.sync_state = icc_sync_state,
134
+
},
135
+
.probe = mtk_emi_icc_probe,
136
+
.remove_new = mtk_emi_icc_remove,
137
+
138
+
};
139
+
module_platform_driver(mtk_emi_icc_mt8183_driver);
140
+
141
+
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
142
+
MODULE_DESCRIPTION("MediaTek MT8183 EMI ICC driver");
143
+
MODULE_LICENSE("GPL");
+339
drivers/interconnect/mediatek/mt8195.c
+339
drivers/interconnect/mediatek/mt8195.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#include <linux/device.h>
9
+
#include <linux/interconnect.h>
10
+
#include <linux/interconnect-provider.h>
11
+
#include <linux/mod_devicetable.h>
12
+
#include <linux/module.h>
13
+
#include <linux/platform_device.h>
14
+
#include <dt-bindings/interconnect/mediatek,mt8195.h>
15
+
16
+
#include "icc-emi.h"
17
+
18
+
static struct mtk_icc_node ddr_emi = {
19
+
.name = "ddr-emi",
20
+
.id = SLAVE_DDR_EMI,
21
+
.ep = 1,
22
+
};
23
+
24
+
static struct mtk_icc_node mcusys = {
25
+
.name = "mcusys",
26
+
.id = MASTER_MCUSYS,
27
+
.ep = 0,
28
+
.num_links = 1,
29
+
.links = { SLAVE_DDR_EMI }
30
+
};
31
+
32
+
static struct mtk_icc_node gpu = {
33
+
.name = "gpu",
34
+
.id = MASTER_GPUSYS,
35
+
.ep = 0,
36
+
.num_links = 1,
37
+
.links = { SLAVE_DDR_EMI }
38
+
};
39
+
40
+
static struct mtk_icc_node mmsys = {
41
+
.name = "mmsys",
42
+
.id = MASTER_MMSYS,
43
+
.ep = 0,
44
+
.num_links = 1,
45
+
.links = { SLAVE_DDR_EMI }
46
+
};
47
+
48
+
static struct mtk_icc_node mm_vpu = {
49
+
.name = "mm-vpu",
50
+
.id = MASTER_MM_VPU,
51
+
.ep = 0,
52
+
.num_links = 1,
53
+
.links = { MASTER_MMSYS }
54
+
};
55
+
56
+
static struct mtk_icc_node mm_disp = {
57
+
.name = "mm-disp",
58
+
.id = MASTER_MM_DISP,
59
+
.ep = 0,
60
+
.num_links = 1,
61
+
.links = { MASTER_MMSYS }
62
+
};
63
+
64
+
static struct mtk_icc_node mm_vdec = {
65
+
.name = "mm-vdec",
66
+
.id = MASTER_MM_VDEC,
67
+
.ep = 0,
68
+
.num_links = 1,
69
+
.links = { MASTER_MMSYS }
70
+
};
71
+
72
+
static struct mtk_icc_node mm_venc = {
73
+
.name = "mm-venc",
74
+
.id = MASTER_MM_VENC,
75
+
.ep = 0,
76
+
.num_links = 1,
77
+
.links = { MASTER_MMSYS }
78
+
};
79
+
80
+
static struct mtk_icc_node mm_cam = {
81
+
.name = "mm-cam",
82
+
.id = MASTER_MM_CAM,
83
+
.ep = 0,
84
+
.num_links = 1,
85
+
.links = { MASTER_MMSYS }
86
+
};
87
+
88
+
static struct mtk_icc_node mm_img = {
89
+
.name = "mm-img",
90
+
.id = MASTER_MM_IMG,
91
+
.ep = 0,
92
+
.num_links = 1,
93
+
.links = { MASTER_MMSYS }
94
+
};
95
+
96
+
static struct mtk_icc_node mm_mdp = {
97
+
.name = "mm-mdp",
98
+
.id = MASTER_MM_MDP,
99
+
.ep = 0,
100
+
.num_links = 1,
101
+
.links = { MASTER_MMSYS }
102
+
};
103
+
104
+
static struct mtk_icc_node vpusys = {
105
+
.name = "vpusys",
106
+
.id = MASTER_VPUSYS,
107
+
.ep = 0,
108
+
.num_links = 1,
109
+
.links = { SLAVE_DDR_EMI }
110
+
};
111
+
112
+
static struct mtk_icc_node vpu_port0 = {
113
+
.name = "vpu-port0",
114
+
.id = MASTER_VPU_0,
115
+
.ep = 0,
116
+
.num_links = 1,
117
+
.links = { MASTER_VPUSYS }
118
+
};
119
+
120
+
static struct mtk_icc_node vpu_port1 = {
121
+
.name = "vpu-port1",
122
+
.id = MASTER_VPU_1,
123
+
.ep = 0,
124
+
.num_links = 1,
125
+
.links = { MASTER_VPUSYS }
126
+
};
127
+
128
+
static struct mtk_icc_node mdlasys = {
129
+
.name = "mdlasys",
130
+
.id = MASTER_MDLASYS,
131
+
.ep = 0,
132
+
.num_links = 1,
133
+
.links = { SLAVE_DDR_EMI }
134
+
};
135
+
136
+
static struct mtk_icc_node mdla_port0 = {
137
+
.name = "mdla-port0",
138
+
.id = MASTER_MDLA_0,
139
+
.ep = 0,
140
+
.num_links = 1,
141
+
.links = { MASTER_MDLASYS }
142
+
};
143
+
144
+
static struct mtk_icc_node ufs = {
145
+
.name = "ufs",
146
+
.id = MASTER_UFS,
147
+
.ep = 0,
148
+
.num_links = 1,
149
+
.links = { SLAVE_DDR_EMI }
150
+
};
151
+
152
+
static struct mtk_icc_node pcie0 = {
153
+
.name = "pcie0",
154
+
.id = MASTER_PCIE_0,
155
+
.ep = 0,
156
+
.num_links = 1,
157
+
.links = { SLAVE_DDR_EMI }
158
+
};
159
+
160
+
static struct mtk_icc_node pcie1 = {
161
+
.name = "pcie1",
162
+
.id = MASTER_PCIE_1,
163
+
.ep = 0,
164
+
.num_links = 1,
165
+
.links = { SLAVE_DDR_EMI }
166
+
};
167
+
168
+
static struct mtk_icc_node usb = {
169
+
.name = "usb",
170
+
.id = MASTER_USB,
171
+
.ep = 0,
172
+
.num_links = 1,
173
+
.links = { SLAVE_DDR_EMI }
174
+
};
175
+
176
+
static struct mtk_icc_node wifi = {
177
+
.name = "wifi",
178
+
.id = MASTER_WIFI,
179
+
.ep = 0,
180
+
.num_links = 1,
181
+
.links = { SLAVE_DDR_EMI }
182
+
};
183
+
184
+
static struct mtk_icc_node bt = {
185
+
.name = "bt",
186
+
.id = MASTER_BT,
187
+
.ep = 0,
188
+
.num_links = 1,
189
+
.links = { SLAVE_DDR_EMI }
190
+
};
191
+
192
+
static struct mtk_icc_node netsys = {
193
+
.name = "netsys",
194
+
.id = MASTER_NETSYS,
195
+
.ep = 0,
196
+
.num_links = 1,
197
+
.links = { SLAVE_DDR_EMI }
198
+
};
199
+
200
+
static struct mtk_icc_node dbgif = {
201
+
.name = "dbgif",
202
+
.id = MASTER_DBGIF,
203
+
.ep = 0,
204
+
.num_links = 1,
205
+
.links = { SLAVE_DDR_EMI }
206
+
};
207
+
208
+
static struct mtk_icc_node hrt_ddr_emi = {
209
+
.name = "hrt-ddr-emi",
210
+
.id = SLAVE_HRT_DDR_EMI,
211
+
.ep = 2,
212
+
};
213
+
214
+
static struct mtk_icc_node hrt_mmsys = {
215
+
.name = "hrt-mmsys",
216
+
.id = MASTER_HRT_MMSYS,
217
+
.ep = 0,
218
+
.num_links = 1,
219
+
.links = { SLAVE_HRT_DDR_EMI }
220
+
};
221
+
222
+
static struct mtk_icc_node hrt_mm_disp = {
223
+
.name = "hrt-mm-disp",
224
+
.id = MASTER_HRT_MM_DISP,
225
+
.ep = 0,
226
+
.num_links = 1,
227
+
.links = { MASTER_HRT_MMSYS }
228
+
};
229
+
230
+
static struct mtk_icc_node hrt_mm_vdec = {
231
+
.name = "hrt-mm-vdec",
232
+
.id = MASTER_HRT_MM_VDEC,
233
+
.ep = 0,
234
+
.num_links = 1,
235
+
.links = { MASTER_HRT_MMSYS }
236
+
};
237
+
238
+
static struct mtk_icc_node hrt_mm_venc = {
239
+
.name = "hrt-mm-venc",
240
+
.id = MASTER_HRT_MM_VENC,
241
+
.ep = 0,
242
+
.num_links = 1,
243
+
.links = { MASTER_HRT_MMSYS }
244
+
};
245
+
246
+
static struct mtk_icc_node hrt_mm_cam = {
247
+
.name = "hrt-mm-cam",
248
+
.id = MASTER_HRT_MM_CAM,
249
+
.ep = 0,
250
+
.num_links = 1,
251
+
.links = { MASTER_HRT_MMSYS }
252
+
};
253
+
254
+
static struct mtk_icc_node hrt_mm_img = {
255
+
.name = "hrt-mm-img",
256
+
.id = MASTER_HRT_MM_IMG,
257
+
.ep = 0,
258
+
.num_links = 1,
259
+
.links = { MASTER_HRT_MMSYS }
260
+
};
261
+
262
+
static struct mtk_icc_node hrt_mm_mdp = {
263
+
.name = "hrt-mm-mdp",
264
+
.id = MASTER_HRT_MM_MDP,
265
+
.ep = 0,
266
+
.num_links = 1,
267
+
.links = { MASTER_HRT_MMSYS }
268
+
};
269
+
270
+
static struct mtk_icc_node hrt_dbgif = {
271
+
.name = "hrt-dbgif",
272
+
.id = MASTER_HRT_DBGIF,
273
+
.ep = 0,
274
+
.num_links = 1,
275
+
.links = { SLAVE_HRT_DDR_EMI }
276
+
};
277
+
278
+
static struct mtk_icc_node *mt8195_emi_icc_nodes[] = {
279
+
[SLAVE_DDR_EMI] = &ddr_emi,
280
+
[MASTER_MCUSYS] = &mcusys,
281
+
[MASTER_GPUSYS] = &gpu,
282
+
[MASTER_MMSYS] = &mmsys,
283
+
[MASTER_MM_VPU] = &mm_vpu,
284
+
[MASTER_MM_DISP] = &mm_disp,
285
+
[MASTER_MM_VDEC] = &mm_vdec,
286
+
[MASTER_MM_VENC] = &mm_venc,
287
+
[MASTER_MM_CAM] = &mm_cam,
288
+
[MASTER_MM_IMG] = &mm_img,
289
+
[MASTER_MM_MDP] = &mm_mdp,
290
+
[MASTER_VPUSYS] = &vpusys,
291
+
[MASTER_VPU_0] = &vpu_port0,
292
+
[MASTER_VPU_1] = &vpu_port1,
293
+
[MASTER_MDLASYS] = &mdlasys,
294
+
[MASTER_MDLA_0] = &mdla_port0,
295
+
[MASTER_UFS] = &ufs,
296
+
[MASTER_PCIE_0] = &pcie0,
297
+
[MASTER_PCIE_1] = &pcie1,
298
+
[MASTER_USB] = &usb,
299
+
[MASTER_WIFI] = &wifi,
300
+
[MASTER_BT] = &bt,
301
+
[MASTER_NETSYS] = &netsys,
302
+
[MASTER_DBGIF] = &dbgif,
303
+
[SLAVE_HRT_DDR_EMI] = &hrt_ddr_emi,
304
+
[MASTER_HRT_MMSYS] = &hrt_mmsys,
305
+
[MASTER_HRT_MM_DISP] = &hrt_mm_disp,
306
+
[MASTER_HRT_MM_VDEC] = &hrt_mm_vdec,
307
+
[MASTER_HRT_MM_VENC] = &hrt_mm_venc,
308
+
[MASTER_HRT_MM_CAM] = &hrt_mm_cam,
309
+
[MASTER_HRT_MM_IMG] = &hrt_mm_img,
310
+
[MASTER_HRT_MM_MDP] = &hrt_mm_mdp,
311
+
[MASTER_HRT_DBGIF] = &hrt_dbgif
312
+
};
313
+
314
+
static struct mtk_icc_desc mt8195_emi_icc = {
315
+
.nodes = mt8195_emi_icc_nodes,
316
+
.num_nodes = ARRAY_SIZE(mt8195_emi_icc_nodes),
317
+
};
318
+
319
+
static const struct of_device_id mtk_mt8195_emi_icc_of_match[] = {
320
+
{ .compatible = "mediatek,mt8195-emi", .data = &mt8195_emi_icc },
321
+
{ /* sentinel */ },
322
+
};
323
+
MODULE_DEVICE_TABLE(of, mtk_mt8195_emi_icc_of_match);
324
+
325
+
static struct platform_driver mtk_emi_icc_mt8195_driver = {
326
+
.driver = {
327
+
.name = "emi-icc-mt8195",
328
+
.of_match_table = mtk_mt8195_emi_icc_of_match,
329
+
.sync_state = icc_sync_state,
330
+
},
331
+
.probe = mtk_emi_icc_probe,
332
+
.remove_new = mtk_emi_icc_remove,
333
+
334
+
};
335
+
module_platform_driver(mtk_emi_icc_mt8195_driver);
336
+
337
+
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
338
+
MODULE_DESCRIPTION("MediaTek MT8195 EMI ICC driver");
339
+
MODULE_LICENSE("GPL");
+23
include/dt-bindings/interconnect/mediatek,mt8183.h
+23
include/dt-bindings/interconnect/mediatek,mt8183.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
9
+
#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
10
+
11
+
#define SLAVE_DDR_EMI 0
12
+
#define MASTER_MCUSYS 1
13
+
#define MASTER_MFG 2
14
+
#define MASTER_MMSYS 3
15
+
#define MASTER_MM_VPU 4
16
+
#define MASTER_MM_DISP 5
17
+
#define MASTER_MM_VDEC 6
18
+
#define MASTER_MM_VENC 7
19
+
#define MASTER_MM_CAM 8
20
+
#define MASTER_MM_IMG 9
21
+
#define MASTER_MM_MDP 10
22
+
23
+
#endif
+44
include/dt-bindings/interconnect/mediatek,mt8195.h
+44
include/dt-bindings/interconnect/mediatek,mt8195.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2020 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
9
+
#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
10
+
11
+
#define SLAVE_DDR_EMI 0
12
+
#define MASTER_MCUSYS 1
13
+
#define MASTER_GPUSYS 2
14
+
#define MASTER_MMSYS 3
15
+
#define MASTER_MM_VPU 4
16
+
#define MASTER_MM_DISP 5
17
+
#define MASTER_MM_VDEC 6
18
+
#define MASTER_MM_VENC 7
19
+
#define MASTER_MM_CAM 8
20
+
#define MASTER_MM_IMG 9
21
+
#define MASTER_MM_MDP 10
22
+
#define MASTER_VPUSYS 11
23
+
#define MASTER_VPU_0 12
24
+
#define MASTER_VPU_1 13
25
+
#define MASTER_MDLASYS 14
26
+
#define MASTER_MDLA_0 15
27
+
#define MASTER_UFS 16
28
+
#define MASTER_PCIE_0 17
29
+
#define MASTER_PCIE_1 18
30
+
#define MASTER_USB 19
31
+
#define MASTER_DBGIF 20
32
+
#define SLAVE_HRT_DDR_EMI 21
33
+
#define MASTER_HRT_MMSYS 22
34
+
#define MASTER_HRT_MM_DISP 23
35
+
#define MASTER_HRT_MM_VDEC 24
36
+
#define MASTER_HRT_MM_VENC 25
37
+
#define MASTER_HRT_MM_CAM 26
38
+
#define MASTER_HRT_MM_IMG 27
39
+
#define MASTER_HRT_MM_MDP 28
40
+
#define MASTER_HRT_DBGIF 29
41
+
#define MASTER_WIFI 30
42
+
#define MASTER_BT 31
43
+
#define MASTER_NETSYS 32
44
+
#endif