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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel
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linux
drm/msm/dpu: drop rogue intr_tear_rd_ptr values
The commit 5a9d50150c2c ("drm/msm/dpu: shift IRQ indices by 1") shifted
IRQ indices by 1, making 'NO_IRQ' to be 0 rather than -1 (and allowing
to skip the definition if the IRQ is not present).
Several platform files were sketched before that commit, but got applied
afterwards. As such, they inherited historical (and currently incorrect)
setting of .intr_tear_rd_ptr = -1 for 'NO_IRQ' value.
Drop that setting for all the affected platforms.
Fixes: 62af6e1cb596 ("drm/msm/dpu: Add support for MSM8917")
Fixes: c079680bb0fa ("drm/msm/dpu: Add support for MSM8937")
Fixes: 7a6109ce1c2c ("drm/msm/dpu: Add support for MSM8953")
Fixes: daf9a92daeb8 ("drm/msm/dpu: Add support for MSM8996")
Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platforms")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/647486/
Link: https://lore.kernel.org/r/20250408-dpu-drop-intr-rd-ptr-v1-1-eeac337d88f8@oss.qualcomm.com
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
authored by Dmitry Baryshkov and committed by Abhinav Kumar ddfa00af 2a34496f
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
···
132
.prog_fetch_lines_worst_case = 14,
133
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
134
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
135
-
.intr_tear_rd_ptr = -1,
136
}, {
137
.name = "intf_2", .id = INTF_2,
138
.base = 0x6b000, .len = 0x268,
···
140
.prog_fetch_lines_worst_case = 14,
141
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
142
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
143
-
.intr_tear_rd_ptr = -1,
144
},
145
};
146
···
132
.prog_fetch_lines_worst_case = 14,
133
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
134
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
135
}, {
136
.name = "intf_2", .id = INTF_2,
137
.base = 0x6b000, .len = 0x268,
···
141
.prog_fetch_lines_worst_case = 14,
142
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
143
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
144
},
145
};
146
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
-3
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
-3
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
···
131
.prog_fetch_lines_worst_case = 14,
132
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
133
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
134
-
.intr_tear_rd_ptr = -1,
135
}, {
136
.name = "intf_1", .id = INTF_1,
137
.base = 0x6a800, .len = 0x268,
···
139
.prog_fetch_lines_worst_case = 14,
140
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
141
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
142
-
.intr_tear_rd_ptr = -1,
143
}, {
144
.name = "intf_2", .id = INTF_2,
145
.base = 0x6b000, .len = 0x268,
···
147
.prog_fetch_lines_worst_case = 14,
148
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
149
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
150
-
.intr_tear_rd_ptr = -1,
151
},
152
};
153
···
131
.prog_fetch_lines_worst_case = 14,
132
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
133
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
134
}, {
135
.name = "intf_1", .id = INTF_1,
136
.base = 0x6a800, .len = 0x268,
···
140
.prog_fetch_lines_worst_case = 14,
141
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
142
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
143
}, {
144
.name = "intf_2", .id = INTF_2,
145
.base = 0x6b000, .len = 0x268,
···
149
.prog_fetch_lines_worst_case = 14,
150
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
151
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
152
},
153
};
154
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
···
241
.prog_fetch_lines_worst_case = 25,
242
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
243
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
244
-
.intr_tear_rd_ptr = -1,
245
}, {
246
.name = "intf_1", .id = INTF_1,
247
.base = 0x6a800, .len = 0x268,
···
249
.prog_fetch_lines_worst_case = 25,
250
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
251
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
252
-
.intr_tear_rd_ptr = -1,
253
}, {
254
.name = "intf_2", .id = INTF_2,
255
.base = 0x6b000, .len = 0x268,
···
257
.prog_fetch_lines_worst_case = 25,
258
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
259
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
260
-
.intr_tear_rd_ptr = -1,
261
}, {
262
.name = "intf_3", .id = INTF_3,
263
.base = 0x6b800, .len = 0x268,
···
264
.prog_fetch_lines_worst_case = 25,
265
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
266
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
267
-
.intr_tear_rd_ptr = -1,
268
},
269
};
270
···
241
.prog_fetch_lines_worst_case = 25,
242
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
243
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
244
}, {
245
.name = "intf_1", .id = INTF_1,
246
.base = 0x6a800, .len = 0x268,
···
250
.prog_fetch_lines_worst_case = 25,
251
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
252
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
253
}, {
254
.name = "intf_2", .id = INTF_2,
255
.base = 0x6b000, .len = 0x268,
···
259
.prog_fetch_lines_worst_case = 25,
260
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
261
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
262
}, {
263
.name = "intf_3", .id = INTF_3,
264
.base = 0x6b800, .len = 0x268,
···
267
.prog_fetch_lines_worst_case = 25,
268
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
269
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
270
},
271
};
272
-3
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
-3
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
···
202
.prog_fetch_lines_worst_case = 21,
203
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
204
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
205
-
.intr_tear_rd_ptr = -1,
206
}, {
207
.name = "intf_1", .id = INTF_1,
208
.base = 0x6a800, .len = 0x280,
···
210
.prog_fetch_lines_worst_case = 21,
211
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
212
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
213
-
.intr_tear_rd_ptr = -1,
214
}, {
215
.name = "intf_2", .id = INTF_2,
216
.base = 0x6b000, .len = 0x280,
···
218
.prog_fetch_lines_worst_case = 21,
219
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
220
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
221
-
.intr_tear_rd_ptr = -1,
222
},
223
};
224
···
202
.prog_fetch_lines_worst_case = 21,
203
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
204
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
205
}, {
206
.name = "intf_1", .id = INTF_1,
207
.base = 0x6a800, .len = 0x280,
···
211
.prog_fetch_lines_worst_case = 21,
212
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
213
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
214
}, {
215
.name = "intf_2", .id = INTF_2,
216
.base = 0x6b000, .len = 0x280,
···
220
.prog_fetch_lines_worst_case = 21,
221
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
222
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
223
},
224
};
225
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
···
147
.prog_fetch_lines_worst_case = 21,
148
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
149
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
150
-
.intr_tear_rd_ptr = -1,
151
}, {
152
.name = "intf_1", .id = INTF_1,
153
.base = 0x6a800, .len = 0x280,
···
155
.prog_fetch_lines_worst_case = 21,
156
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
157
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
158
-
.intr_tear_rd_ptr = -1,
159
},
160
};
161
···
147
.prog_fetch_lines_worst_case = 21,
148
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
149
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
150
}, {
151
.name = "intf_1", .id = INTF_1,
152
.base = 0x6a800, .len = 0x280,
···
156
.prog_fetch_lines_worst_case = 21,
157
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
158
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
159
},
160
};
161